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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: cmpeqz_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i32 eq, q0, zr8; CHECK-NEXT: vpsel q0, q1, q09; CHECK-NEXT: bx lr10entry:11 %c1 = icmp eq <4 x i32> %a, zeroinitializer12 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>13 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b14 ret <4 x i32> %s15}16 17define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {18; CHECK-LABEL: cmpnez_v4i1:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vcmp.i32 eq, q0, zr21; CHECK-NEXT: vpsel q0, q1, q022; CHECK-NEXT: bx lr23entry:24 %c1 = icmp eq <4 x i32> %a, zeroinitializer25 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>26 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b27 ret <4 x i32> %s28}29 30define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {31; CHECK-LABEL: cmpsltz_v4i1:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vcmp.i32 eq, q0, zr34; CHECK-NEXT: vpsel q0, q1, q035; CHECK-NEXT: bx lr36entry:37 %c1 = icmp eq <4 x i32> %a, zeroinitializer38 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>39 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b40 ret <4 x i32> %s41}42 43define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {44; CHECK-LABEL: cmpsgtz_v4i1:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vcmp.i32 eq, q0, zr47; CHECK-NEXT: vpsel q0, q1, q048; CHECK-NEXT: bx lr49entry:50 %c1 = icmp eq <4 x i32> %a, zeroinitializer51 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>52 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b53 ret <4 x i32> %s54}55 56define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {57; CHECK-LABEL: cmpslez_v4i1:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vcmp.i32 eq, q0, zr60; CHECK-NEXT: vpsel q0, q1, q061; CHECK-NEXT: bx lr62entry:63 %c1 = icmp eq <4 x i32> %a, zeroinitializer64 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>65 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b66 ret <4 x i32> %s67}68 69define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {70; CHECK-LABEL: cmpsgez_v4i1:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vcmp.i32 eq, q0, zr73; CHECK-NEXT: vpsel q0, q1, q074; CHECK-NEXT: bx lr75entry:76 %c1 = icmp eq <4 x i32> %a, zeroinitializer77 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>78 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b79 ret <4 x i32> %s80}81 82define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {83; CHECK-LABEL: cmpultz_v4i1:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vcmp.i32 eq, q0, zr86; CHECK-NEXT: vpsel q0, q1, q087; CHECK-NEXT: bx lr88entry:89 %c1 = icmp eq <4 x i32> %a, zeroinitializer90 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>91 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b92 ret <4 x i32> %s93}94 95define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {96; CHECK-LABEL: cmpugtz_v4i1:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vcmp.i32 eq, q0, zr99; CHECK-NEXT: vpsel q0, q1, q0100; CHECK-NEXT: bx lr101entry:102 %c1 = icmp eq <4 x i32> %a, zeroinitializer103 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>104 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b105 ret <4 x i32> %s106}107 108define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {109; CHECK-LABEL: cmpulez_v4i1:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vcmp.i32 eq, q0, zr112; CHECK-NEXT: vpsel q0, q1, q0113; CHECK-NEXT: bx lr114entry:115 %c1 = icmp eq <4 x i32> %a, zeroinitializer116 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>117 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b118 ret <4 x i32> %s119}120 121define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {122; CHECK-LABEL: cmpugez_v4i1:123; CHECK: @ %bb.0: @ %entry124; CHECK-NEXT: vcmp.i32 eq, q0, zr125; CHECK-NEXT: vpsel q0, q1, q0126; CHECK-NEXT: bx lr127entry:128 %c1 = icmp eq <4 x i32> %a, zeroinitializer129 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>130 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b131 ret <4 x i32> %s132}133 134 135 136define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {137; CHECK-LABEL: cmpeq_v4i1:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vcmp.i32 eq, q0, zr140; CHECK-NEXT: vpsel q0, q1, q0141; CHECK-NEXT: bx lr142entry:143 %c1 = icmp eq <4 x i32> %a, zeroinitializer144 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>145 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b146 ret <4 x i32> %s147}148 149define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {150; CHECK-LABEL: cmpne_v4i1:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vcmp.i32 eq, q0, zr153; CHECK-NEXT: vpsel q0, q1, q0154; CHECK-NEXT: bx lr155entry:156 %c1 = icmp eq <4 x i32> %a, zeroinitializer157 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>158 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b159 ret <4 x i32> %s160}161 162define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {163; CHECK-LABEL: cmpslt_v4i1:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vcmp.i32 eq, q0, zr166; CHECK-NEXT: vpsel q0, q1, q0167; CHECK-NEXT: bx lr168entry:169 %c1 = icmp eq <4 x i32> %a, zeroinitializer170 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>171 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b172 ret <4 x i32> %s173}174 175define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {176; CHECK-LABEL: cmpsgt_v4i1:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: vcmp.i32 eq, q0, zr179; CHECK-NEXT: vpsel q0, q1, q0180; CHECK-NEXT: bx lr181entry:182 %c1 = icmp eq <4 x i32> %a, zeroinitializer183 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>184 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b185 ret <4 x i32> %s186}187 188define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {189; CHECK-LABEL: cmpsle_v4i1:190; CHECK: @ %bb.0: @ %entry191; CHECK-NEXT: vcmp.i32 eq, q0, zr192; CHECK-NEXT: vpsel q0, q1, q0193; CHECK-NEXT: bx lr194entry:195 %c1 = icmp eq <4 x i32> %a, zeroinitializer196 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>197 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b198 ret <4 x i32> %s199}200 201define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {202; CHECK-LABEL: cmpsge_v4i1:203; CHECK: @ %bb.0: @ %entry204; CHECK-NEXT: vcmp.i32 eq, q0, zr205; CHECK-NEXT: vpsel q0, q1, q0206; CHECK-NEXT: bx lr207entry:208 %c1 = icmp eq <4 x i32> %a, zeroinitializer209 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>210 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b211 ret <4 x i32> %s212}213 214define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {215; CHECK-LABEL: cmpult_v4i1:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vcmp.i32 eq, q0, zr218; CHECK-NEXT: vpsel q0, q1, q0219; CHECK-NEXT: bx lr220entry:221 %c1 = icmp eq <4 x i32> %a, zeroinitializer222 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>223 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b224 ret <4 x i32> %s225}226 227define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {228; CHECK-LABEL: cmpugt_v4i1:229; CHECK: @ %bb.0: @ %entry230; CHECK-NEXT: vcmp.i32 eq, q0, zr231; CHECK-NEXT: vpsel q0, q1, q0232; CHECK-NEXT: bx lr233entry:234 %c1 = icmp eq <4 x i32> %a, zeroinitializer235 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>236 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b237 ret <4 x i32> %s238}239 240define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {241; CHECK-LABEL: cmpule_v4i1:242; CHECK: @ %bb.0: @ %entry243; CHECK-NEXT: vcmp.i32 eq, q0, zr244; CHECK-NEXT: vpsel q0, q1, q0245; CHECK-NEXT: bx lr246entry:247 %c1 = icmp eq <4 x i32> %a, zeroinitializer248 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>249 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b250 ret <4 x i32> %s251}252 253define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {254; CHECK-LABEL: cmpuge_v4i1:255; CHECK: @ %bb.0: @ %entry256; CHECK-NEXT: vcmp.i32 eq, q0, zr257; CHECK-NEXT: vpsel q0, q1, q0258; CHECK-NEXT: bx lr259entry:260 %c1 = icmp eq <4 x i32> %a, zeroinitializer261 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1>262 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b263 ret <4 x i32> %s264}265 266 267 268 269define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {270; CHECK-LABEL: cmpeqz_v8i1:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vcmp.i16 eq, q0, zr273; CHECK-NEXT: vpsel q0, q1, q0274; CHECK-NEXT: bx lr275entry:276 %c1 = icmp eq <8 x i16> %a, zeroinitializer277 %o = xor <8 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>278 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b279 ret <8 x i16> %s280}281 282define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {283; CHECK-LABEL: cmpeq_v8i1:284; CHECK: @ %bb.0: @ %entry285; CHECK-NEXT: vcmp.i16 eq, q0, zr286; CHECK-NEXT: vpsel q0, q1, q0287; CHECK-NEXT: bx lr288entry:289 %c1 = icmp eq <8 x i16> %a, zeroinitializer290 %o = xor <8 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>291 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b292 ret <8 x i16> %s293}294 295 296define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {297; CHECK-LABEL: cmpeqz_v16i1:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vcmp.i8 eq, q0, zr300; CHECK-NEXT: vpsel q0, q1, q0301; CHECK-NEXT: bx lr302entry:303 %c1 = icmp eq <16 x i8> %a, zeroinitializer304 %o = xor <16 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>305 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b306 ret <16 x i8> %s307}308 309define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {310; CHECK-LABEL: cmpeq_v16i1:311; CHECK: @ %bb.0: @ %entry312; CHECK-NEXT: vcmp.i8 eq, q0, zr313; CHECK-NEXT: vpsel q0, q1, q0314; CHECK-NEXT: bx lr315entry:316 %c1 = icmp eq <16 x i8> %a, zeroinitializer317 %o = xor <16 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>318 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b319 ret <16 x i8> %s320}321 322 323define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {324; CHECK-LABEL: cmpeqz_v2i1:325; CHECK: @ %bb.0: @ %entry326; CHECK-NEXT: vmov r0, r1, d0327; CHECK-NEXT: orrs r0, r1328; CHECK-NEXT: mov.w r1, #0329; CHECK-NEXT: csetm r0, eq330; CHECK-NEXT: bfi r1, r0, #0, #8331; CHECK-NEXT: vmov r0, r2, d1332; CHECK-NEXT: orrs r0, r2333; CHECK-NEXT: csetm r0, eq334; CHECK-NEXT: bfi r1, r0, #8, #8335; CHECK-NEXT: vmsr p0, r1336; CHECK-NEXT: vpsel q0, q1, q0337; CHECK-NEXT: bx lr338entry:339 %c1 = icmp eq <2 x i64> %a, zeroinitializer340 %o = xor <2 x i1> %c1, <i1 -1, i1 -1>341 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b342 ret <2 x i64> %s343}344 345define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {346; CHECK-LABEL: cmpeq_v2i1:347; CHECK: @ %bb.0: @ %entry348; CHECK-NEXT: vmov r0, r1, d0349; CHECK-NEXT: orrs r0, r1350; CHECK-NEXT: mov.w r1, #0351; CHECK-NEXT: csetm r0, eq352; CHECK-NEXT: bfi r1, r0, #0, #8353; CHECK-NEXT: vmov r0, r2, d1354; CHECK-NEXT: orrs r0, r2355; CHECK-NEXT: csetm r0, eq356; CHECK-NEXT: bfi r1, r0, #8, #8357; CHECK-NEXT: vmsr p0, r1358; CHECK-NEXT: vpsel q0, q1, q0359; CHECK-NEXT: bx lr360entry:361 %c1 = icmp eq <2 x i64> %a, zeroinitializer362 %o = xor <2 x i1> %c1, <i1 -1, i1 -1>363 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b364 ret <2 x i64> %s365}366 367define arm_aapcs_vfpcc <4 x i32> @vpnot_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {368; CHECK-LABEL: vpnot_v4i1:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: vpte.s32 lt, q0, zr371; CHECK-NEXT: vcmpt.s32 gt, q1, zr372; CHECK-NEXT: vcmpe.i32 eq, q2, zr373; CHECK-NEXT: vpsel q0, q0, q1374; CHECK-NEXT: bx lr375entry:376 %c1 = icmp slt <4 x i32> %a, zeroinitializer377 %c2 = icmp sgt <4 x i32> %b, zeroinitializer378 %c3 = icmp eq <4 x i32> %c, zeroinitializer379 %o1 = and <4 x i1> %c1, %c2380 %o2 = xor <4 x i1> %o1, <i1 -1, i1 -1, i1 -1, i1 -1>381 %o = and <4 x i1> %c3, %o2382 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b383 ret <4 x i32> %s384}385 386declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>)387declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)388 389define arm_aapcs_vfpcc <4 x i32> @vpttet_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {390; CHECK-LABEL: vpttet_v4i1:391; CHECK: @ %bb.0: @ %entry392; CHECK-NEXT: vpttet.s32 ge, q0, q2393; CHECK-NEXT: vmovt q0, q2394; CHECK-NEXT: vmovt q0, q2395; CHECK-NEXT: vmove q0, q2396; CHECK-NEXT: vmovt q0, q2397; CHECK-NEXT: bx lr398entry:399 %0 = icmp sge <4 x i32> %x, %z400 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %0, <4 x i32> %x)401 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %0, <4 x i32> %1)402 %3 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>403 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %3, <4 x i32> %2)404 %5 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true>405 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %5, <4 x i32> %4)406 ret <4 x i32> %6407}408 409define arm_aapcs_vfpcc <4 x i32> @vpttee_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {410; CHECK-LABEL: vpttee_v4i1:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vmov q3, q2413; CHECK-NEXT: vpttee.s32 ge, q0, q2414; CHECK-NEXT: vmaxt.s32 q3, q0, q1415; CHECK-NEXT: vcmpt.s32 gt, q0, zr416; CHECK-NEXT: vmove q3, q2417; CHECK-NEXT: vmove q3, q2418; CHECK-NEXT: vmov q0, q3419; CHECK-NEXT: bx lr420entry:421 %0 = icmp sge <4 x i32> %x, %z422 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z)423 %2 = icmp sgt <4 x i32> %x, zeroinitializer424 %3 = and <4 x i1> %0, %2425 %4 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true>426 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %4, <4 x i32> %1)427 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %4, <4 x i32> %5)428 ret <4 x i32> %6429}430 431define arm_aapcs_vfpcc <4 x i32> @vpttee2_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {432; CHECK-LABEL: vpttee2_v4i1:433; CHECK: @ %bb.0: @ %entry434; CHECK-NEXT: vmov q3, q2435; CHECK-NEXT: vpttee.s32 ge, q0, q2436; CHECK-NEXT: vmaxt.s32 q3, q0, q1437; CHECK-NEXT: vcmpt.s32 gt, q0, zr438; CHECK-NEXT: vcmpe.s32 gt, q1, zr439; CHECK-NEXT: vmove q3, q2440; CHECK-NEXT: vmov q0, q3441; CHECK-NEXT: bx lr442entry:443 %0 = icmp sge <4 x i32> %x, %z444 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z)445 %2 = icmp sgt <4 x i32> %x, zeroinitializer446 %3 = and <4 x i1> %0, %2447 %4 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true>448 %5 = icmp sgt <4 x i32> %y, zeroinitializer449 %6 = and <4 x i1> %5, %4450 %7 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %6, <4 x i32> %1)451 ret <4 x i32> %7452}453 454define arm_aapcs_vfpcc <4 x i32> @vpttte_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {455; CHECK-LABEL: vpttte_v4i1:456; CHECK: @ %bb.0: @ %entry457; CHECK-NEXT: vmov q3, q2458; CHECK-NEXT: vpttte.s32 ge, q0, q2459; CHECK-NEXT: vmaxt.s32 q3, q0, q1460; CHECK-NEXT: vcmpt.s32 gt, q0, zr461; CHECK-NEXT: vmovt q3, q2462; CHECK-NEXT: vmove q3, q2463; CHECK-NEXT: vmov q0, q3464; CHECK-NEXT: bx lr465entry:466 %0 = icmp sge <4 x i32> %x, %z467 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z)468 %2 = icmp sgt <4 x i32> %x, zeroinitializer469 %3 = and <4 x i1> %0, %2470 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %3, <4 x i32> %1)471 %5 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true>472 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %5, <4 x i32> %4)473 ret <4 x i32> %6474}475