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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: cmpeqz_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vpt.i32 ne, q0, zr8; CHECK-NEXT: vcmpt.i32 ne, q1, zr9; CHECK-NEXT: vpsel q0, q1, q010; CHECK-NEXT: bx lr11entry:12 %c1 = icmp eq <4 x i32> %a, zeroinitializer13 %c2 = icmp eq <4 x i32> %b, zeroinitializer14 %o = or <4 x i1> %c1, %c215 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b16 ret <4 x i32> %s17}18 19define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {20; CHECK-LABEL: cmpnez_v4i1:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vpt.i32 ne, q0, zr23; CHECK-NEXT: vcmpt.i32 eq, q1, zr24; CHECK-NEXT: vpsel q0, q1, q025; CHECK-NEXT: bx lr26entry:27 %c1 = icmp eq <4 x i32> %a, zeroinitializer28 %c2 = icmp ne <4 x i32> %b, zeroinitializer29 %o = or <4 x i1> %c1, %c230 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b31 ret <4 x i32> %s32}33 34define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {35; CHECK-LABEL: cmpsltz_v4i1:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vpt.i32 ne, q0, zr38; CHECK-NEXT: vcmpt.s32 ge, q1, zr39; CHECK-NEXT: vpsel q0, q1, q040; CHECK-NEXT: bx lr41entry:42 %c1 = icmp eq <4 x i32> %a, zeroinitializer43 %c2 = icmp slt <4 x i32> %b, zeroinitializer44 %o = or <4 x i1> %c1, %c245 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b46 ret <4 x i32> %s47}48 49define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {50; CHECK-LABEL: cmpsgtz_v4i1:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: vpt.i32 ne, q0, zr53; CHECK-NEXT: vcmpt.s32 le, q1, zr54; CHECK-NEXT: vpsel q0, q1, q055; CHECK-NEXT: bx lr56entry:57 %c1 = icmp eq <4 x i32> %a, zeroinitializer58 %c2 = icmp sgt <4 x i32> %b, zeroinitializer59 %o = or <4 x i1> %c1, %c260 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b61 ret <4 x i32> %s62}63 64define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {65; CHECK-LABEL: cmpslez_v4i1:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vpt.i32 ne, q0, zr68; CHECK-NEXT: vcmpt.s32 gt, q1, zr69; CHECK-NEXT: vpsel q0, q1, q070; CHECK-NEXT: bx lr71entry:72 %c1 = icmp eq <4 x i32> %a, zeroinitializer73 %c2 = icmp sle <4 x i32> %b, zeroinitializer74 %o = or <4 x i1> %c1, %c275 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b76 ret <4 x i32> %s77}78 79define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {80; CHECK-LABEL: cmpsgez_v4i1:81; CHECK: @ %bb.0: @ %entry82; CHECK-NEXT: vpt.i32 ne, q0, zr83; CHECK-NEXT: vcmpt.s32 lt, q1, zr84; CHECK-NEXT: vpsel q0, q1, q085; CHECK-NEXT: bx lr86entry:87 %c1 = icmp eq <4 x i32> %a, zeroinitializer88 %c2 = icmp sge <4 x i32> %b, zeroinitializer89 %o = or <4 x i1> %c1, %c290 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b91 ret <4 x i32> %s92}93 94define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {95; CHECK-LABEL: cmpultz_v4i1:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vcmp.i32 eq, q0, zr98; CHECK-NEXT: vpsel q0, q0, q199; CHECK-NEXT: bx lr100entry:101 %c1 = icmp eq <4 x i32> %a, zeroinitializer102 %c2 = icmp ult <4 x i32> %b, zeroinitializer103 %o = or <4 x i1> %c1, %c2104 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b105 ret <4 x i32> %s106}107 108define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {109; CHECK-LABEL: cmpugtz_v4i1:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vpt.i32 ne, q0, zr112; CHECK-NEXT: vcmpt.i32 eq, q1, zr113; CHECK-NEXT: vpsel q0, q1, q0114; CHECK-NEXT: bx lr115entry:116 %c1 = icmp eq <4 x i32> %a, zeroinitializer117 %c2 = icmp ugt <4 x i32> %b, zeroinitializer118 %o = or <4 x i1> %c1, %c2119 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b120 ret <4 x i32> %s121}122 123define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {124; CHECK-LABEL: cmpulez_v4i1:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vmov.i32 q2, #0x0127; CHECK-NEXT: vcmp.u32 cs, q2, q1128; CHECK-NEXT: vpnot129; CHECK-NEXT: vpst130; CHECK-NEXT: vcmpt.i32 ne, q0, zr131; CHECK-NEXT: vpsel q0, q1, q0132; CHECK-NEXT: bx lr133entry:134 %c1 = icmp eq <4 x i32> %a, zeroinitializer135 %c2 = icmp ule <4 x i32> %b, zeroinitializer136 %o = or <4 x i1> %c1, %c2137 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b138 ret <4 x i32> %s139}140 141define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {142; CHECK-LABEL: cmpugez_v4i1:143; CHECK: @ %bb.0: @ %entry144; CHECK-NEXT: bx lr145entry:146 %c1 = icmp eq <4 x i32> %a, zeroinitializer147 %c2 = icmp uge <4 x i32> %b, zeroinitializer148 %o = or <4 x i1> %c1, %c2149 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b150 ret <4 x i32> %s151}152 153 154 155define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {156; CHECK-LABEL: cmpeq_v4i1:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: vpt.i32 ne, q0, zr159; CHECK-NEXT: vcmpt.i32 ne, q1, q2160; CHECK-NEXT: vpsel q0, q1, q0161; CHECK-NEXT: bx lr162entry:163 %c1 = icmp eq <4 x i32> %a, zeroinitializer164 %c2 = icmp eq <4 x i32> %b, %c165 %o = or <4 x i1> %c1, %c2166 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b167 ret <4 x i32> %s168}169 170define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {171; CHECK-LABEL: cmpne_v4i1:172; CHECK: @ %bb.0: @ %entry173; CHECK-NEXT: vpt.i32 ne, q0, zr174; CHECK-NEXT: vcmpt.i32 eq, q1, q2175; CHECK-NEXT: vpsel q0, q1, q0176; CHECK-NEXT: bx lr177entry:178 %c1 = icmp eq <4 x i32> %a, zeroinitializer179 %c2 = icmp ne <4 x i32> %b, %c180 %o = or <4 x i1> %c1, %c2181 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b182 ret <4 x i32> %s183}184 185define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {186; CHECK-LABEL: cmpslt_v4i1:187; CHECK: @ %bb.0: @ %entry188; CHECK-NEXT: vpt.i32 ne, q0, zr189; CHECK-NEXT: vcmpt.s32 le, q2, q1190; CHECK-NEXT: vpsel q0, q1, q0191; CHECK-NEXT: bx lr192entry:193 %c1 = icmp eq <4 x i32> %a, zeroinitializer194 %c2 = icmp slt <4 x i32> %b, %c195 %o = or <4 x i1> %c1, %c2196 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b197 ret <4 x i32> %s198}199 200define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {201; CHECK-LABEL: cmpsgt_v4i1:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vpt.i32 ne, q0, zr204; CHECK-NEXT: vcmpt.s32 le, q1, q2205; CHECK-NEXT: vpsel q0, q1, q0206; CHECK-NEXT: bx lr207entry:208 %c1 = icmp eq <4 x i32> %a, zeroinitializer209 %c2 = icmp sgt <4 x i32> %b, %c210 %o = or <4 x i1> %c1, %c2211 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b212 ret <4 x i32> %s213}214 215define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {216; CHECK-LABEL: cmpsle_v4i1:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: vpt.i32 ne, q0, zr219; CHECK-NEXT: vcmpt.s32 lt, q2, q1220; CHECK-NEXT: vpsel q0, q1, q0221; CHECK-NEXT: bx lr222entry:223 %c1 = icmp eq <4 x i32> %a, zeroinitializer224 %c2 = icmp sle <4 x i32> %b, %c225 %o = or <4 x i1> %c1, %c2226 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b227 ret <4 x i32> %s228}229 230define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {231; CHECK-LABEL: cmpsge_v4i1:232; CHECK: @ %bb.0: @ %entry233; CHECK-NEXT: vpt.i32 ne, q0, zr234; CHECK-NEXT: vcmpt.s32 lt, q1, q2235; CHECK-NEXT: vpsel q0, q1, q0236; CHECK-NEXT: bx lr237entry:238 %c1 = icmp eq <4 x i32> %a, zeroinitializer239 %c2 = icmp sge <4 x i32> %b, %c240 %o = or <4 x i1> %c1, %c2241 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b242 ret <4 x i32> %s243}244 245define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {246; CHECK-LABEL: cmpult_v4i1:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vcmp.u32 hi, q2, q1249; CHECK-NEXT: vpnot250; CHECK-NEXT: vpst251; CHECK-NEXT: vcmpt.i32 ne, q0, zr252; CHECK-NEXT: vpsel q0, q1, q0253; CHECK-NEXT: bx lr254entry:255 %c1 = icmp eq <4 x i32> %a, zeroinitializer256 %c2 = icmp ult <4 x i32> %b, %c257 %o = or <4 x i1> %c1, %c2258 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b259 ret <4 x i32> %s260}261 262define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {263; CHECK-LABEL: cmpugt_v4i1:264; CHECK: @ %bb.0: @ %entry265; CHECK-NEXT: vcmp.u32 hi, q1, q2266; CHECK-NEXT: vpnot267; CHECK-NEXT: vpst268; CHECK-NEXT: vcmpt.i32 ne, q0, zr269; CHECK-NEXT: vpsel q0, q1, q0270; CHECK-NEXT: bx lr271entry:272 %c1 = icmp eq <4 x i32> %a, zeroinitializer273 %c2 = icmp ugt <4 x i32> %b, %c274 %o = or <4 x i1> %c1, %c2275 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b276 ret <4 x i32> %s277}278 279define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {280; CHECK-LABEL: cmpule_v4i1:281; CHECK: @ %bb.0: @ %entry282; CHECK-NEXT: vcmp.u32 cs, q2, q1283; CHECK-NEXT: vpnot284; CHECK-NEXT: vpst285; CHECK-NEXT: vcmpt.i32 ne, q0, zr286; CHECK-NEXT: vpsel q0, q1, q0287; CHECK-NEXT: bx lr288entry:289 %c1 = icmp eq <4 x i32> %a, zeroinitializer290 %c2 = icmp ule <4 x i32> %b, %c291 %o = or <4 x i1> %c1, %c2292 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b293 ret <4 x i32> %s294}295 296define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {297; CHECK-LABEL: cmpuge_v4i1:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vcmp.u32 cs, q1, q2300; CHECK-NEXT: vpnot301; CHECK-NEXT: vpst302; CHECK-NEXT: vcmpt.i32 ne, q0, zr303; CHECK-NEXT: vpsel q0, q1, q0304; CHECK-NEXT: bx lr305entry:306 %c1 = icmp eq <4 x i32> %a, zeroinitializer307 %c2 = icmp uge <4 x i32> %b, %c308 %o = or <4 x i1> %c1, %c2309 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b310 ret <4 x i32> %s311}312 313 314 315 316define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {317; CHECK-LABEL: cmpeqz_v8i1:318; CHECK: @ %bb.0: @ %entry319; CHECK-NEXT: vpt.i16 ne, q0, zr320; CHECK-NEXT: vcmpt.i16 ne, q1, zr321; CHECK-NEXT: vpsel q0, q1, q0322; CHECK-NEXT: bx lr323entry:324 %c1 = icmp eq <8 x i16> %a, zeroinitializer325 %c2 = icmp eq <8 x i16> %b, zeroinitializer326 %o = or <8 x i1> %c1, %c2327 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b328 ret <8 x i16> %s329}330 331define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {332; CHECK-LABEL: cmpeq_v8i1:333; CHECK: @ %bb.0: @ %entry334; CHECK-NEXT: vpt.i16 ne, q0, zr335; CHECK-NEXT: vcmpt.i16 ne, q1, q2336; CHECK-NEXT: vpsel q0, q1, q0337; CHECK-NEXT: bx lr338entry:339 %c1 = icmp eq <8 x i16> %a, zeroinitializer340 %c2 = icmp eq <8 x i16> %b, %c341 %o = or <8 x i1> %c1, %c2342 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b343 ret <8 x i16> %s344}345 346 347define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {348; CHECK-LABEL: cmpeqz_v16i1:349; CHECK: @ %bb.0: @ %entry350; CHECK-NEXT: vpt.i8 ne, q0, zr351; CHECK-NEXT: vcmpt.i8 ne, q1, zr352; CHECK-NEXT: vpsel q0, q1, q0353; CHECK-NEXT: bx lr354entry:355 %c1 = icmp eq <16 x i8> %a, zeroinitializer356 %c2 = icmp eq <16 x i8> %b, zeroinitializer357 %o = or <16 x i1> %c1, %c2358 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b359 ret <16 x i8> %s360}361 362define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {363; CHECK-LABEL: cmpeq_v16i1:364; CHECK: @ %bb.0: @ %entry365; CHECK-NEXT: vpt.i8 ne, q0, zr366; CHECK-NEXT: vcmpt.i8 ne, q1, q2367; CHECK-NEXT: vpsel q0, q1, q0368; CHECK-NEXT: bx lr369entry:370 %c1 = icmp eq <16 x i8> %a, zeroinitializer371 %c2 = icmp eq <16 x i8> %b, %c372 %o = or <16 x i1> %c1, %c2373 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b374 ret <16 x i8> %s375}376 377 378define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {379; CHECK-LABEL: cmpeqz_v2i1:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: vmov r0, r1, d2382; CHECK-NEXT: orrs r0, r1383; CHECK-NEXT: vmov r1, r2, d0384; CHECK-NEXT: cset r0, eq385; CHECK-NEXT: orrs r1, r2386; CHECK-NEXT: csinc r0, r0, zr, ne387; CHECK-NEXT: movs r1, #0388; CHECK-NEXT: rsbs r0, r0, #0389; CHECK-NEXT: bfi r1, r0, #0, #8390; CHECK-NEXT: vmov r0, r2, d3391; CHECK-NEXT: orrs r0, r2392; CHECK-NEXT: vmov r2, r3, d1393; CHECK-NEXT: cset r0, eq394; CHECK-NEXT: orrs r2, r3395; CHECK-NEXT: csinc r0, r0, zr, ne396; CHECK-NEXT: rsbs r0, r0, #0397; CHECK-NEXT: bfi r1, r0, #8, #8398; CHECK-NEXT: vmsr p0, r1399; CHECK-NEXT: vpsel q0, q0, q1400; CHECK-NEXT: bx lr401entry:402 %c1 = icmp eq <2 x i64> %a, zeroinitializer403 %c2 = icmp eq <2 x i64> %b, zeroinitializer404 %o = or <2 x i1> %c1, %c2405 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b406 ret <2 x i64> %s407}408 409define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {410; CHECK-LABEL: cmpeq_v2i1:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vmov r0, r1, d4413; CHECK-NEXT: vmov r2, r3, d2414; CHECK-NEXT: eors r1, r3415; CHECK-NEXT: eors r0, r2416; CHECK-NEXT: orrs r0, r1417; CHECK-NEXT: vmov r1, r2, d0418; CHECK-NEXT: cset r0, eq419; CHECK-NEXT: orrs r1, r2420; CHECK-NEXT: vmov r12, r2, d5421; CHECK-NEXT: csinc r0, r0, zr, ne422; CHECK-NEXT: movs r1, #0423; CHECK-NEXT: rsbs r0, r0, #0424; CHECK-NEXT: bfi r1, r0, #0, #8425; CHECK-NEXT: vmov r3, r0, d3426; CHECK-NEXT: eors r0, r2427; CHECK-NEXT: eor.w r2, r3, r12428; CHECK-NEXT: orrs r0, r2429; CHECK-NEXT: vmov r2, r3, d1430; CHECK-NEXT: cset r0, eq431; CHECK-NEXT: orrs r2, r3432; CHECK-NEXT: csinc r0, r0, zr, ne433; CHECK-NEXT: rsbs r0, r0, #0434; CHECK-NEXT: bfi r1, r0, #8, #8435; CHECK-NEXT: vmsr p0, r1436; CHECK-NEXT: vpsel q0, q0, q1437; CHECK-NEXT: bx lr438entry:439 %c1 = icmp eq <2 x i64> %a, zeroinitializer440 %c2 = icmp eq <2 x i64> %b, %c441 %o = or <2 x i1> %c1, %c2442 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b443 ret <2 x i64> %s444}445 446 447