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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc <4 x i32> @add_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {5; CHECK-LABEL: add_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vpt.i32 eq, q0, zr8; CHECK-NEXT: vaddt.i32 q0, q1, q29; CHECK-NEXT: bx lr10entry:11 %c = icmp eq <4 x i32> %z, zeroinitializer12 %a = add <4 x i32> %x, %y13 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z14 ret <4 x i32> %b15}16 17define arm_aapcs_vfpcc <8 x i16> @add_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {18; CHECK-LABEL: add_v8i16:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vpt.i16 eq, q0, zr21; CHECK-NEXT: vaddt.i16 q0, q1, q222; CHECK-NEXT: bx lr23entry:24 %c = icmp eq <8 x i16> %z, zeroinitializer25 %a = add <8 x i16> %x, %y26 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z27 ret <8 x i16> %b28}29 30define arm_aapcs_vfpcc <16 x i8> @add_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {31; CHECK-LABEL: add_v16i8:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vpt.i8 eq, q0, zr34; CHECK-NEXT: vaddt.i8 q0, q1, q235; CHECK-NEXT: bx lr36entry:37 %c = icmp eq <16 x i8> %z, zeroinitializer38 %a = add <16 x i8> %x, %y39 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z40 ret <16 x i8> %b41}42 43define arm_aapcs_vfpcc <4 x i32> @sub_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {44; CHECK-LABEL: sub_v4i32:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vpt.i32 eq, q0, zr47; CHECK-NEXT: vsubt.i32 q0, q1, q248; CHECK-NEXT: bx lr49entry:50 %c = icmp eq <4 x i32> %z, zeroinitializer51 %a = sub <4 x i32> %x, %y52 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z53 ret <4 x i32> %b54}55 56define arm_aapcs_vfpcc <8 x i16> @sub_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {57; CHECK-LABEL: sub_v8i16:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vpt.i16 eq, q0, zr60; CHECK-NEXT: vsubt.i16 q0, q1, q261; CHECK-NEXT: bx lr62entry:63 %c = icmp eq <8 x i16> %z, zeroinitializer64 %a = sub <8 x i16> %x, %y65 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z66 ret <8 x i16> %b67}68 69define arm_aapcs_vfpcc <16 x i8> @sub_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {70; CHECK-LABEL: sub_v16i8:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vpt.i8 eq, q0, zr73; CHECK-NEXT: vsubt.i8 q0, q1, q274; CHECK-NEXT: bx lr75entry:76 %c = icmp eq <16 x i8> %z, zeroinitializer77 %a = sub <16 x i8> %x, %y78 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z79 ret <16 x i8> %b80}81 82define arm_aapcs_vfpcc <4 x i32> @mul_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {83; CHECK-LABEL: mul_v4i32:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vpt.i32 eq, q0, zr86; CHECK-NEXT: vmult.i32 q0, q1, q287; CHECK-NEXT: bx lr88entry:89 %c = icmp eq <4 x i32> %z, zeroinitializer90 %a = mul <4 x i32> %x, %y91 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z92 ret <4 x i32> %b93}94 95define arm_aapcs_vfpcc <8 x i16> @mul_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {96; CHECK-LABEL: mul_v8i16:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vpt.i16 eq, q0, zr99; CHECK-NEXT: vmult.i16 q0, q1, q2100; CHECK-NEXT: bx lr101entry:102 %c = icmp eq <8 x i16> %z, zeroinitializer103 %a = mul <8 x i16> %x, %y104 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z105 ret <8 x i16> %b106}107 108define arm_aapcs_vfpcc <16 x i8> @mul_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {109; CHECK-LABEL: mul_v16i8:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vpt.i8 eq, q0, zr112; CHECK-NEXT: vmult.i8 q0, q1, q2113; CHECK-NEXT: bx lr114entry:115 %c = icmp eq <16 x i8> %z, zeroinitializer116 %a = mul <16 x i8> %x, %y117 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z118 ret <16 x i8> %b119}120 121define arm_aapcs_vfpcc <4 x i32> @and_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {122; CHECK-LABEL: and_v4i32:123; CHECK: @ %bb.0: @ %entry124; CHECK-NEXT: vpt.i32 eq, q0, zr125; CHECK-NEXT: vandt q0, q1, q2126; CHECK-NEXT: bx lr127entry:128 %c = icmp eq <4 x i32> %z, zeroinitializer129 %a = and <4 x i32> %x, %y130 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z131 ret <4 x i32> %b132}133 134define arm_aapcs_vfpcc <8 x i16> @and_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {135; CHECK-LABEL: and_v8i16:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vpt.i16 eq, q0, zr138; CHECK-NEXT: vandt q0, q1, q2139; CHECK-NEXT: bx lr140entry:141 %c = icmp eq <8 x i16> %z, zeroinitializer142 %a = and <8 x i16> %x, %y143 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z144 ret <8 x i16> %b145}146 147define arm_aapcs_vfpcc <16 x i8> @and_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {148; CHECK-LABEL: and_v16i8:149; CHECK: @ %bb.0: @ %entry150; CHECK-NEXT: vpt.i8 eq, q0, zr151; CHECK-NEXT: vandt q0, q1, q2152; CHECK-NEXT: bx lr153entry:154 %c = icmp eq <16 x i8> %z, zeroinitializer155 %a = and <16 x i8> %x, %y156 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z157 ret <16 x i8> %b158}159 160define arm_aapcs_vfpcc <4 x i32> @or_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {161; CHECK-LABEL: or_v4i32:162; CHECK: @ %bb.0: @ %entry163; CHECK-NEXT: vpt.i32 eq, q0, zr164; CHECK-NEXT: vorrt q0, q1, q2165; CHECK-NEXT: bx lr166entry:167 %c = icmp eq <4 x i32> %z, zeroinitializer168 %a = or <4 x i32> %x, %y169 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z170 ret <4 x i32> %b171}172 173define arm_aapcs_vfpcc <8 x i16> @or_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {174; CHECK-LABEL: or_v8i16:175; CHECK: @ %bb.0: @ %entry176; CHECK-NEXT: vpt.i16 eq, q0, zr177; CHECK-NEXT: vorrt q0, q1, q2178; CHECK-NEXT: bx lr179entry:180 %c = icmp eq <8 x i16> %z, zeroinitializer181 %a = or <8 x i16> %x, %y182 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z183 ret <8 x i16> %b184}185 186define arm_aapcs_vfpcc <16 x i8> @or_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {187; CHECK-LABEL: or_v16i8:188; CHECK: @ %bb.0: @ %entry189; CHECK-NEXT: vpt.i8 eq, q0, zr190; CHECK-NEXT: vorrt q0, q1, q2191; CHECK-NEXT: bx lr192entry:193 %c = icmp eq <16 x i8> %z, zeroinitializer194 %a = or <16 x i8> %x, %y195 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z196 ret <16 x i8> %b197}198 199define arm_aapcs_vfpcc <4 x i32> @xor_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {200; CHECK-LABEL: xor_v4i32:201; CHECK: @ %bb.0: @ %entry202; CHECK-NEXT: vpt.i32 eq, q0, zr203; CHECK-NEXT: veort q0, q1, q2204; CHECK-NEXT: bx lr205entry:206 %c = icmp eq <4 x i32> %z, zeroinitializer207 %a = xor <4 x i32> %x, %y208 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z209 ret <4 x i32> %b210}211 212define arm_aapcs_vfpcc <8 x i16> @xor_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {213; CHECK-LABEL: xor_v8i16:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vpt.i16 eq, q0, zr216; CHECK-NEXT: veort q0, q1, q2217; CHECK-NEXT: bx lr218entry:219 %c = icmp eq <8 x i16> %z, zeroinitializer220 %a = xor <8 x i16> %x, %y221 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z222 ret <8 x i16> %b223}224 225define arm_aapcs_vfpcc <16 x i8> @xor_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {226; CHECK-LABEL: xor_v16i8:227; CHECK: @ %bb.0: @ %entry228; CHECK-NEXT: vpt.i8 eq, q0, zr229; CHECK-NEXT: veort q0, q1, q2230; CHECK-NEXT: bx lr231entry:232 %c = icmp eq <16 x i8> %z, zeroinitializer233 %a = xor <16 x i8> %x, %y234 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z235 ret <16 x i8> %b236}237 238define arm_aapcs_vfpcc <4 x i32> @shl_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {239; CHECK-LABEL: shl_v4i32:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vpt.i32 eq, q0, zr242; CHECK-NEXT: vshlt.u32 q0, q1, q2243; CHECK-NEXT: bx lr244entry:245 %c = icmp eq <4 x i32> %z, zeroinitializer246 %a = shl <4 x i32> %x, %y247 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z248 ret <4 x i32> %b249}250 251define arm_aapcs_vfpcc <8 x i16> @shl_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {252; CHECK-LABEL: shl_v8i16:253; CHECK: @ %bb.0: @ %entry254; CHECK-NEXT: vpt.i16 eq, q0, zr255; CHECK-NEXT: vshlt.u16 q0, q1, q2256; CHECK-NEXT: bx lr257entry:258 %c = icmp eq <8 x i16> %z, zeroinitializer259 %a = shl <8 x i16> %x, %y260 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z261 ret <8 x i16> %b262}263 264define arm_aapcs_vfpcc <16 x i8> @shl_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {265; CHECK-LABEL: shl_v16i8:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: vpt.i8 eq, q0, zr268; CHECK-NEXT: vshlt.u8 q0, q1, q2269; CHECK-NEXT: bx lr270entry:271 %c = icmp eq <16 x i8> %z, zeroinitializer272 %a = shl <16 x i8> %x, %y273 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z274 ret <16 x i8> %b275}276 277define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {278; CHECK-LABEL: ashr_v4i32:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vneg.s32 q2, q2281; CHECK-NEXT: vpt.i32 eq, q0, zr282; CHECK-NEXT: vshlt.s32 q0, q1, q2283; CHECK-NEXT: bx lr284entry:285 %c = icmp eq <4 x i32> %z, zeroinitializer286 %a = ashr <4 x i32> %x, %y287 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z288 ret <4 x i32> %b289}290 291define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {292; CHECK-LABEL: ashr_v8i16:293; CHECK: @ %bb.0: @ %entry294; CHECK-NEXT: vneg.s16 q2, q2295; CHECK-NEXT: vpt.i16 eq, q0, zr296; CHECK-NEXT: vshlt.s16 q0, q1, q2297; CHECK-NEXT: bx lr298entry:299 %c = icmp eq <8 x i16> %z, zeroinitializer300 %a = ashr <8 x i16> %x, %y301 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z302 ret <8 x i16> %b303}304 305define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {306; CHECK-LABEL: ashr_v16i8:307; CHECK: @ %bb.0: @ %entry308; CHECK-NEXT: vneg.s8 q2, q2309; CHECK-NEXT: vpt.i8 eq, q0, zr310; CHECK-NEXT: vshlt.s8 q0, q1, q2311; CHECK-NEXT: bx lr312entry:313 %c = icmp eq <16 x i8> %z, zeroinitializer314 %a = ashr <16 x i8> %x, %y315 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z316 ret <16 x i8> %b317}318 319define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {320; CHECK-LABEL: lshr_v4i32:321; CHECK: @ %bb.0: @ %entry322; CHECK-NEXT: vneg.s32 q2, q2323; CHECK-NEXT: vpt.i32 eq, q0, zr324; CHECK-NEXT: vshlt.u32 q0, q1, q2325; CHECK-NEXT: bx lr326entry:327 %c = icmp eq <4 x i32> %z, zeroinitializer328 %a = lshr <4 x i32> %x, %y329 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z330 ret <4 x i32> %b331}332 333define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {334; CHECK-LABEL: lshr_v8i16:335; CHECK: @ %bb.0: @ %entry336; CHECK-NEXT: vneg.s16 q2, q2337; CHECK-NEXT: vpt.i16 eq, q0, zr338; CHECK-NEXT: vshlt.u16 q0, q1, q2339; CHECK-NEXT: bx lr340entry:341 %c = icmp eq <8 x i16> %z, zeroinitializer342 %a = lshr <8 x i16> %x, %y343 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z344 ret <8 x i16> %b345}346 347define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {348; CHECK-LABEL: lshr_v16i8:349; CHECK: @ %bb.0: @ %entry350; CHECK-NEXT: vneg.s8 q2, q2351; CHECK-NEXT: vpt.i8 eq, q0, zr352; CHECK-NEXT: vshlt.u8 q0, q1, q2353; CHECK-NEXT: bx lr354entry:355 %c = icmp eq <16 x i8> %z, zeroinitializer356 %a = lshr <16 x i8> %x, %y357 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z358 ret <16 x i8> %b359}360 361define arm_aapcs_vfpcc <4 x i32> @andnot_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {362; CHECK-LABEL: andnot_v4i32:363; CHECK: @ %bb.0: @ %entry364; CHECK-NEXT: vpt.i32 eq, q0, zr365; CHECK-NEXT: vbict q0, q1, q2366; CHECK-NEXT: bx lr367entry:368 %c = icmp eq <4 x i32> %z, zeroinitializer369 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>370 %a = and <4 x i32> %x, %y1371 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z372 ret <4 x i32> %b373}374 375define arm_aapcs_vfpcc <8 x i16> @andnot_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {376; CHECK-LABEL: andnot_v8i16:377; CHECK: @ %bb.0: @ %entry378; CHECK-NEXT: vpt.i16 eq, q0, zr379; CHECK-NEXT: vbict q0, q1, q2380; CHECK-NEXT: bx lr381entry:382 %c = icmp eq <8 x i16> %z, zeroinitializer383 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>384 %a = and <8 x i16> %x, %y1385 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z386 ret <8 x i16> %b387}388 389define arm_aapcs_vfpcc <16 x i8> @andnot_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {390; CHECK-LABEL: andnot_v16i8:391; CHECK: @ %bb.0: @ %entry392; CHECK-NEXT: vpt.i8 eq, q0, zr393; CHECK-NEXT: vbict q0, q1, q2394; CHECK-NEXT: bx lr395entry:396 %c = icmp eq <16 x i8> %z, zeroinitializer397 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>398 %a = and <16 x i8> %x, %y1399 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z400 ret <16 x i8> %b401}402 403define arm_aapcs_vfpcc <4 x i32> @ornot_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {404; CHECK-LABEL: ornot_v4i32:405; CHECK: @ %bb.0: @ %entry406; CHECK-NEXT: vpt.i32 eq, q0, zr407; CHECK-NEXT: vornt q0, q1, q2408; CHECK-NEXT: bx lr409entry:410 %c = icmp eq <4 x i32> %z, zeroinitializer411 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>412 %a = or <4 x i32> %x, %y1413 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z414 ret <4 x i32> %b415}416 417define arm_aapcs_vfpcc <8 x i16> @ornot_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {418; CHECK-LABEL: ornot_v8i16:419; CHECK: @ %bb.0: @ %entry420; CHECK-NEXT: vpt.i16 eq, q0, zr421; CHECK-NEXT: vornt q0, q1, q2422; CHECK-NEXT: bx lr423entry:424 %c = icmp eq <8 x i16> %z, zeroinitializer425 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>426 %a = or <8 x i16> %x, %y1427 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z428 ret <8 x i16> %b429}430 431define arm_aapcs_vfpcc <16 x i8> @ornot_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {432; CHECK-LABEL: ornot_v16i8:433; CHECK: @ %bb.0: @ %entry434; CHECK-NEXT: vpt.i8 eq, q0, zr435; CHECK-NEXT: vornt q0, q1, q2436; CHECK-NEXT: bx lr437entry:438 %c = icmp eq <16 x i8> %z, zeroinitializer439 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>440 %a = or <16 x i8> %x, %y1441 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z442 ret <16 x i8> %b443}444 445define arm_aapcs_vfpcc <4 x float> @fadd_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {446; CHECK-LABEL: fadd_v4f32:447; CHECK: @ %bb.0: @ %entry448; CHECK-NEXT: vpt.f32 eq, q0, zr449; CHECK-NEXT: vaddt.f32 q0, q1, q2450; CHECK-NEXT: bx lr451entry:452 %c = fcmp oeq <4 x float> %z, zeroinitializer453 %a = fadd <4 x float> %x, %y454 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z455 ret <4 x float> %b456}457 458define arm_aapcs_vfpcc <8 x half> @fadd_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {459; CHECK-LABEL: fadd_v8f16:460; CHECK: @ %bb.0: @ %entry461; CHECK-NEXT: vpt.f16 eq, q0, zr462; CHECK-NEXT: vaddt.f16 q0, q1, q2463; CHECK-NEXT: bx lr464entry:465 %c = fcmp oeq <8 x half> %z, zeroinitializer466 %a = fadd <8 x half> %x, %y467 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z468 ret <8 x half> %b469}470 471define arm_aapcs_vfpcc <4 x float> @fsub_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {472; CHECK-LABEL: fsub_v4f32:473; CHECK: @ %bb.0: @ %entry474; CHECK-NEXT: vpt.f32 eq, q0, zr475; CHECK-NEXT: vsubt.f32 q0, q1, q2476; CHECK-NEXT: bx lr477entry:478 %c = fcmp oeq <4 x float> %z, zeroinitializer479 %a = fsub <4 x float> %x, %y480 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z481 ret <4 x float> %b482}483 484define arm_aapcs_vfpcc <8 x half> @fsub_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {485; CHECK-LABEL: fsub_v8f16:486; CHECK: @ %bb.0: @ %entry487; CHECK-NEXT: vpt.f16 eq, q0, zr488; CHECK-NEXT: vsubt.f16 q0, q1, q2489; CHECK-NEXT: bx lr490entry:491 %c = fcmp oeq <8 x half> %z, zeroinitializer492 %a = fsub <8 x half> %x, %y493 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z494 ret <8 x half> %b495}496 497define arm_aapcs_vfpcc <4 x float> @fmul_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {498; CHECK-LABEL: fmul_v4f32:499; CHECK: @ %bb.0: @ %entry500; CHECK-NEXT: vpt.f32 eq, q0, zr501; CHECK-NEXT: vmult.f32 q0, q1, q2502; CHECK-NEXT: bx lr503entry:504 %c = fcmp oeq <4 x float> %z, zeroinitializer505 %a = fmul <4 x float> %x, %y506 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z507 ret <4 x float> %b508}509 510define arm_aapcs_vfpcc <8 x half> @fmul_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {511; CHECK-LABEL: fmul_v8f16:512; CHECK: @ %bb.0: @ %entry513; CHECK-NEXT: vpt.f16 eq, q0, zr514; CHECK-NEXT: vmult.f16 q0, q1, q2515; CHECK-NEXT: bx lr516entry:517 %c = fcmp oeq <8 x half> %z, zeroinitializer518 %a = fmul <8 x half> %x, %y519 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z520 ret <8 x half> %b521}522 523define arm_aapcs_vfpcc <4 x float> @fdiv_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {524; CHECK-LABEL: fdiv_v4f32:525; CHECK: @ %bb.0: @ %entry526; CHECK-NEXT: vdiv.f32 s7, s7, s11527; CHECK-NEXT: vcmp.f32 eq, q0, zr528; CHECK-NEXT: vdiv.f32 s6, s6, s10529; CHECK-NEXT: vdiv.f32 s5, s5, s9530; CHECK-NEXT: vdiv.f32 s4, s4, s8531; CHECK-NEXT: vpsel q0, q1, q0532; CHECK-NEXT: bx lr533entry:534 %c = fcmp oeq <4 x float> %z, zeroinitializer535 %a = fdiv <4 x float> %x, %y536 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z537 ret <4 x float> %b538}539 540define arm_aapcs_vfpcc <8 x half> @fdiv_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {541; CHECK-LABEL: fdiv_v8f16:542; CHECK: @ %bb.0: @ %entry543; CHECK-NEXT: vmovx.f16 s14, s4544; CHECK-NEXT: vmovx.f16 s12, s8545; CHECK-NEXT: vdiv.f16 s4, s4, s8546; CHECK-NEXT: vdiv.f16 s12, s14, s12547; CHECK-NEXT: vins.f16 s4, s12548; CHECK-NEXT: vmovx.f16 s12, s5549; CHECK-NEXT: vmovx.f16 s8, s9550; CHECK-NEXT: vdiv.f16 s5, s5, s9551; CHECK-NEXT: vdiv.f16 s8, s12, s8552; CHECK-NEXT: vmovx.f16 s12, s6553; CHECK-NEXT: vins.f16 s5, s8554; CHECK-NEXT: vmovx.f16 s8, s10555; CHECK-NEXT: vdiv.f16 s6, s6, s10556; CHECK-NEXT: vdiv.f16 s8, s12, s8557; CHECK-NEXT: vins.f16 s6, s8558; CHECK-NEXT: vmovx.f16 s10, s7559; CHECK-NEXT: vmovx.f16 s8, s11560; CHECK-NEXT: vdiv.f16 s7, s7, s11561; CHECK-NEXT: vdiv.f16 s8, s10, s8562; CHECK-NEXT: vcmp.f16 eq, q0, zr563; CHECK-NEXT: vins.f16 s7, s8564; CHECK-NEXT: vpsel q0, q1, q0565; CHECK-NEXT: bx lr566entry:567 %c = fcmp oeq <8 x half> %z, zeroinitializer568 %a = fdiv <8 x half> %x, %y569 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z570 ret <8 x half> %b571}572 573define arm_aapcs_vfpcc <4 x i32> @icmp_slt_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {574; CHECK-LABEL: icmp_slt_v4i32:575; CHECK: @ %bb.0: @ %entry576; CHECK-NEXT: vpt.i32 eq, q0, zr577; CHECK-NEXT: vmint.s32 q0, q1, q2578; CHECK-NEXT: bx lr579entry:580 %c = icmp eq <4 x i32> %z, zeroinitializer581 %a1 = icmp slt <4 x i32> %x, %y582 %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y583 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z584 ret <4 x i32> %b585}586 587define arm_aapcs_vfpcc <8 x i16> @icmp_slt_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {588; CHECK-LABEL: icmp_slt_v8i16:589; CHECK: @ %bb.0: @ %entry590; CHECK-NEXT: vpt.i16 eq, q0, zr591; CHECK-NEXT: vmint.s16 q0, q1, q2592; CHECK-NEXT: bx lr593entry:594 %c = icmp eq <8 x i16> %z, zeroinitializer595 %a1 = icmp slt <8 x i16> %x, %y596 %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y597 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z598 ret <8 x i16> %b599}600 601define arm_aapcs_vfpcc <16 x i8> @icmp_slt_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {602; CHECK-LABEL: icmp_slt_v16i8:603; CHECK: @ %bb.0: @ %entry604; CHECK-NEXT: vpt.i8 eq, q0, zr605; CHECK-NEXT: vmint.s8 q0, q1, q2606; CHECK-NEXT: bx lr607entry:608 %c = icmp eq <16 x i8> %z, zeroinitializer609 %a1 = icmp slt <16 x i8> %x, %y610 %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y611 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z612 ret <16 x i8> %b613}614 615define arm_aapcs_vfpcc <4 x i32> @icmp_sgt_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {616; CHECK-LABEL: icmp_sgt_v4i32:617; CHECK: @ %bb.0: @ %entry618; CHECK-NEXT: vpt.i32 eq, q0, zr619; CHECK-NEXT: vmaxt.s32 q0, q1, q2620; CHECK-NEXT: bx lr621entry:622 %c = icmp eq <4 x i32> %z, zeroinitializer623 %a1 = icmp sgt <4 x i32> %x, %y624 %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y625 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z626 ret <4 x i32> %b627}628 629define arm_aapcs_vfpcc <8 x i16> @icmp_sgt_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {630; CHECK-LABEL: icmp_sgt_v8i16:631; CHECK: @ %bb.0: @ %entry632; CHECK-NEXT: vpt.i16 eq, q0, zr633; CHECK-NEXT: vmaxt.s16 q0, q1, q2634; CHECK-NEXT: bx lr635entry:636 %c = icmp eq <8 x i16> %z, zeroinitializer637 %a1 = icmp sgt <8 x i16> %x, %y638 %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y639 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z640 ret <8 x i16> %b641}642 643define arm_aapcs_vfpcc <16 x i8> @icmp_sgt_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {644; CHECK-LABEL: icmp_sgt_v16i8:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: vpt.i8 eq, q0, zr647; CHECK-NEXT: vmaxt.s8 q0, q1, q2648; CHECK-NEXT: bx lr649entry:650 %c = icmp eq <16 x i8> %z, zeroinitializer651 %a1 = icmp sgt <16 x i8> %x, %y652 %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y653 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z654 ret <16 x i8> %b655}656 657define arm_aapcs_vfpcc <4 x i32> @icmp_ult_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {658; CHECK-LABEL: icmp_ult_v4i32:659; CHECK: @ %bb.0: @ %entry660; CHECK-NEXT: vpt.i32 eq, q0, zr661; CHECK-NEXT: vmint.u32 q0, q1, q2662; CHECK-NEXT: bx lr663entry:664 %c = icmp eq <4 x i32> %z, zeroinitializer665 %a1 = icmp ult <4 x i32> %x, %y666 %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y667 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z668 ret <4 x i32> %b669}670 671define arm_aapcs_vfpcc <8 x i16> @icmp_ult_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {672; CHECK-LABEL: icmp_ult_v8i16:673; CHECK: @ %bb.0: @ %entry674; CHECK-NEXT: vpt.i16 eq, q0, zr675; CHECK-NEXT: vmint.u16 q0, q1, q2676; CHECK-NEXT: bx lr677entry:678 %c = icmp eq <8 x i16> %z, zeroinitializer679 %a1 = icmp ult <8 x i16> %x, %y680 %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y681 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z682 ret <8 x i16> %b683}684 685define arm_aapcs_vfpcc <16 x i8> @icmp_ult_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {686; CHECK-LABEL: icmp_ult_v16i8:687; CHECK: @ %bb.0: @ %entry688; CHECK-NEXT: vpt.i8 eq, q0, zr689; CHECK-NEXT: vmint.u8 q0, q1, q2690; CHECK-NEXT: bx lr691entry:692 %c = icmp eq <16 x i8> %z, zeroinitializer693 %a1 = icmp ult <16 x i8> %x, %y694 %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y695 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z696 ret <16 x i8> %b697}698 699define arm_aapcs_vfpcc <4 x i32> @icmp_ugt_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {700; CHECK-LABEL: icmp_ugt_v4i32:701; CHECK: @ %bb.0: @ %entry702; CHECK-NEXT: vpt.i32 eq, q0, zr703; CHECK-NEXT: vmaxt.u32 q0, q1, q2704; CHECK-NEXT: bx lr705entry:706 %c = icmp eq <4 x i32> %z, zeroinitializer707 %a1 = icmp ugt <4 x i32> %x, %y708 %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y709 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z710 ret <4 x i32> %b711}712 713define arm_aapcs_vfpcc <8 x i16> @icmp_ugt_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {714; CHECK-LABEL: icmp_ugt_v8i16:715; CHECK: @ %bb.0: @ %entry716; CHECK-NEXT: vpt.i16 eq, q0, zr717; CHECK-NEXT: vmaxt.u16 q0, q1, q2718; CHECK-NEXT: bx lr719entry:720 %c = icmp eq <8 x i16> %z, zeroinitializer721 %a1 = icmp ugt <8 x i16> %x, %y722 %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y723 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z724 ret <8 x i16> %b725}726 727define arm_aapcs_vfpcc <16 x i8> @icmp_ugt_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {728; CHECK-LABEL: icmp_ugt_v16i8:729; CHECK: @ %bb.0: @ %entry730; CHECK-NEXT: vpt.i8 eq, q0, zr731; CHECK-NEXT: vmaxt.u8 q0, q1, q2732; CHECK-NEXT: bx lr733entry:734 %c = icmp eq <16 x i8> %z, zeroinitializer735 %a1 = icmp ugt <16 x i8> %x, %y736 %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y737 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z738 ret <16 x i8> %b739}740 741define arm_aapcs_vfpcc <4 x float> @fcmp_fast_olt_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {742; CHECK-LABEL: fcmp_fast_olt_v4f32:743; CHECK: @ %bb.0: @ %entry744; CHECK-NEXT: vpt.f32 eq, q0, zr745; CHECK-NEXT: vminnmt.f32 q0, q1, q2746; CHECK-NEXT: bx lr747entry:748 %c = fcmp oeq <4 x float> %z, zeroinitializer749 %a1 = fcmp fast olt <4 x float> %x, %y750 %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y751 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z752 ret <4 x float> %b753}754 755define arm_aapcs_vfpcc <8 x half> @fcmp_fast_olt_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {756; CHECK-LABEL: fcmp_fast_olt_v8f16:757; CHECK: @ %bb.0: @ %entry758; CHECK-NEXT: vpt.f16 eq, q0, zr759; CHECK-NEXT: vminnmt.f16 q0, q1, q2760; CHECK-NEXT: bx lr761entry:762 %c = fcmp oeq <8 x half> %z, zeroinitializer763 %a1 = fcmp fast olt <8 x half> %x, %y764 %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y765 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z766 ret <8 x half> %b767}768 769define arm_aapcs_vfpcc <4 x float> @fcmp_fast_ogt_v4f32(<4 x float> %z, <4 x float> %x, <4 x float> %y) {770; CHECK-LABEL: fcmp_fast_ogt_v4f32:771; CHECK: @ %bb.0: @ %entry772; CHECK-NEXT: vpt.f32 eq, q0, zr773; CHECK-NEXT: vmaxnmt.f32 q0, q1, q2774; CHECK-NEXT: bx lr775entry:776 %c = fcmp oeq <4 x float> %z, zeroinitializer777 %a1 = fcmp fast ogt <4 x float> %x, %y778 %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y779 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z780 ret <4 x float> %b781}782 783define arm_aapcs_vfpcc <8 x half> @fcmp_fast_ogt_v8f16(<8 x half> %z, <8 x half> %x, <8 x half> %y) {784; CHECK-LABEL: fcmp_fast_ogt_v8f16:785; CHECK: @ %bb.0: @ %entry786; CHECK-NEXT: vpt.f16 eq, q0, zr787; CHECK-NEXT: vmaxnmt.f16 q0, q1, q2788; CHECK-NEXT: bx lr789entry:790 %c = fcmp oeq <8 x half> %z, zeroinitializer791 %a1 = fcmp fast ogt <8 x half> %x, %y792 %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y793 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z794 ret <8 x half> %b795}796 797define arm_aapcs_vfpcc <4 x i32> @sadd_sat_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {798; CHECK-LABEL: sadd_sat_v4i32:799; CHECK: @ %bb.0: @ %entry800; CHECK-NEXT: vpt.i32 eq, q0, zr801; CHECK-NEXT: vqaddt.s32 q0, q1, q2802; CHECK-NEXT: bx lr803entry:804 %c = icmp eq <4 x i32> %z, zeroinitializer805 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)806 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z807 ret <4 x i32> %b808}809 810define arm_aapcs_vfpcc <8 x i16> @sadd_sat_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {811; CHECK-LABEL: sadd_sat_v8i16:812; CHECK: @ %bb.0: @ %entry813; CHECK-NEXT: vpt.i16 eq, q0, zr814; CHECK-NEXT: vqaddt.s16 q0, q1, q2815; CHECK-NEXT: bx lr816entry:817 %c = icmp eq <8 x i16> %z, zeroinitializer818 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)819 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z820 ret <8 x i16> %b821}822 823define arm_aapcs_vfpcc <16 x i8> @sadd_sat_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {824; CHECK-LABEL: sadd_sat_v16i8:825; CHECK: @ %bb.0: @ %entry826; CHECK-NEXT: vpt.i8 eq, q0, zr827; CHECK-NEXT: vqaddt.s8 q0, q1, q2828; CHECK-NEXT: bx lr829entry:830 %c = icmp eq <16 x i8> %z, zeroinitializer831 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)832 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z833 ret <16 x i8> %b834}835 836define arm_aapcs_vfpcc <4 x i32> @uadd_sat_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {837; CHECK-LABEL: uadd_sat_v4i32:838; CHECK: @ %bb.0: @ %entry839; CHECK-NEXT: vpt.i32 eq, q0, zr840; CHECK-NEXT: vqaddt.u32 q0, q1, q2841; CHECK-NEXT: bx lr842entry:843 %c = icmp eq <4 x i32> %z, zeroinitializer844 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)845 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z846 ret <4 x i32> %b847}848 849define arm_aapcs_vfpcc <8 x i16> @uadd_sat_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {850; CHECK-LABEL: uadd_sat_v8i16:851; CHECK: @ %bb.0: @ %entry852; CHECK-NEXT: vpt.i16 eq, q0, zr853; CHECK-NEXT: vqaddt.u16 q0, q1, q2854; CHECK-NEXT: bx lr855entry:856 %c = icmp eq <8 x i16> %z, zeroinitializer857 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)858 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z859 ret <8 x i16> %b860}861 862define arm_aapcs_vfpcc <16 x i8> @uadd_sat_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {863; CHECK-LABEL: uadd_sat_v16i8:864; CHECK: @ %bb.0: @ %entry865; CHECK-NEXT: vpt.i8 eq, q0, zr866; CHECK-NEXT: vqaddt.u8 q0, q1, q2867; CHECK-NEXT: bx lr868entry:869 %c = icmp eq <16 x i8> %z, zeroinitializer870 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)871 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z872 ret <16 x i8> %b873}874 875define arm_aapcs_vfpcc <4 x i32> @ssub_sat_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {876; CHECK-LABEL: ssub_sat_v4i32:877; CHECK: @ %bb.0: @ %entry878; CHECK-NEXT: vpt.i32 eq, q0, zr879; CHECK-NEXT: vqsubt.s32 q0, q1, q2880; CHECK-NEXT: bx lr881entry:882 %c = icmp eq <4 x i32> %z, zeroinitializer883 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)884 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z885 ret <4 x i32> %b886}887 888define arm_aapcs_vfpcc <8 x i16> @ssub_sat_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {889; CHECK-LABEL: ssub_sat_v8i16:890; CHECK: @ %bb.0: @ %entry891; CHECK-NEXT: vpt.i16 eq, q0, zr892; CHECK-NEXT: vqsubt.s16 q0, q1, q2893; CHECK-NEXT: bx lr894entry:895 %c = icmp eq <8 x i16> %z, zeroinitializer896 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)897 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z898 ret <8 x i16> %b899}900 901define arm_aapcs_vfpcc <16 x i8> @ssub_sat_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {902; CHECK-LABEL: ssub_sat_v16i8:903; CHECK: @ %bb.0: @ %entry904; CHECK-NEXT: vpt.i8 eq, q0, zr905; CHECK-NEXT: vqsubt.s8 q0, q1, q2906; CHECK-NEXT: bx lr907entry:908 %c = icmp eq <16 x i8> %z, zeroinitializer909 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)910 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z911 ret <16 x i8> %b912}913 914define arm_aapcs_vfpcc <4 x i32> @usub_sat_v4i32(<4 x i32> %z, <4 x i32> %x, <4 x i32> %y) {915; CHECK-LABEL: usub_sat_v4i32:916; CHECK: @ %bb.0: @ %entry917; CHECK-NEXT: vpt.i32 eq, q0, zr918; CHECK-NEXT: vqsubt.u32 q0, q1, q2919; CHECK-NEXT: bx lr920entry:921 %c = icmp eq <4 x i32> %z, zeroinitializer922 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)923 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z924 ret <4 x i32> %b925}926 927define arm_aapcs_vfpcc <8 x i16> @usub_sat_v8i16(<8 x i16> %z, <8 x i16> %x, <8 x i16> %y) {928; CHECK-LABEL: usub_sat_v8i16:929; CHECK: @ %bb.0: @ %entry930; CHECK-NEXT: vpt.i16 eq, q0, zr931; CHECK-NEXT: vqsubt.u16 q0, q1, q2932; CHECK-NEXT: bx lr933entry:934 %c = icmp eq <8 x i16> %z, zeroinitializer935 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)936 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z937 ret <8 x i16> %b938}939 940define arm_aapcs_vfpcc <16 x i8> @usub_sat_v16i8(<16 x i8> %z, <16 x i8> %x, <16 x i8> %y) {941; CHECK-LABEL: usub_sat_v16i8:942; CHECK: @ %bb.0: @ %entry943; CHECK-NEXT: vpt.i8 eq, q0, zr944; CHECK-NEXT: vqsubt.u8 q0, q1, q2945; CHECK-NEXT: bx lr946entry:947 %c = icmp eq <16 x i8> %z, zeroinitializer948 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)949 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z950 ret <16 x i8> %b951}952 953define arm_aapcs_vfpcc <4 x i32> @addqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {954; CHECK-LABEL: addqr_v4i32:955; CHECK: @ %bb.0: @ %entry956; CHECK-NEXT: vpt.i32 eq, q0, zr957; CHECK-NEXT: vaddt.i32 q0, q1, r0958; CHECK-NEXT: bx lr959entry:960 %c = icmp eq <4 x i32> %z, zeroinitializer961 %i = insertelement <4 x i32> undef, i32 %y, i32 0962 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer963 %a = add <4 x i32> %x, %ys964 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z965 ret <4 x i32> %b966}967 968define arm_aapcs_vfpcc <8 x i16> @addqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {969; CHECK-LABEL: addqr_v8i16:970; CHECK: @ %bb.0: @ %entry971; CHECK-NEXT: vpt.i16 eq, q0, zr972; CHECK-NEXT: vaddt.i16 q0, q1, r0973; CHECK-NEXT: bx lr974entry:975 %c = icmp eq <8 x i16> %z, zeroinitializer976 %i = insertelement <8 x i16> undef, i16 %y, i32 0977 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer978 %a = add <8 x i16> %x, %ys979 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z980 ret <8 x i16> %b981}982 983define arm_aapcs_vfpcc <16 x i8> @addqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {984; CHECK-LABEL: addqr_v16i8:985; CHECK: @ %bb.0: @ %entry986; CHECK-NEXT: vpt.i8 eq, q0, zr987; CHECK-NEXT: vaddt.i8 q0, q1, r0988; CHECK-NEXT: bx lr989entry:990 %c = icmp eq <16 x i8> %z, zeroinitializer991 %i = insertelement <16 x i8> undef, i8 %y, i32 0992 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer993 %a = add <16 x i8> %x, %ys994 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z995 ret <16 x i8> %b996}997 998define arm_aapcs_vfpcc <4 x i32> @subqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {999; CHECK-LABEL: subqr_v4i32:1000; CHECK: @ %bb.0: @ %entry1001; CHECK-NEXT: vpt.i32 eq, q0, zr1002; CHECK-NEXT: vsubt.i32 q0, q1, r01003; CHECK-NEXT: bx lr1004entry:1005 %c = icmp eq <4 x i32> %z, zeroinitializer1006 %i = insertelement <4 x i32> undef, i32 %y, i32 01007 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1008 %a = sub <4 x i32> %x, %ys1009 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1010 ret <4 x i32> %b1011}1012 1013define arm_aapcs_vfpcc <8 x i16> @subqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1014; CHECK-LABEL: subqr_v8i16:1015; CHECK: @ %bb.0: @ %entry1016; CHECK-NEXT: vpt.i16 eq, q0, zr1017; CHECK-NEXT: vsubt.i16 q0, q1, r01018; CHECK-NEXT: bx lr1019entry:1020 %c = icmp eq <8 x i16> %z, zeroinitializer1021 %i = insertelement <8 x i16> undef, i16 %y, i32 01022 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1023 %a = sub <8 x i16> %x, %ys1024 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1025 ret <8 x i16> %b1026}1027 1028define arm_aapcs_vfpcc <16 x i8> @subqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1029; CHECK-LABEL: subqr_v16i8:1030; CHECK: @ %bb.0: @ %entry1031; CHECK-NEXT: vpt.i8 eq, q0, zr1032; CHECK-NEXT: vsubt.i8 q0, q1, r01033; CHECK-NEXT: bx lr1034entry:1035 %c = icmp eq <16 x i8> %z, zeroinitializer1036 %i = insertelement <16 x i8> undef, i8 %y, i32 01037 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1038 %a = sub <16 x i8> %x, %ys1039 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1040 ret <16 x i8> %b1041}1042 1043define arm_aapcs_vfpcc <4 x i32> @mulqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {1044; CHECK-LABEL: mulqr_v4i32:1045; CHECK: @ %bb.0: @ %entry1046; CHECK-NEXT: vpt.i32 eq, q0, zr1047; CHECK-NEXT: vmult.i32 q0, q1, r01048; CHECK-NEXT: bx lr1049entry:1050 %c = icmp eq <4 x i32> %z, zeroinitializer1051 %i = insertelement <4 x i32> undef, i32 %y, i32 01052 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1053 %a = mul <4 x i32> %x, %ys1054 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1055 ret <4 x i32> %b1056}1057 1058define arm_aapcs_vfpcc <8 x i16> @mulqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1059; CHECK-LABEL: mulqr_v8i16:1060; CHECK: @ %bb.0: @ %entry1061; CHECK-NEXT: vpt.i16 eq, q0, zr1062; CHECK-NEXT: vmult.i16 q0, q1, r01063; CHECK-NEXT: bx lr1064entry:1065 %c = icmp eq <8 x i16> %z, zeroinitializer1066 %i = insertelement <8 x i16> undef, i16 %y, i32 01067 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1068 %a = mul <8 x i16> %x, %ys1069 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1070 ret <8 x i16> %b1071}1072 1073define arm_aapcs_vfpcc <16 x i8> @mulqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1074; CHECK-LABEL: mulqr_v16i8:1075; CHECK: @ %bb.0: @ %entry1076; CHECK-NEXT: vpt.i8 eq, q0, zr1077; CHECK-NEXT: vmult.i8 q0, q1, r01078; CHECK-NEXT: bx lr1079entry:1080 %c = icmp eq <16 x i8> %z, zeroinitializer1081 %i = insertelement <16 x i8> undef, i8 %y, i32 01082 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1083 %a = mul <16 x i8> %x, %ys1084 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1085 ret <16 x i8> %b1086}1087 1088define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32(<4 x float> %z, <4 x float> %x, float %y) {1089; CHECK-LABEL: faddqr_v4f32:1090; CHECK: @ %bb.0: @ %entry1091; CHECK-NEXT: vmov r0, s81092; CHECK-NEXT: vpt.f32 eq, q0, zr1093; CHECK-NEXT: vaddt.f32 q0, q1, r01094; CHECK-NEXT: bx lr1095entry:1096 %c = fcmp oeq <4 x float> %z, zeroinitializer1097 %i = insertelement <4 x float> undef, float %y, i32 01098 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1099 %a = fadd <4 x float> %x, %ys1100 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z1101 ret <4 x float> %b1102}1103 1104define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16(<8 x half> %z, <8 x half> %x, half %y) {1105; CHECK-LABEL: faddqr_v8f16:1106; CHECK: @ %bb.0: @ %entry1107; CHECK-NEXT: vmov.f16 r0, s81108; CHECK-NEXT: vpt.f16 eq, q0, zr1109; CHECK-NEXT: vaddt.f16 q0, q1, r01110; CHECK-NEXT: bx lr1111entry:1112 %c = fcmp oeq <8 x half> %z, zeroinitializer1113 %i = insertelement <8 x half> undef, half %y, i32 01114 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1115 %a = fadd <8 x half> %x, %ys1116 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z1117 ret <8 x half> %b1118}1119 1120define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32(<4 x float> %z, <4 x float> %x, float %y) {1121; CHECK-LABEL: fsubqr_v4f32:1122; CHECK: @ %bb.0: @ %entry1123; CHECK-NEXT: vmov r0, s81124; CHECK-NEXT: vpt.f32 eq, q0, zr1125; CHECK-NEXT: vsubt.f32 q0, q1, r01126; CHECK-NEXT: bx lr1127entry:1128 %c = fcmp oeq <4 x float> %z, zeroinitializer1129 %i = insertelement <4 x float> undef, float %y, i32 01130 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1131 %a = fsub <4 x float> %x, %ys1132 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z1133 ret <4 x float> %b1134}1135 1136define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16(<8 x half> %z, <8 x half> %x, half %y) {1137; CHECK-LABEL: fsubqr_v8f16:1138; CHECK: @ %bb.0: @ %entry1139; CHECK-NEXT: vmov.f16 r0, s81140; CHECK-NEXT: vpt.f16 eq, q0, zr1141; CHECK-NEXT: vsubt.f16 q0, q1, r01142; CHECK-NEXT: bx lr1143entry:1144 %c = fcmp oeq <8 x half> %z, zeroinitializer1145 %i = insertelement <8 x half> undef, half %y, i32 01146 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1147 %a = fsub <8 x half> %x, %ys1148 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z1149 ret <8 x half> %b1150}1151 1152define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32(<4 x float> %z, <4 x float> %x, float %y) {1153; CHECK-LABEL: fmulqr_v4f32:1154; CHECK: @ %bb.0: @ %entry1155; CHECK-NEXT: vmov r0, s81156; CHECK-NEXT: vpt.f32 eq, q0, zr1157; CHECK-NEXT: vmult.f32 q0, q1, r01158; CHECK-NEXT: bx lr1159entry:1160 %c = fcmp oeq <4 x float> %z, zeroinitializer1161 %i = insertelement <4 x float> undef, float %y, i32 01162 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1163 %a = fmul <4 x float> %x, %ys1164 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %z1165 ret <4 x float> %b1166}1167 1168define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16(<8 x half> %z, <8 x half> %x, half %y) {1169; CHECK-LABEL: fmulqr_v8f16:1170; CHECK: @ %bb.0: @ %entry1171; CHECK-NEXT: vmov.f16 r0, s81172; CHECK-NEXT: vpt.f16 eq, q0, zr1173; CHECK-NEXT: vmult.f16 q0, q1, r01174; CHECK-NEXT: bx lr1175entry:1176 %c = fcmp oeq <8 x half> %z, zeroinitializer1177 %i = insertelement <8 x half> undef, half %y, i32 01178 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1179 %a = fmul <8 x half> %x, %ys1180 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %z1181 ret <8 x half> %b1182}1183 1184define arm_aapcs_vfpcc <4 x i32> @sadd_satqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {1185; CHECK-LABEL: sadd_satqr_v4i32:1186; CHECK: @ %bb.0: @ %entry1187; CHECK-NEXT: vpt.i32 eq, q0, zr1188; CHECK-NEXT: vqaddt.s32 q0, q1, r01189; CHECK-NEXT: bx lr1190entry:1191 %c = icmp eq <4 x i32> %z, zeroinitializer1192 %i = insertelement <4 x i32> undef, i32 %y, i32 01193 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1194 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1195 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1196 ret <4 x i32> %b1197}1198 1199define arm_aapcs_vfpcc <8 x i16> @sadd_satqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1200; CHECK-LABEL: sadd_satqr_v8i16:1201; CHECK: @ %bb.0: @ %entry1202; CHECK-NEXT: vpt.i16 eq, q0, zr1203; CHECK-NEXT: vqaddt.s16 q0, q1, r01204; CHECK-NEXT: bx lr1205entry:1206 %c = icmp eq <8 x i16> %z, zeroinitializer1207 %i = insertelement <8 x i16> undef, i16 %y, i32 01208 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1209 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1210 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1211 ret <8 x i16> %b1212}1213 1214define arm_aapcs_vfpcc <16 x i8> @sadd_satqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1215; CHECK-LABEL: sadd_satqr_v16i8:1216; CHECK: @ %bb.0: @ %entry1217; CHECK-NEXT: vpt.i8 eq, q0, zr1218; CHECK-NEXT: vqaddt.s8 q0, q1, r01219; CHECK-NEXT: bx lr1220entry:1221 %c = icmp eq <16 x i8> %z, zeroinitializer1222 %i = insertelement <16 x i8> undef, i8 %y, i32 01223 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1224 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1225 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1226 ret <16 x i8> %b1227}1228 1229define arm_aapcs_vfpcc <4 x i32> @uadd_satqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {1230; CHECK-LABEL: uadd_satqr_v4i32:1231; CHECK: @ %bb.0: @ %entry1232; CHECK-NEXT: vpt.i32 eq, q0, zr1233; CHECK-NEXT: vqaddt.u32 q0, q1, r01234; CHECK-NEXT: bx lr1235entry:1236 %c = icmp eq <4 x i32> %z, zeroinitializer1237 %i = insertelement <4 x i32> undef, i32 %y, i32 01238 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1239 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1240 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1241 ret <4 x i32> %b1242}1243 1244define arm_aapcs_vfpcc <8 x i16> @uadd_satqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1245; CHECK-LABEL: uadd_satqr_v8i16:1246; CHECK: @ %bb.0: @ %entry1247; CHECK-NEXT: vpt.i16 eq, q0, zr1248; CHECK-NEXT: vqaddt.u16 q0, q1, r01249; CHECK-NEXT: bx lr1250entry:1251 %c = icmp eq <8 x i16> %z, zeroinitializer1252 %i = insertelement <8 x i16> undef, i16 %y, i32 01253 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1254 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1255 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1256 ret <8 x i16> %b1257}1258 1259define arm_aapcs_vfpcc <16 x i8> @uadd_satqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1260; CHECK-LABEL: uadd_satqr_v16i8:1261; CHECK: @ %bb.0: @ %entry1262; CHECK-NEXT: vpt.i8 eq, q0, zr1263; CHECK-NEXT: vqaddt.u8 q0, q1, r01264; CHECK-NEXT: bx lr1265entry:1266 %c = icmp eq <16 x i8> %z, zeroinitializer1267 %i = insertelement <16 x i8> undef, i8 %y, i32 01268 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1269 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1270 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1271 ret <16 x i8> %b1272}1273 1274define arm_aapcs_vfpcc <4 x i32> @ssub_satqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {1275; CHECK-LABEL: ssub_satqr_v4i32:1276; CHECK: @ %bb.0: @ %entry1277; CHECK-NEXT: vpt.i32 eq, q0, zr1278; CHECK-NEXT: vqsubt.s32 q0, q1, r01279; CHECK-NEXT: bx lr1280entry:1281 %c = icmp eq <4 x i32> %z, zeroinitializer1282 %i = insertelement <4 x i32> undef, i32 %y, i32 01283 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1284 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1285 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1286 ret <4 x i32> %b1287}1288 1289define arm_aapcs_vfpcc <8 x i16> @ssub_satqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1290; CHECK-LABEL: ssub_satqr_v8i16:1291; CHECK: @ %bb.0: @ %entry1292; CHECK-NEXT: vpt.i16 eq, q0, zr1293; CHECK-NEXT: vqsubt.s16 q0, q1, r01294; CHECK-NEXT: bx lr1295entry:1296 %c = icmp eq <8 x i16> %z, zeroinitializer1297 %i = insertelement <8 x i16> undef, i16 %y, i32 01298 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1299 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1300 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1301 ret <8 x i16> %b1302}1303 1304define arm_aapcs_vfpcc <16 x i8> @ssub_satqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1305; CHECK-LABEL: ssub_satqr_v16i8:1306; CHECK: @ %bb.0: @ %entry1307; CHECK-NEXT: vpt.i8 eq, q0, zr1308; CHECK-NEXT: vqsubt.s8 q0, q1, r01309; CHECK-NEXT: bx lr1310entry:1311 %c = icmp eq <16 x i8> %z, zeroinitializer1312 %i = insertelement <16 x i8> undef, i8 %y, i32 01313 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1314 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1315 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1316 ret <16 x i8> %b1317}1318 1319define arm_aapcs_vfpcc <4 x i32> @usub_satqr_v4i32(<4 x i32> %z, <4 x i32> %x, i32 %y) {1320; CHECK-LABEL: usub_satqr_v4i32:1321; CHECK: @ %bb.0: @ %entry1322; CHECK-NEXT: vpt.i32 eq, q0, zr1323; CHECK-NEXT: vqsubt.u32 q0, q1, r01324; CHECK-NEXT: bx lr1325entry:1326 %c = icmp eq <4 x i32> %z, zeroinitializer1327 %i = insertelement <4 x i32> undef, i32 %y, i32 01328 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1329 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1330 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %z1331 ret <4 x i32> %b1332}1333 1334define arm_aapcs_vfpcc <8 x i16> @usub_satqr_v8i16(<8 x i16> %z, <8 x i16> %x, i16 %y) {1335; CHECK-LABEL: usub_satqr_v8i16:1336; CHECK: @ %bb.0: @ %entry1337; CHECK-NEXT: vpt.i16 eq, q0, zr1338; CHECK-NEXT: vqsubt.u16 q0, q1, r01339; CHECK-NEXT: bx lr1340entry:1341 %c = icmp eq <8 x i16> %z, zeroinitializer1342 %i = insertelement <8 x i16> undef, i16 %y, i32 01343 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1344 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1345 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %z1346 ret <8 x i16> %b1347}1348 1349define arm_aapcs_vfpcc <16 x i8> @usub_satqr_v16i8(<16 x i8> %z, <16 x i8> %x, i8 %y) {1350; CHECK-LABEL: usub_satqr_v16i8:1351; CHECK: @ %bb.0: @ %entry1352; CHECK-NEXT: vpt.i8 eq, q0, zr1353; CHECK-NEXT: vqsubt.u8 q0, q1, r01354; CHECK-NEXT: bx lr1355entry:1356 %c = icmp eq <16 x i8> %z, zeroinitializer1357 %i = insertelement <16 x i8> undef, i8 %y, i32 01358 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1359 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1360 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %z1361 ret <16 x i8> %b1362}1363 1364declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)1365declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)1366declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)1367declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)1368declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)1369declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)1370declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)1371declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)1372declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)1373declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)1374declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)1375declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)1376