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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc <4 x i32> @add_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {5; CHECK-LABEL: add_v4i32_x:6; CHECK:       @ %bb.0: @ %entry7; CHECK-NEXT:    vctp.32 r08; CHECK-NEXT:    vpst9; CHECK-NEXT:    vaddt.i32 q0, q0, q110; CHECK-NEXT:    bx lr11entry:12  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)13  %a = add <4 x i32> %x, %y14  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x15  ret <4 x i32> %b16}17 18define arm_aapcs_vfpcc <8 x i16> @add_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {19; CHECK-LABEL: add_v8i16_x:20; CHECK:       @ %bb.0: @ %entry21; CHECK-NEXT:    vctp.16 r022; CHECK-NEXT:    vpst23; CHECK-NEXT:    vaddt.i16 q0, q0, q124; CHECK-NEXT:    bx lr25entry:26  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)27  %a = add <8 x i16> %x, %y28  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x29  ret <8 x i16> %b30}31 32define arm_aapcs_vfpcc <16 x i8> @add_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {33; CHECK-LABEL: add_v16i8_x:34; CHECK:       @ %bb.0: @ %entry35; CHECK-NEXT:    vctp.8 r036; CHECK-NEXT:    vpst37; CHECK-NEXT:    vaddt.i8 q0, q0, q138; CHECK-NEXT:    bx lr39entry:40  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)41  %a = add <16 x i8> %x, %y42  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x43  ret <16 x i8> %b44}45 46define arm_aapcs_vfpcc <4 x i32> @sub_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {47; CHECK-LABEL: sub_v4i32_x:48; CHECK:       @ %bb.0: @ %entry49; CHECK-NEXT:    vctp.32 r050; CHECK-NEXT:    vpst51; CHECK-NEXT:    vsubt.i32 q0, q0, q152; CHECK-NEXT:    bx lr53entry:54  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)55  %a = sub <4 x i32> %x, %y56  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x57  ret <4 x i32> %b58}59 60define arm_aapcs_vfpcc <8 x i16> @sub_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {61; CHECK-LABEL: sub_v8i16_x:62; CHECK:       @ %bb.0: @ %entry63; CHECK-NEXT:    vctp.16 r064; CHECK-NEXT:    vpst65; CHECK-NEXT:    vsubt.i16 q0, q0, q166; CHECK-NEXT:    bx lr67entry:68  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)69  %a = sub <8 x i16> %x, %y70  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x71  ret <8 x i16> %b72}73 74define arm_aapcs_vfpcc <16 x i8> @sub_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {75; CHECK-LABEL: sub_v16i8_x:76; CHECK:       @ %bb.0: @ %entry77; CHECK-NEXT:    vctp.8 r078; CHECK-NEXT:    vpst79; CHECK-NEXT:    vsubt.i8 q0, q0, q180; CHECK-NEXT:    bx lr81entry:82  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)83  %a = sub <16 x i8> %x, %y84  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x85  ret <16 x i8> %b86}87 88define arm_aapcs_vfpcc <4 x i32> @mul_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {89; CHECK-LABEL: mul_v4i32_x:90; CHECK:       @ %bb.0: @ %entry91; CHECK-NEXT:    vctp.32 r092; CHECK-NEXT:    vpst93; CHECK-NEXT:    vmult.i32 q0, q0, q194; CHECK-NEXT:    bx lr95entry:96  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)97  %a = mul <4 x i32> %x, %y98  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x99  ret <4 x i32> %b100}101 102define arm_aapcs_vfpcc <8 x i16> @mul_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {103; CHECK-LABEL: mul_v8i16_x:104; CHECK:       @ %bb.0: @ %entry105; CHECK-NEXT:    vctp.16 r0106; CHECK-NEXT:    vpst107; CHECK-NEXT:    vmult.i16 q0, q0, q1108; CHECK-NEXT:    bx lr109entry:110  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)111  %a = mul <8 x i16> %x, %y112  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x113  ret <8 x i16> %b114}115 116define arm_aapcs_vfpcc <16 x i8> @mul_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {117; CHECK-LABEL: mul_v16i8_x:118; CHECK:       @ %bb.0: @ %entry119; CHECK-NEXT:    vctp.8 r0120; CHECK-NEXT:    vpst121; CHECK-NEXT:    vmult.i8 q0, q0, q1122; CHECK-NEXT:    bx lr123entry:124  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)125  %a = mul <16 x i8> %x, %y126  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x127  ret <16 x i8> %b128}129 130define arm_aapcs_vfpcc <4 x i32> @and_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {131; CHECK-LABEL: and_v4i32_x:132; CHECK:       @ %bb.0: @ %entry133; CHECK-NEXT:    vctp.32 r0134; CHECK-NEXT:    vpst135; CHECK-NEXT:    vandt q0, q0, q1136; CHECK-NEXT:    bx lr137entry:138  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)139  %a = and <4 x i32> %x, %y140  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x141  ret <4 x i32> %b142}143 144define arm_aapcs_vfpcc <8 x i16> @and_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {145; CHECK-LABEL: and_v8i16_x:146; CHECK:       @ %bb.0: @ %entry147; CHECK-NEXT:    vctp.16 r0148; CHECK-NEXT:    vpst149; CHECK-NEXT:    vandt q0, q0, q1150; CHECK-NEXT:    bx lr151entry:152  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)153  %a = and <8 x i16> %x, %y154  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x155  ret <8 x i16> %b156}157 158define arm_aapcs_vfpcc <16 x i8> @and_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {159; CHECK-LABEL: and_v16i8_x:160; CHECK:       @ %bb.0: @ %entry161; CHECK-NEXT:    vctp.8 r0162; CHECK-NEXT:    vpst163; CHECK-NEXT:    vandt q0, q0, q1164; CHECK-NEXT:    bx lr165entry:166  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)167  %a = and <16 x i8> %x, %y168  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x169  ret <16 x i8> %b170}171 172define arm_aapcs_vfpcc <4 x i32> @or_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {173; CHECK-LABEL: or_v4i32_x:174; CHECK:       @ %bb.0: @ %entry175; CHECK-NEXT:    vctp.32 r0176; CHECK-NEXT:    vpst177; CHECK-NEXT:    vorrt q0, q0, q1178; CHECK-NEXT:    bx lr179entry:180  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)181  %a = or <4 x i32> %x, %y182  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x183  ret <4 x i32> %b184}185 186define arm_aapcs_vfpcc <8 x i16> @or_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {187; CHECK-LABEL: or_v8i16_x:188; CHECK:       @ %bb.0: @ %entry189; CHECK-NEXT:    vctp.16 r0190; CHECK-NEXT:    vpst191; CHECK-NEXT:    vorrt q0, q0, q1192; CHECK-NEXT:    bx lr193entry:194  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)195  %a = or <8 x i16> %x, %y196  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x197  ret <8 x i16> %b198}199 200define arm_aapcs_vfpcc <16 x i8> @or_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {201; CHECK-LABEL: or_v16i8_x:202; CHECK:       @ %bb.0: @ %entry203; CHECK-NEXT:    vctp.8 r0204; CHECK-NEXT:    vpst205; CHECK-NEXT:    vorrt q0, q0, q1206; CHECK-NEXT:    bx lr207entry:208  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)209  %a = or <16 x i8> %x, %y210  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x211  ret <16 x i8> %b212}213 214define arm_aapcs_vfpcc <4 x i32> @xor_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {215; CHECK-LABEL: xor_v4i32_x:216; CHECK:       @ %bb.0: @ %entry217; CHECK-NEXT:    vctp.32 r0218; CHECK-NEXT:    vpst219; CHECK-NEXT:    veort q0, q0, q1220; CHECK-NEXT:    bx lr221entry:222  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)223  %a = xor <4 x i32> %x, %y224  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x225  ret <4 x i32> %b226}227 228define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {229; CHECK-LABEL: xor_v8i16_x:230; CHECK:       @ %bb.0: @ %entry231; CHECK-NEXT:    vctp.16 r0232; CHECK-NEXT:    vpst233; CHECK-NEXT:    veort q0, q0, q1234; CHECK-NEXT:    bx lr235entry:236  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)237  %a = xor <8 x i16> %x, %y238  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x239  ret <8 x i16> %b240}241 242define arm_aapcs_vfpcc <16 x i8> @xor_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {243; CHECK-LABEL: xor_v16i8_x:244; CHECK:       @ %bb.0: @ %entry245; CHECK-NEXT:    vctp.8 r0246; CHECK-NEXT:    vpst247; CHECK-NEXT:    veort q0, q0, q1248; CHECK-NEXT:    bx lr249entry:250  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)251  %a = xor <16 x i8> %x, %y252  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x253  ret <16 x i8> %b254}255 256define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {257; CHECK-LABEL: shl_v4i32_x:258; CHECK:       @ %bb.0: @ %entry259; CHECK-NEXT:    vctp.32 r0260; CHECK-NEXT:    vpst261; CHECK-NEXT:    vshlt.u32 q0, q0, q1262; CHECK-NEXT:    bx lr263entry:264  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)265  %a = shl <4 x i32> %x, %y266  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x267  ret <4 x i32> %b268}269 270define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {271; CHECK-LABEL: shl_v8i16_x:272; CHECK:       @ %bb.0: @ %entry273; CHECK-NEXT:    vctp.16 r0274; CHECK-NEXT:    vpst275; CHECK-NEXT:    vshlt.u16 q0, q0, q1276; CHECK-NEXT:    bx lr277entry:278  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)279  %a = shl <8 x i16> %x, %y280  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x281  ret <8 x i16> %b282}283 284define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {285; CHECK-LABEL: shl_v16i8_x:286; CHECK:       @ %bb.0: @ %entry287; CHECK-NEXT:    vctp.8 r0288; CHECK-NEXT:    vpst289; CHECK-NEXT:    vshlt.u8 q0, q0, q1290; CHECK-NEXT:    bx lr291entry:292  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)293  %a = shl <16 x i8> %x, %y294  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x295  ret <16 x i8> %b296}297 298define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {299; CHECK-LABEL: ashr_v4i32_x:300; CHECK:       @ %bb.0: @ %entry301; CHECK-NEXT:    vneg.s32 q1, q1302; CHECK-NEXT:    vctp.32 r0303; CHECK-NEXT:    vpst304; CHECK-NEXT:    vshlt.s32 q0, q0, q1305; CHECK-NEXT:    bx lr306entry:307  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)308  %a = ashr <4 x i32> %x, %y309  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x310  ret <4 x i32> %b311}312 313define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {314; CHECK-LABEL: ashr_v8i16_x:315; CHECK:       @ %bb.0: @ %entry316; CHECK-NEXT:    vneg.s16 q1, q1317; CHECK-NEXT:    vctp.16 r0318; CHECK-NEXT:    vpst319; CHECK-NEXT:    vshlt.s16 q0, q0, q1320; CHECK-NEXT:    bx lr321entry:322  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)323  %a = ashr <8 x i16> %x, %y324  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x325  ret <8 x i16> %b326}327 328define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {329; CHECK-LABEL: ashr_v16i8_x:330; CHECK:       @ %bb.0: @ %entry331; CHECK-NEXT:    vneg.s8 q1, q1332; CHECK-NEXT:    vctp.8 r0333; CHECK-NEXT:    vpst334; CHECK-NEXT:    vshlt.s8 q0, q0, q1335; CHECK-NEXT:    bx lr336entry:337  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)338  %a = ashr <16 x i8> %x, %y339  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x340  ret <16 x i8> %b341}342 343define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {344; CHECK-LABEL: lshr_v4i32_x:345; CHECK:       @ %bb.0: @ %entry346; CHECK-NEXT:    vneg.s32 q1, q1347; CHECK-NEXT:    vctp.32 r0348; CHECK-NEXT:    vpst349; CHECK-NEXT:    vshlt.u32 q0, q0, q1350; CHECK-NEXT:    bx lr351entry:352  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)353  %a = lshr <4 x i32> %x, %y354  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x355  ret <4 x i32> %b356}357 358define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {359; CHECK-LABEL: lshr_v8i16_x:360; CHECK:       @ %bb.0: @ %entry361; CHECK-NEXT:    vneg.s16 q1, q1362; CHECK-NEXT:    vctp.16 r0363; CHECK-NEXT:    vpst364; CHECK-NEXT:    vshlt.u16 q0, q0, q1365; CHECK-NEXT:    bx lr366entry:367  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)368  %a = lshr <8 x i16> %x, %y369  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x370  ret <8 x i16> %b371}372 373define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {374; CHECK-LABEL: lshr_v16i8_x:375; CHECK:       @ %bb.0: @ %entry376; CHECK-NEXT:    vneg.s8 q1, q1377; CHECK-NEXT:    vctp.8 r0378; CHECK-NEXT:    vpst379; CHECK-NEXT:    vshlt.u8 q0, q0, q1380; CHECK-NEXT:    bx lr381entry:382  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)383  %a = lshr <16 x i8> %x, %y384  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x385  ret <16 x i8> %b386}387 388define arm_aapcs_vfpcc <4 x i32> @andnot_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {389; CHECK-LABEL: andnot_v4i32_x:390; CHECK:       @ %bb.0: @ %entry391; CHECK-NEXT:    vctp.32 r0392; CHECK-NEXT:    vpst393; CHECK-NEXT:    vbict q0, q0, q1394; CHECK-NEXT:    bx lr395entry:396  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)397  %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>398  %a = and <4 x i32> %x, %y1399  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x400  ret <4 x i32> %b401}402 403define arm_aapcs_vfpcc <8 x i16> @andnot_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {404; CHECK-LABEL: andnot_v8i16_x:405; CHECK:       @ %bb.0: @ %entry406; CHECK-NEXT:    vctp.16 r0407; CHECK-NEXT:    vpst408; CHECK-NEXT:    vbict q0, q0, q1409; CHECK-NEXT:    bx lr410entry:411  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)412  %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>413  %a = and <8 x i16> %x, %y1414  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x415  ret <8 x i16> %b416}417 418define arm_aapcs_vfpcc <16 x i8> @andnot_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {419; CHECK-LABEL: andnot_v16i8_x:420; CHECK:       @ %bb.0: @ %entry421; CHECK-NEXT:    vctp.8 r0422; CHECK-NEXT:    vpst423; CHECK-NEXT:    vbict q0, q0, q1424; CHECK-NEXT:    bx lr425entry:426  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)427  %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>428  %a = and <16 x i8> %x, %y1429  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x430  ret <16 x i8> %b431}432 433define arm_aapcs_vfpcc <4 x i32> @ornot_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {434; CHECK-LABEL: ornot_v4i32_x:435; CHECK:       @ %bb.0: @ %entry436; CHECK-NEXT:    vctp.32 r0437; CHECK-NEXT:    vpst438; CHECK-NEXT:    vornt q0, q0, q1439; CHECK-NEXT:    bx lr440entry:441  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)442  %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>443  %a = or <4 x i32> %x, %y1444  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x445  ret <4 x i32> %b446}447 448define arm_aapcs_vfpcc <8 x i16> @ornot_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {449; CHECK-LABEL: ornot_v8i16_x:450; CHECK:       @ %bb.0: @ %entry451; CHECK-NEXT:    vctp.16 r0452; CHECK-NEXT:    vpst453; CHECK-NEXT:    vornt q0, q0, q1454; CHECK-NEXT:    bx lr455entry:456  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)457  %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>458  %a = or <8 x i16> %x, %y1459  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x460  ret <8 x i16> %b461}462 463define arm_aapcs_vfpcc <16 x i8> @ornot_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {464; CHECK-LABEL: ornot_v16i8_x:465; CHECK:       @ %bb.0: @ %entry466; CHECK-NEXT:    vctp.8 r0467; CHECK-NEXT:    vpst468; CHECK-NEXT:    vornt q0, q0, q1469; CHECK-NEXT:    bx lr470entry:471  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)472  %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>473  %a = or <16 x i8> %x, %y1474  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x475  ret <16 x i8> %b476}477 478define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {479; CHECK-LABEL: fadd_v4f32_x:480; CHECK:       @ %bb.0: @ %entry481; CHECK-NEXT:    vctp.32 r0482; CHECK-NEXT:    vpst483; CHECK-NEXT:    vaddt.f32 q0, q0, q1484; CHECK-NEXT:    bx lr485entry:486  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)487  %a = fadd <4 x float> %x, %y488  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x489  ret <4 x float> %b490}491 492define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {493; CHECK-LABEL: fadd_v8f16_x:494; CHECK:       @ %bb.0: @ %entry495; CHECK-NEXT:    vctp.16 r0496; CHECK-NEXT:    vpst497; CHECK-NEXT:    vaddt.f16 q0, q0, q1498; CHECK-NEXT:    bx lr499entry:500  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)501  %a = fadd <8 x half> %x, %y502  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x503  ret <8 x half> %b504}505 506define arm_aapcs_vfpcc <4 x float> @fsub_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {507; CHECK-LABEL: fsub_v4f32_x:508; CHECK:       @ %bb.0: @ %entry509; CHECK-NEXT:    vctp.32 r0510; CHECK-NEXT:    vpst511; CHECK-NEXT:    vsubt.f32 q0, q0, q1512; CHECK-NEXT:    bx lr513entry:514  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)515  %a = fsub <4 x float> %x, %y516  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x517  ret <4 x float> %b518}519 520define arm_aapcs_vfpcc <8 x half> @fsub_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {521; CHECK-LABEL: fsub_v8f16_x:522; CHECK:       @ %bb.0: @ %entry523; CHECK-NEXT:    vctp.16 r0524; CHECK-NEXT:    vpst525; CHECK-NEXT:    vsubt.f16 q0, q0, q1526; CHECK-NEXT:    bx lr527entry:528  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)529  %a = fsub <8 x half> %x, %y530  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x531  ret <8 x half> %b532}533 534define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {535; CHECK-LABEL: fmul_v4f32_x:536; CHECK:       @ %bb.0: @ %entry537; CHECK-NEXT:    vctp.32 r0538; CHECK-NEXT:    vpst539; CHECK-NEXT:    vmult.f32 q0, q0, q1540; CHECK-NEXT:    bx lr541entry:542  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)543  %a = fmul <4 x float> %x, %y544  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x545  ret <4 x float> %b546}547 548define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {549; CHECK-LABEL: fmul_v8f16_x:550; CHECK:       @ %bb.0: @ %entry551; CHECK-NEXT:    vctp.16 r0552; CHECK-NEXT:    vpst553; CHECK-NEXT:    vmult.f16 q0, q0, q1554; CHECK-NEXT:    bx lr555entry:556  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)557  %a = fmul <8 x half> %x, %y558  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x559  ret <8 x half> %b560}561 562define arm_aapcs_vfpcc <4 x float> @fdiv_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {563; CHECK-LABEL: fdiv_v4f32_x:564; CHECK:       @ %bb.0: @ %entry565; CHECK-NEXT:    vdiv.f32 s7, s3, s7566; CHECK-NEXT:    vctp.32 r0567; CHECK-NEXT:    vdiv.f32 s6, s2, s6568; CHECK-NEXT:    vdiv.f32 s5, s1, s5569; CHECK-NEXT:    vdiv.f32 s4, s0, s4570; CHECK-NEXT:    vpst571; CHECK-NEXT:    vmovt q0, q1572; CHECK-NEXT:    bx lr573entry:574  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)575  %a = fdiv <4 x float> %x, %y576  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x577  ret <4 x float> %b578}579 580define arm_aapcs_vfpcc <8 x half> @fdiv_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {581; CHECK-LABEL: fdiv_v8f16_x:582; CHECK:       @ %bb.0: @ %entry583; CHECK-NEXT:    vmovx.f16 s8, s4584; CHECK-NEXT:    vmovx.f16 s10, s0585; CHECK-NEXT:    vdiv.f16 s8, s10, s8586; CHECK-NEXT:    vdiv.f16 s4, s0, s4587; CHECK-NEXT:    vins.f16 s4, s8588; CHECK-NEXT:    vmovx.f16 s8, s5589; CHECK-NEXT:    vmovx.f16 s10, s1590; CHECK-NEXT:    vdiv.f16 s5, s1, s5591; CHECK-NEXT:    vdiv.f16 s8, s10, s8592; CHECK-NEXT:    vmovx.f16 s10, s2593; CHECK-NEXT:    vins.f16 s5, s8594; CHECK-NEXT:    vmovx.f16 s8, s6595; CHECK-NEXT:    vdiv.f16 s8, s10, s8596; CHECK-NEXT:    vdiv.f16 s6, s2, s6597; CHECK-NEXT:    vins.f16 s6, s8598; CHECK-NEXT:    vmovx.f16 s8, s7599; CHECK-NEXT:    vmovx.f16 s10, s3600; CHECK-NEXT:    vdiv.f16 s7, s3, s7601; CHECK-NEXT:    vdiv.f16 s8, s10, s8602; CHECK-NEXT:    vctp.16 r0603; CHECK-NEXT:    vins.f16 s7, s8604; CHECK-NEXT:    vpst605; CHECK-NEXT:    vmovt q0, q1606; CHECK-NEXT:    bx lr607entry:608  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)609  %a = fdiv <8 x half> %x, %y610  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x611  ret <8 x half> %b612}613 614define arm_aapcs_vfpcc <4 x float> @fmai_v4f32_x(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {615; CHECK-LABEL: fmai_v4f32_x:616; CHECK:       @ %bb.0: @ %entry617; CHECK-NEXT:    vctp.32 r0618; CHECK-NEXT:    vpst619; CHECK-NEXT:    vfmat.f32 q0, q1, q2620; CHECK-NEXT:    bx lr621entry:622  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)623  %a = call <4 x float> @llvm.fma.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %x)624  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x625  ret <4 x float> %b626}627 628define arm_aapcs_vfpcc <8 x half> @fmai_v8f16_x(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {629; CHECK-LABEL: fmai_v8f16_x:630; CHECK:       @ %bb.0: @ %entry631; CHECK-NEXT:    vctp.16 r0632; CHECK-NEXT:    vpst633; CHECK-NEXT:    vfmat.f16 q0, q1, q2634; CHECK-NEXT:    bx lr635entry:636  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)637  %a = call <8 x half> @llvm.fma.v8f16(<8 x half> %y, <8 x half> %z, <8 x half> %x)638  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x639  ret <8 x half> %b640}641 642define arm_aapcs_vfpcc <4 x float> @fma_v4f32_x(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {643; CHECK-LABEL: fma_v4f32_x:644; CHECK:       @ %bb.0: @ %entry645; CHECK-NEXT:    vctp.32 r0646; CHECK-NEXT:    vpst647; CHECK-NEXT:    vfmat.f32 q0, q1, q2648; CHECK-NEXT:    bx lr649entry:650  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)651  %m = fmul fast <4 x float> %y, %z652  %a = fadd fast <4 x float> %m, %x653  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x654  ret <4 x float> %b655}656 657define arm_aapcs_vfpcc <8 x half> @fma_v8f16_x(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {658; CHECK-LABEL: fma_v8f16_x:659; CHECK:       @ %bb.0: @ %entry660; CHECK-NEXT:    vctp.16 r0661; CHECK-NEXT:    vpst662; CHECK-NEXT:    vfmat.f16 q0, q1, q2663; CHECK-NEXT:    bx lr664entry:665  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)666  %m = fmul fast <8 x half> %y, %z667  %a = fadd fast <8 x half> %m, %x668  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x669  ret <8 x half> %b670}671 672define arm_aapcs_vfpcc <4 x i32> @icmp_slt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {673; CHECK-LABEL: icmp_slt_v4i32_x:674; CHECK:       @ %bb.0: @ %entry675; CHECK-NEXT:    vctp.32 r0676; CHECK-NEXT:    vpst677; CHECK-NEXT:    vmint.s32 q0, q0, q1678; CHECK-NEXT:    bx lr679entry:680  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)681  %a1 = icmp slt <4 x i32> %x, %y682  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y683  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x684  ret <4 x i32> %b685}686 687define arm_aapcs_vfpcc <8 x i16> @icmp_slt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {688; CHECK-LABEL: icmp_slt_v8i16_x:689; CHECK:       @ %bb.0: @ %entry690; CHECK-NEXT:    vctp.16 r0691; CHECK-NEXT:    vpst692; CHECK-NEXT:    vmint.s16 q0, q0, q1693; CHECK-NEXT:    bx lr694entry:695  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)696  %a1 = icmp slt <8 x i16> %x, %y697  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y698  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x699  ret <8 x i16> %b700}701 702define arm_aapcs_vfpcc <16 x i8> @icmp_slt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {703; CHECK-LABEL: icmp_slt_v16i8_x:704; CHECK:       @ %bb.0: @ %entry705; CHECK-NEXT:    vctp.8 r0706; CHECK-NEXT:    vpst707; CHECK-NEXT:    vmint.s8 q0, q0, q1708; CHECK-NEXT:    bx lr709entry:710  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)711  %a1 = icmp slt <16 x i8> %x, %y712  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y713  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x714  ret <16 x i8> %b715}716 717define arm_aapcs_vfpcc <4 x i32> @icmp_sgt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {718; CHECK-LABEL: icmp_sgt_v4i32_x:719; CHECK:       @ %bb.0: @ %entry720; CHECK-NEXT:    vctp.32 r0721; CHECK-NEXT:    vpst722; CHECK-NEXT:    vmaxt.s32 q0, q0, q1723; CHECK-NEXT:    bx lr724entry:725  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)726  %a1 = icmp sgt <4 x i32> %x, %y727  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y728  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x729  ret <4 x i32> %b730}731 732define arm_aapcs_vfpcc <8 x i16> @icmp_sgt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {733; CHECK-LABEL: icmp_sgt_v8i16_x:734; CHECK:       @ %bb.0: @ %entry735; CHECK-NEXT:    vctp.16 r0736; CHECK-NEXT:    vpst737; CHECK-NEXT:    vmaxt.s16 q0, q0, q1738; CHECK-NEXT:    bx lr739entry:740  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)741  %a1 = icmp sgt <8 x i16> %x, %y742  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y743  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x744  ret <8 x i16> %b745}746 747define arm_aapcs_vfpcc <16 x i8> @icmp_sgt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {748; CHECK-LABEL: icmp_sgt_v16i8_x:749; CHECK:       @ %bb.0: @ %entry750; CHECK-NEXT:    vctp.8 r0751; CHECK-NEXT:    vpst752; CHECK-NEXT:    vmaxt.s8 q0, q0, q1753; CHECK-NEXT:    bx lr754entry:755  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)756  %a1 = icmp sgt <16 x i8> %x, %y757  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y758  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x759  ret <16 x i8> %b760}761 762define arm_aapcs_vfpcc <4 x i32> @icmp_ult_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {763; CHECK-LABEL: icmp_ult_v4i32_x:764; CHECK:       @ %bb.0: @ %entry765; CHECK-NEXT:    vctp.32 r0766; CHECK-NEXT:    vpst767; CHECK-NEXT:    vmint.u32 q0, q0, q1768; CHECK-NEXT:    bx lr769entry:770  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)771  %a1 = icmp ult <4 x i32> %x, %y772  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y773  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x774  ret <4 x i32> %b775}776 777define arm_aapcs_vfpcc <8 x i16> @icmp_ult_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {778; CHECK-LABEL: icmp_ult_v8i16_x:779; CHECK:       @ %bb.0: @ %entry780; CHECK-NEXT:    vctp.16 r0781; CHECK-NEXT:    vpst782; CHECK-NEXT:    vmint.u16 q0, q0, q1783; CHECK-NEXT:    bx lr784entry:785  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)786  %a1 = icmp ult <8 x i16> %x, %y787  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y788  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x789  ret <8 x i16> %b790}791 792define arm_aapcs_vfpcc <16 x i8> @icmp_ult_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {793; CHECK-LABEL: icmp_ult_v16i8_x:794; CHECK:       @ %bb.0: @ %entry795; CHECK-NEXT:    vctp.8 r0796; CHECK-NEXT:    vpst797; CHECK-NEXT:    vmint.u8 q0, q0, q1798; CHECK-NEXT:    bx lr799entry:800  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)801  %a1 = icmp ult <16 x i8> %x, %y802  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y803  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x804  ret <16 x i8> %b805}806 807define arm_aapcs_vfpcc <4 x i32> @icmp_ugt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {808; CHECK-LABEL: icmp_ugt_v4i32_x:809; CHECK:       @ %bb.0: @ %entry810; CHECK-NEXT:    vctp.32 r0811; CHECK-NEXT:    vpst812; CHECK-NEXT:    vmaxt.u32 q0, q0, q1813; CHECK-NEXT:    bx lr814entry:815  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)816  %a1 = icmp ugt <4 x i32> %x, %y817  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y818  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x819  ret <4 x i32> %b820}821 822define arm_aapcs_vfpcc <8 x i16> @icmp_ugt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {823; CHECK-LABEL: icmp_ugt_v8i16_x:824; CHECK:       @ %bb.0: @ %entry825; CHECK-NEXT:    vctp.16 r0826; CHECK-NEXT:    vpst827; CHECK-NEXT:    vmaxt.u16 q0, q0, q1828; CHECK-NEXT:    bx lr829entry:830  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)831  %a1 = icmp ugt <8 x i16> %x, %y832  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y833  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x834  ret <8 x i16> %b835}836 837define arm_aapcs_vfpcc <16 x i8> @icmp_ugt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {838; CHECK-LABEL: icmp_ugt_v16i8_x:839; CHECK:       @ %bb.0: @ %entry840; CHECK-NEXT:    vctp.8 r0841; CHECK-NEXT:    vpst842; CHECK-NEXT:    vmaxt.u8 q0, q0, q1843; CHECK-NEXT:    bx lr844entry:845  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)846  %a1 = icmp ugt <16 x i8> %x, %y847  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y848  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x849  ret <16 x i8> %b850}851 852define arm_aapcs_vfpcc <4 x float> @fcmp_fast_olt_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {853; CHECK-LABEL: fcmp_fast_olt_v4f32_x:854; CHECK:       @ %bb.0: @ %entry855; CHECK-NEXT:    vctp.32 r0856; CHECK-NEXT:    vpst857; CHECK-NEXT:    vminnmt.f32 q0, q0, q1858; CHECK-NEXT:    bx lr859entry:860  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)861  %a1 = fcmp fast olt <4 x float> %x, %y862  %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y863  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x864  ret <4 x float> %b865}866 867define arm_aapcs_vfpcc <8 x half> @fcmp_fast_olt_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {868; CHECK-LABEL: fcmp_fast_olt_v8f16_x:869; CHECK:       @ %bb.0: @ %entry870; CHECK-NEXT:    vctp.16 r0871; CHECK-NEXT:    vpst872; CHECK-NEXT:    vminnmt.f16 q0, q0, q1873; CHECK-NEXT:    bx lr874entry:875  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)876  %a1 = fcmp fast olt <8 x half> %x, %y877  %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y878  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x879  ret <8 x half> %b880}881 882define arm_aapcs_vfpcc <4 x float> @fcmp_fast_ogt_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {883; CHECK-LABEL: fcmp_fast_ogt_v4f32_x:884; CHECK:       @ %bb.0: @ %entry885; CHECK-NEXT:    vctp.32 r0886; CHECK-NEXT:    vpst887; CHECK-NEXT:    vmaxnmt.f32 q0, q0, q1888; CHECK-NEXT:    bx lr889entry:890  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)891  %a1 = fcmp fast ogt <4 x float> %x, %y892  %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y893  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x894  ret <4 x float> %b895}896 897define arm_aapcs_vfpcc <8 x half> @fcmp_fast_ogt_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {898; CHECK-LABEL: fcmp_fast_ogt_v8f16_x:899; CHECK:       @ %bb.0: @ %entry900; CHECK-NEXT:    vctp.16 r0901; CHECK-NEXT:    vpst902; CHECK-NEXT:    vmaxnmt.f16 q0, q0, q1903; CHECK-NEXT:    bx lr904entry:905  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)906  %a1 = fcmp fast ogt <8 x half> %x, %y907  %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y908  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x909  ret <8 x half> %b910}911 912define arm_aapcs_vfpcc <4 x i32> @sadd_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {913; CHECK-LABEL: sadd_sat_v4i32_x:914; CHECK:       @ %bb.0: @ %entry915; CHECK-NEXT:    vctp.32 r0916; CHECK-NEXT:    vpst917; CHECK-NEXT:    vqaddt.s32 q0, q0, q1918; CHECK-NEXT:    bx lr919entry:920  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)921  %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)922  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x923  ret <4 x i32> %b924}925 926define arm_aapcs_vfpcc <8 x i16> @sadd_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {927; CHECK-LABEL: sadd_sat_v8i16_x:928; CHECK:       @ %bb.0: @ %entry929; CHECK-NEXT:    vctp.16 r0930; CHECK-NEXT:    vpst931; CHECK-NEXT:    vqaddt.s16 q0, q0, q1932; CHECK-NEXT:    bx lr933entry:934  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)935  %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)936  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x937  ret <8 x i16> %b938}939 940define arm_aapcs_vfpcc <16 x i8> @sadd_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {941; CHECK-LABEL: sadd_sat_v16i8_x:942; CHECK:       @ %bb.0: @ %entry943; CHECK-NEXT:    vctp.8 r0944; CHECK-NEXT:    vpst945; CHECK-NEXT:    vqaddt.s8 q0, q0, q1946; CHECK-NEXT:    bx lr947entry:948  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)949  %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)950  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x951  ret <16 x i8> %b952}953 954define arm_aapcs_vfpcc <4 x i32> @uadd_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {955; CHECK-LABEL: uadd_sat_v4i32_x:956; CHECK:       @ %bb.0: @ %entry957; CHECK-NEXT:    vctp.32 r0958; CHECK-NEXT:    vpst959; CHECK-NEXT:    vqaddt.u32 q0, q0, q1960; CHECK-NEXT:    bx lr961entry:962  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)963  %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)964  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x965  ret <4 x i32> %b966}967 968define arm_aapcs_vfpcc <8 x i16> @uadd_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {969; CHECK-LABEL: uadd_sat_v8i16_x:970; CHECK:       @ %bb.0: @ %entry971; CHECK-NEXT:    vctp.16 r0972; CHECK-NEXT:    vpst973; CHECK-NEXT:    vqaddt.u16 q0, q0, q1974; CHECK-NEXT:    bx lr975entry:976  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)977  %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)978  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x979  ret <8 x i16> %b980}981 982define arm_aapcs_vfpcc <16 x i8> @uadd_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {983; CHECK-LABEL: uadd_sat_v16i8_x:984; CHECK:       @ %bb.0: @ %entry985; CHECK-NEXT:    vctp.8 r0986; CHECK-NEXT:    vpst987; CHECK-NEXT:    vqaddt.u8 q0, q0, q1988; CHECK-NEXT:    bx lr989entry:990  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)991  %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)992  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x993  ret <16 x i8> %b994}995 996define arm_aapcs_vfpcc <4 x i32> @ssub_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {997; CHECK-LABEL: ssub_sat_v4i32_x:998; CHECK:       @ %bb.0: @ %entry999; CHECK-NEXT:    vctp.32 r01000; CHECK-NEXT:    vpst1001; CHECK-NEXT:    vqsubt.s32 q0, q0, q11002; CHECK-NEXT:    bx lr1003entry:1004  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1005  %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)1006  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1007  ret <4 x i32> %b1008}1009 1010define arm_aapcs_vfpcc <8 x i16> @ssub_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {1011; CHECK-LABEL: ssub_sat_v8i16_x:1012; CHECK:       @ %bb.0: @ %entry1013; CHECK-NEXT:    vctp.16 r01014; CHECK-NEXT:    vpst1015; CHECK-NEXT:    vqsubt.s16 q0, q0, q11016; CHECK-NEXT:    bx lr1017entry:1018  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1019  %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)1020  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1021  ret <8 x i16> %b1022}1023 1024define arm_aapcs_vfpcc <16 x i8> @ssub_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {1025; CHECK-LABEL: ssub_sat_v16i8_x:1026; CHECK:       @ %bb.0: @ %entry1027; CHECK-NEXT:    vctp.8 r01028; CHECK-NEXT:    vpst1029; CHECK-NEXT:    vqsubt.s8 q0, q0, q11030; CHECK-NEXT:    bx lr1031entry:1032  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1033  %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1034  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1035  ret <16 x i8> %b1036}1037 1038define arm_aapcs_vfpcc <4 x i32> @usub_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {1039; CHECK-LABEL: usub_sat_v4i32_x:1040; CHECK:       @ %bb.0: @ %entry1041; CHECK-NEXT:    vctp.32 r01042; CHECK-NEXT:    vpst1043; CHECK-NEXT:    vqsubt.u32 q0, q0, q11044; CHECK-NEXT:    bx lr1045entry:1046  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1047  %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)1048  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1049  ret <4 x i32> %b1050}1051 1052define arm_aapcs_vfpcc <8 x i16> @usub_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {1053; CHECK-LABEL: usub_sat_v8i16_x:1054; CHECK:       @ %bb.0: @ %entry1055; CHECK-NEXT:    vctp.16 r01056; CHECK-NEXT:    vpst1057; CHECK-NEXT:    vqsubt.u16 q0, q0, q11058; CHECK-NEXT:    bx lr1059entry:1060  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1061  %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)1062  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1063  ret <8 x i16> %b1064}1065 1066define arm_aapcs_vfpcc <16 x i8> @usub_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {1067; CHECK-LABEL: usub_sat_v16i8_x:1068; CHECK:       @ %bb.0: @ %entry1069; CHECK-NEXT:    vctp.8 r01070; CHECK-NEXT:    vpst1071; CHECK-NEXT:    vqsubt.u8 q0, q0, q11072; CHECK-NEXT:    bx lr1073entry:1074  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1075  %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1076  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1077  ret <16 x i8> %b1078}1079 1080define arm_aapcs_vfpcc <4 x i32> @addqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1081; CHECK-LABEL: addqr_v4i32_x:1082; CHECK:       @ %bb.0: @ %entry1083; CHECK-NEXT:    vctp.32 r11084; CHECK-NEXT:    vpst1085; CHECK-NEXT:    vaddt.i32 q0, q0, r01086; CHECK-NEXT:    bx lr1087entry:1088  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1089  %i = insertelement <4 x i32> undef, i32 %y, i32 01090  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1091  %a = add <4 x i32> %x, %ys1092  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1093  ret <4 x i32> %b1094}1095 1096define arm_aapcs_vfpcc <8 x i16> @addqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1097; CHECK-LABEL: addqr_v8i16_x:1098; CHECK:       @ %bb.0: @ %entry1099; CHECK-NEXT:    vctp.16 r11100; CHECK-NEXT:    vpst1101; CHECK-NEXT:    vaddt.i16 q0, q0, r01102; CHECK-NEXT:    bx lr1103entry:1104  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1105  %i = insertelement <8 x i16> undef, i16 %y, i32 01106  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1107  %a = add <8 x i16> %x, %ys1108  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1109  ret <8 x i16> %b1110}1111 1112define arm_aapcs_vfpcc <16 x i8> @addqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1113; CHECK-LABEL: addqr_v16i8_x:1114; CHECK:       @ %bb.0: @ %entry1115; CHECK-NEXT:    vctp.8 r11116; CHECK-NEXT:    vpst1117; CHECK-NEXT:    vaddt.i8 q0, q0, r01118; CHECK-NEXT:    bx lr1119entry:1120  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1121  %i = insertelement <16 x i8> undef, i8 %y, i32 01122  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1123  %a = add <16 x i8> %x, %ys1124  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1125  ret <16 x i8> %b1126}1127 1128define arm_aapcs_vfpcc <4 x i32> @subqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1129; CHECK-LABEL: subqr_v4i32_x:1130; CHECK:       @ %bb.0: @ %entry1131; CHECK-NEXT:    vctp.32 r11132; CHECK-NEXT:    vpst1133; CHECK-NEXT:    vsubt.i32 q0, q0, r01134; CHECK-NEXT:    bx lr1135entry:1136  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1137  %i = insertelement <4 x i32> undef, i32 %y, i32 01138  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1139  %a = sub <4 x i32> %x, %ys1140  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1141  ret <4 x i32> %b1142}1143 1144define arm_aapcs_vfpcc <8 x i16> @subqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1145; CHECK-LABEL: subqr_v8i16_x:1146; CHECK:       @ %bb.0: @ %entry1147; CHECK-NEXT:    vctp.16 r11148; CHECK-NEXT:    vpst1149; CHECK-NEXT:    vsubt.i16 q0, q0, r01150; CHECK-NEXT:    bx lr1151entry:1152  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1153  %i = insertelement <8 x i16> undef, i16 %y, i32 01154  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1155  %a = sub <8 x i16> %x, %ys1156  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1157  ret <8 x i16> %b1158}1159 1160define arm_aapcs_vfpcc <16 x i8> @subqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1161; CHECK-LABEL: subqr_v16i8_x:1162; CHECK:       @ %bb.0: @ %entry1163; CHECK-NEXT:    vctp.8 r11164; CHECK-NEXT:    vpst1165; CHECK-NEXT:    vsubt.i8 q0, q0, r01166; CHECK-NEXT:    bx lr1167entry:1168  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1169  %i = insertelement <16 x i8> undef, i8 %y, i32 01170  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1171  %a = sub <16 x i8> %x, %ys1172  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1173  ret <16 x i8> %b1174}1175 1176define arm_aapcs_vfpcc <4 x i32> @mulqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1177; CHECK-LABEL: mulqr_v4i32_x:1178; CHECK:       @ %bb.0: @ %entry1179; CHECK-NEXT:    vctp.32 r11180; CHECK-NEXT:    vpst1181; CHECK-NEXT:    vmult.i32 q0, q0, r01182; CHECK-NEXT:    bx lr1183entry:1184  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1185  %i = insertelement <4 x i32> undef, i32 %y, i32 01186  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1187  %a = mul <4 x i32> %x, %ys1188  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1189  ret <4 x i32> %b1190}1191 1192define arm_aapcs_vfpcc <8 x i16> @mulqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1193; CHECK-LABEL: mulqr_v8i16_x:1194; CHECK:       @ %bb.0: @ %entry1195; CHECK-NEXT:    vctp.16 r11196; CHECK-NEXT:    vpst1197; CHECK-NEXT:    vmult.i16 q0, q0, r01198; CHECK-NEXT:    bx lr1199entry:1200  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1201  %i = insertelement <8 x i16> undef, i16 %y, i32 01202  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1203  %a = mul <8 x i16> %x, %ys1204  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1205  ret <8 x i16> %b1206}1207 1208define arm_aapcs_vfpcc <16 x i8> @mulqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1209; CHECK-LABEL: mulqr_v16i8_x:1210; CHECK:       @ %bb.0: @ %entry1211; CHECK-NEXT:    vctp.8 r11212; CHECK-NEXT:    vpst1213; CHECK-NEXT:    vmult.i8 q0, q0, r01214; CHECK-NEXT:    bx lr1215entry:1216  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1217  %i = insertelement <16 x i8> undef, i8 %y, i32 01218  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1219  %a = mul <16 x i8> %x, %ys1220  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1221  ret <16 x i8> %b1222}1223 1224define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1225; CHECK-LABEL: faddqr_v4f32_x:1226; CHECK:       @ %bb.0: @ %entry1227; CHECK-NEXT:    vmov r1, s41228; CHECK-NEXT:    vctp.32 r01229; CHECK-NEXT:    vpst1230; CHECK-NEXT:    vaddt.f32 q0, q0, r11231; CHECK-NEXT:    bx lr1232entry:1233  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1234  %i = insertelement <4 x float> undef, float %y, i32 01235  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1236  %a = fadd <4 x float> %x, %ys1237  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x1238  ret <4 x float> %b1239}1240 1241define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1242; CHECK-LABEL: faddqr_v8f16_x:1243; CHECK:       @ %bb.0: @ %entry1244; CHECK-NEXT:    vmov.f16 r1, s41245; CHECK-NEXT:    vctp.16 r01246; CHECK-NEXT:    vpst1247; CHECK-NEXT:    vaddt.f16 q0, q0, r11248; CHECK-NEXT:    bx lr1249entry:1250  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1251  %i = insertelement <8 x half> undef, half %y, i32 01252  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1253  %a = fadd <8 x half> %x, %ys1254  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x1255  ret <8 x half> %b1256}1257 1258define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1259; CHECK-LABEL: fsubqr_v4f32_x:1260; CHECK:       @ %bb.0: @ %entry1261; CHECK-NEXT:    vmov r1, s41262; CHECK-NEXT:    vctp.32 r01263; CHECK-NEXT:    vpst1264; CHECK-NEXT:    vsubt.f32 q0, q0, r11265; CHECK-NEXT:    bx lr1266entry:1267  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1268  %i = insertelement <4 x float> undef, float %y, i32 01269  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1270  %a = fsub <4 x float> %x, %ys1271  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x1272  ret <4 x float> %b1273}1274 1275define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1276; CHECK-LABEL: fsubqr_v8f16_x:1277; CHECK:       @ %bb.0: @ %entry1278; CHECK-NEXT:    vmov.f16 r1, s41279; CHECK-NEXT:    vctp.16 r01280; CHECK-NEXT:    vpst1281; CHECK-NEXT:    vsubt.f16 q0, q0, r11282; CHECK-NEXT:    bx lr1283entry:1284  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1285  %i = insertelement <8 x half> undef, half %y, i32 01286  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1287  %a = fsub <8 x half> %x, %ys1288  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x1289  ret <8 x half> %b1290}1291 1292define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1293; CHECK-LABEL: fmulqr_v4f32_x:1294; CHECK:       @ %bb.0: @ %entry1295; CHECK-NEXT:    vmov r1, s41296; CHECK-NEXT:    vctp.32 r01297; CHECK-NEXT:    vpst1298; CHECK-NEXT:    vmult.f32 q0, q0, r11299; CHECK-NEXT:    bx lr1300entry:1301  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1302  %i = insertelement <4 x float> undef, float %y, i32 01303  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1304  %a = fmul <4 x float> %x, %ys1305  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x1306  ret <4 x float> %b1307}1308 1309define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1310; CHECK-LABEL: fmulqr_v8f16_x:1311; CHECK:       @ %bb.0: @ %entry1312; CHECK-NEXT:    vmov.f16 r1, s41313; CHECK-NEXT:    vctp.16 r01314; CHECK-NEXT:    vpst1315; CHECK-NEXT:    vmult.f16 q0, q0, r11316; CHECK-NEXT:    bx lr1317entry:1318  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1319  %i = insertelement <8 x half> undef, half %y, i32 01320  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1321  %a = fmul <8 x half> %x, %ys1322  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x1323  ret <8 x half> %b1324}1325 1326define arm_aapcs_vfpcc <4 x i32> @sadd_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1327; CHECK-LABEL: sadd_satqr_v4i32_x:1328; CHECK:       @ %bb.0: @ %entry1329; CHECK-NEXT:    vctp.32 r11330; CHECK-NEXT:    vpst1331; CHECK-NEXT:    vqaddt.s32 q0, q0, r01332; CHECK-NEXT:    bx lr1333entry:1334  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1335  %i = insertelement <4 x i32> undef, i32 %y, i32 01336  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1337  %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1338  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1339  ret <4 x i32> %b1340}1341 1342define arm_aapcs_vfpcc <8 x i16> @sadd_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1343; CHECK-LABEL: sadd_satqr_v8i16_x:1344; CHECK:       @ %bb.0: @ %entry1345; CHECK-NEXT:    vctp.16 r11346; CHECK-NEXT:    vpst1347; CHECK-NEXT:    vqaddt.s16 q0, q0, r01348; CHECK-NEXT:    bx lr1349entry:1350  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1351  %i = insertelement <8 x i16> undef, i16 %y, i32 01352  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1353  %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1354  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1355  ret <8 x i16> %b1356}1357 1358define arm_aapcs_vfpcc <16 x i8> @sadd_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1359; CHECK-LABEL: sadd_satqr_v16i8_x:1360; CHECK:       @ %bb.0: @ %entry1361; CHECK-NEXT:    vctp.8 r11362; CHECK-NEXT:    vpst1363; CHECK-NEXT:    vqaddt.s8 q0, q0, r01364; CHECK-NEXT:    bx lr1365entry:1366  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1367  %i = insertelement <16 x i8> undef, i8 %y, i32 01368  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1369  %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1370  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1371  ret <16 x i8> %b1372}1373 1374define arm_aapcs_vfpcc <4 x i32> @uadd_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1375; CHECK-LABEL: uadd_satqr_v4i32_x:1376; CHECK:       @ %bb.0: @ %entry1377; CHECK-NEXT:    vctp.32 r11378; CHECK-NEXT:    vpst1379; CHECK-NEXT:    vqaddt.u32 q0, q0, r01380; CHECK-NEXT:    bx lr1381entry:1382  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1383  %i = insertelement <4 x i32> undef, i32 %y, i32 01384  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1385  %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1386  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1387  ret <4 x i32> %b1388}1389 1390define arm_aapcs_vfpcc <8 x i16> @uadd_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1391; CHECK-LABEL: uadd_satqr_v8i16_x:1392; CHECK:       @ %bb.0: @ %entry1393; CHECK-NEXT:    vctp.16 r11394; CHECK-NEXT:    vpst1395; CHECK-NEXT:    vqaddt.u16 q0, q0, r01396; CHECK-NEXT:    bx lr1397entry:1398  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1399  %i = insertelement <8 x i16> undef, i16 %y, i32 01400  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1401  %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1402  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1403  ret <8 x i16> %b1404}1405 1406define arm_aapcs_vfpcc <16 x i8> @uadd_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1407; CHECK-LABEL: uadd_satqr_v16i8_x:1408; CHECK:       @ %bb.0: @ %entry1409; CHECK-NEXT:    vctp.8 r11410; CHECK-NEXT:    vpst1411; CHECK-NEXT:    vqaddt.u8 q0, q0, r01412; CHECK-NEXT:    bx lr1413entry:1414  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1415  %i = insertelement <16 x i8> undef, i8 %y, i32 01416  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1417  %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1418  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1419  ret <16 x i8> %b1420}1421 1422define arm_aapcs_vfpcc <4 x i32> @ssub_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1423; CHECK-LABEL: ssub_satqr_v4i32_x:1424; CHECK:       @ %bb.0: @ %entry1425; CHECK-NEXT:    vctp.32 r11426; CHECK-NEXT:    vpst1427; CHECK-NEXT:    vqsubt.s32 q0, q0, r01428; CHECK-NEXT:    bx lr1429entry:1430  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1431  %i = insertelement <4 x i32> undef, i32 %y, i32 01432  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1433  %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1434  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1435  ret <4 x i32> %b1436}1437 1438define arm_aapcs_vfpcc <8 x i16> @ssub_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1439; CHECK-LABEL: ssub_satqr_v8i16_x:1440; CHECK:       @ %bb.0: @ %entry1441; CHECK-NEXT:    vctp.16 r11442; CHECK-NEXT:    vpst1443; CHECK-NEXT:    vqsubt.s16 q0, q0, r01444; CHECK-NEXT:    bx lr1445entry:1446  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1447  %i = insertelement <8 x i16> undef, i16 %y, i32 01448  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1449  %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1450  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1451  ret <8 x i16> %b1452}1453 1454define arm_aapcs_vfpcc <16 x i8> @ssub_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1455; CHECK-LABEL: ssub_satqr_v16i8_x:1456; CHECK:       @ %bb.0: @ %entry1457; CHECK-NEXT:    vctp.8 r11458; CHECK-NEXT:    vpst1459; CHECK-NEXT:    vqsubt.s8 q0, q0, r01460; CHECK-NEXT:    bx lr1461entry:1462  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1463  %i = insertelement <16 x i8> undef, i8 %y, i32 01464  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1465  %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1466  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1467  ret <16 x i8> %b1468}1469 1470define arm_aapcs_vfpcc <4 x i32> @usub_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1471; CHECK-LABEL: usub_satqr_v4i32_x:1472; CHECK:       @ %bb.0: @ %entry1473; CHECK-NEXT:    vctp.32 r11474; CHECK-NEXT:    vpst1475; CHECK-NEXT:    vqsubt.u32 q0, q0, r01476; CHECK-NEXT:    bx lr1477entry:1478  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1479  %i = insertelement <4 x i32> undef, i32 %y, i32 01480  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1481  %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1482  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1483  ret <4 x i32> %b1484}1485 1486define arm_aapcs_vfpcc <8 x i16> @usub_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1487; CHECK-LABEL: usub_satqr_v8i16_x:1488; CHECK:       @ %bb.0: @ %entry1489; CHECK-NEXT:    vctp.16 r11490; CHECK-NEXT:    vpst1491; CHECK-NEXT:    vqsubt.u16 q0, q0, r01492; CHECK-NEXT:    bx lr1493entry:1494  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1495  %i = insertelement <8 x i16> undef, i16 %y, i32 01496  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1497  %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1498  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1499  ret <8 x i16> %b1500}1501 1502define arm_aapcs_vfpcc <16 x i8> @usub_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1503; CHECK-LABEL: usub_satqr_v16i8_x:1504; CHECK:       @ %bb.0: @ %entry1505; CHECK-NEXT:    vctp.8 r11506; CHECK-NEXT:    vpst1507; CHECK-NEXT:    vqsubt.u8 q0, q0, r01508; CHECK-NEXT:    bx lr1509entry:1510  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1511  %i = insertelement <16 x i8> undef, i8 %y, i32 01512  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1513  %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1514  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1515  ret <16 x i8> %b1516}1517 1518define arm_aapcs_vfpcc <4 x i32> @add_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1519; CHECK-LABEL: add_v4i32_y:1520; CHECK:       @ %bb.0: @ %entry1521; CHECK-NEXT:    vctp.32 r01522; CHECK-NEXT:    vpst1523; CHECK-NEXT:    vaddt.i32 q1, q0, q11524; CHECK-NEXT:    vmov q0, q11525; CHECK-NEXT:    bx lr1526entry:1527  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1528  %a = add <4 x i32> %x, %y1529  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1530  ret <4 x i32> %b1531}1532 1533define arm_aapcs_vfpcc <8 x i16> @add_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1534; CHECK-LABEL: add_v8i16_y:1535; CHECK:       @ %bb.0: @ %entry1536; CHECK-NEXT:    vctp.16 r01537; CHECK-NEXT:    vpst1538; CHECK-NEXT:    vaddt.i16 q1, q0, q11539; CHECK-NEXT:    vmov q0, q11540; CHECK-NEXT:    bx lr1541entry:1542  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1543  %a = add <8 x i16> %x, %y1544  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1545  ret <8 x i16> %b1546}1547 1548define arm_aapcs_vfpcc <16 x i8> @add_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1549; CHECK-LABEL: add_v16i8_y:1550; CHECK:       @ %bb.0: @ %entry1551; CHECK-NEXT:    vctp.8 r01552; CHECK-NEXT:    vpst1553; CHECK-NEXT:    vaddt.i8 q1, q0, q11554; CHECK-NEXT:    vmov q0, q11555; CHECK-NEXT:    bx lr1556entry:1557  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1558  %a = add <16 x i8> %x, %y1559  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1560  ret <16 x i8> %b1561}1562 1563define arm_aapcs_vfpcc <4 x i32> @sub_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1564; CHECK-LABEL: sub_v4i32_y:1565; CHECK:       @ %bb.0: @ %entry1566; CHECK-NEXT:    vctp.32 r01567; CHECK-NEXT:    vpst1568; CHECK-NEXT:    vsubt.i32 q1, q0, q11569; CHECK-NEXT:    vmov q0, q11570; CHECK-NEXT:    bx lr1571entry:1572  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1573  %a = sub <4 x i32> %x, %y1574  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1575  ret <4 x i32> %b1576}1577 1578define arm_aapcs_vfpcc <8 x i16> @sub_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1579; CHECK-LABEL: sub_v8i16_y:1580; CHECK:       @ %bb.0: @ %entry1581; CHECK-NEXT:    vctp.16 r01582; CHECK-NEXT:    vpst1583; CHECK-NEXT:    vsubt.i16 q1, q0, q11584; CHECK-NEXT:    vmov q0, q11585; CHECK-NEXT:    bx lr1586entry:1587  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1588  %a = sub <8 x i16> %x, %y1589  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1590  ret <8 x i16> %b1591}1592 1593define arm_aapcs_vfpcc <16 x i8> @sub_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1594; CHECK-LABEL: sub_v16i8_y:1595; CHECK:       @ %bb.0: @ %entry1596; CHECK-NEXT:    vctp.8 r01597; CHECK-NEXT:    vpst1598; CHECK-NEXT:    vsubt.i8 q1, q0, q11599; CHECK-NEXT:    vmov q0, q11600; CHECK-NEXT:    bx lr1601entry:1602  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1603  %a = sub <16 x i8> %x, %y1604  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1605  ret <16 x i8> %b1606}1607 1608define arm_aapcs_vfpcc <4 x i32> @mul_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1609; CHECK-LABEL: mul_v4i32_y:1610; CHECK:       @ %bb.0: @ %entry1611; CHECK-NEXT:    vctp.32 r01612; CHECK-NEXT:    vpst1613; CHECK-NEXT:    vmult.i32 q1, q0, q11614; CHECK-NEXT:    vmov q0, q11615; CHECK-NEXT:    bx lr1616entry:1617  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1618  %a = mul <4 x i32> %x, %y1619  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1620  ret <4 x i32> %b1621}1622 1623define arm_aapcs_vfpcc <8 x i16> @mul_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1624; CHECK-LABEL: mul_v8i16_y:1625; CHECK:       @ %bb.0: @ %entry1626; CHECK-NEXT:    vctp.16 r01627; CHECK-NEXT:    vpst1628; CHECK-NEXT:    vmult.i16 q1, q0, q11629; CHECK-NEXT:    vmov q0, q11630; CHECK-NEXT:    bx lr1631entry:1632  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1633  %a = mul <8 x i16> %x, %y1634  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1635  ret <8 x i16> %b1636}1637 1638define arm_aapcs_vfpcc <16 x i8> @mul_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1639; CHECK-LABEL: mul_v16i8_y:1640; CHECK:       @ %bb.0: @ %entry1641; CHECK-NEXT:    vctp.8 r01642; CHECK-NEXT:    vpst1643; CHECK-NEXT:    vmult.i8 q1, q0, q11644; CHECK-NEXT:    vmov q0, q11645; CHECK-NEXT:    bx lr1646entry:1647  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1648  %a = mul <16 x i8> %x, %y1649  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1650  ret <16 x i8> %b1651}1652 1653define arm_aapcs_vfpcc <4 x i32> @and_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1654; CHECK-LABEL: and_v4i32_y:1655; CHECK:       @ %bb.0: @ %entry1656; CHECK-NEXT:    vctp.32 r01657; CHECK-NEXT:    vpst1658; CHECK-NEXT:    vandt q1, q0, q11659; CHECK-NEXT:    vmov q0, q11660; CHECK-NEXT:    bx lr1661entry:1662  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1663  %a = and <4 x i32> %x, %y1664  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1665  ret <4 x i32> %b1666}1667 1668define arm_aapcs_vfpcc <8 x i16> @and_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1669; CHECK-LABEL: and_v8i16_y:1670; CHECK:       @ %bb.0: @ %entry1671; CHECK-NEXT:    vctp.16 r01672; CHECK-NEXT:    vpst1673; CHECK-NEXT:    vandt q1, q0, q11674; CHECK-NEXT:    vmov q0, q11675; CHECK-NEXT:    bx lr1676entry:1677  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1678  %a = and <8 x i16> %x, %y1679  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1680  ret <8 x i16> %b1681}1682 1683define arm_aapcs_vfpcc <16 x i8> @and_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1684; CHECK-LABEL: and_v16i8_y:1685; CHECK:       @ %bb.0: @ %entry1686; CHECK-NEXT:    vctp.8 r01687; CHECK-NEXT:    vpst1688; CHECK-NEXT:    vandt q1, q0, q11689; CHECK-NEXT:    vmov q0, q11690; CHECK-NEXT:    bx lr1691entry:1692  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1693  %a = and <16 x i8> %x, %y1694  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1695  ret <16 x i8> %b1696}1697 1698define arm_aapcs_vfpcc <4 x i32> @or_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1699; CHECK-LABEL: or_v4i32_y:1700; CHECK:       @ %bb.0: @ %entry1701; CHECK-NEXT:    vctp.32 r01702; CHECK-NEXT:    vpst1703; CHECK-NEXT:    vorrt q1, q0, q11704; CHECK-NEXT:    vmov q0, q11705; CHECK-NEXT:    bx lr1706entry:1707  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1708  %a = or <4 x i32> %x, %y1709  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1710  ret <4 x i32> %b1711}1712 1713define arm_aapcs_vfpcc <8 x i16> @or_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1714; CHECK-LABEL: or_v8i16_y:1715; CHECK:       @ %bb.0: @ %entry1716; CHECK-NEXT:    vctp.16 r01717; CHECK-NEXT:    vpst1718; CHECK-NEXT:    vorrt q1, q0, q11719; CHECK-NEXT:    vmov q0, q11720; CHECK-NEXT:    bx lr1721entry:1722  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1723  %a = or <8 x i16> %x, %y1724  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1725  ret <8 x i16> %b1726}1727 1728define arm_aapcs_vfpcc <16 x i8> @or_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1729; CHECK-LABEL: or_v16i8_y:1730; CHECK:       @ %bb.0: @ %entry1731; CHECK-NEXT:    vctp.8 r01732; CHECK-NEXT:    vpst1733; CHECK-NEXT:    vorrt q1, q0, q11734; CHECK-NEXT:    vmov q0, q11735; CHECK-NEXT:    bx lr1736entry:1737  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1738  %a = or <16 x i8> %x, %y1739  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1740  ret <16 x i8> %b1741}1742 1743define arm_aapcs_vfpcc <4 x i32> @xor_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1744; CHECK-LABEL: xor_v4i32_y:1745; CHECK:       @ %bb.0: @ %entry1746; CHECK-NEXT:    vctp.32 r01747; CHECK-NEXT:    vpst1748; CHECK-NEXT:    veort q1, q0, q11749; CHECK-NEXT:    vmov q0, q11750; CHECK-NEXT:    bx lr1751entry:1752  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1753  %a = xor <4 x i32> %x, %y1754  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1755  ret <4 x i32> %b1756}1757 1758define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1759; CHECK-LABEL: xor_v8i16_y:1760; CHECK:       @ %bb.0: @ %entry1761; CHECK-NEXT:    vctp.16 r01762; CHECK-NEXT:    vpst1763; CHECK-NEXT:    veort q1, q0, q11764; CHECK-NEXT:    vmov q0, q11765; CHECK-NEXT:    bx lr1766entry:1767  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1768  %a = xor <8 x i16> %x, %y1769  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1770  ret <8 x i16> %b1771}1772 1773define arm_aapcs_vfpcc <16 x i8> @xor_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1774; CHECK-LABEL: xor_v16i8_y:1775; CHECK:       @ %bb.0: @ %entry1776; CHECK-NEXT:    vctp.8 r01777; CHECK-NEXT:    vpst1778; CHECK-NEXT:    veort q1, q0, q11779; CHECK-NEXT:    vmov q0, q11780; CHECK-NEXT:    bx lr1781entry:1782  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1783  %a = xor <16 x i8> %x, %y1784  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1785  ret <16 x i8> %b1786}1787 1788define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1789; CHECK-LABEL: shl_v4i32_y:1790; CHECK:       @ %bb.0: @ %entry1791; CHECK-NEXT:    vctp.32 r01792; CHECK-NEXT:    vpst1793; CHECK-NEXT:    vshlt.u32 q1, q0, q11794; CHECK-NEXT:    vmov q0, q11795; CHECK-NEXT:    bx lr1796entry:1797  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1798  %a = shl <4 x i32> %x, %y1799  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1800  ret <4 x i32> %b1801}1802 1803define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1804; CHECK-LABEL: shl_v8i16_y:1805; CHECK:       @ %bb.0: @ %entry1806; CHECK-NEXT:    vctp.16 r01807; CHECK-NEXT:    vpst1808; CHECK-NEXT:    vshlt.u16 q1, q0, q11809; CHECK-NEXT:    vmov q0, q11810; CHECK-NEXT:    bx lr1811entry:1812  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1813  %a = shl <8 x i16> %x, %y1814  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1815  ret <8 x i16> %b1816}1817 1818define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1819; CHECK-LABEL: shl_v16i8_y:1820; CHECK:       @ %bb.0: @ %entry1821; CHECK-NEXT:    vctp.8 r01822; CHECK-NEXT:    vpst1823; CHECK-NEXT:    vshlt.u8 q1, q0, q11824; CHECK-NEXT:    vmov q0, q11825; CHECK-NEXT:    bx lr1826entry:1827  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1828  %a = shl <16 x i8> %x, %y1829  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1830  ret <16 x i8> %b1831}1832 1833define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1834; CHECK-LABEL: ashr_v4i32_y:1835; CHECK:       @ %bb.0: @ %entry1836; CHECK-NEXT:    vneg.s32 q2, q11837; CHECK-NEXT:    vctp.32 r01838; CHECK-NEXT:    vpst1839; CHECK-NEXT:    vshlt.s32 q1, q0, q21840; CHECK-NEXT:    vmov q0, q11841; CHECK-NEXT:    bx lr1842entry:1843  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1844  %a = ashr <4 x i32> %x, %y1845  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1846  ret <4 x i32> %b1847}1848 1849define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1850; CHECK-LABEL: ashr_v8i16_y:1851; CHECK:       @ %bb.0: @ %entry1852; CHECK-NEXT:    vneg.s16 q2, q11853; CHECK-NEXT:    vctp.16 r01854; CHECK-NEXT:    vpst1855; CHECK-NEXT:    vshlt.s16 q1, q0, q21856; CHECK-NEXT:    vmov q0, q11857; CHECK-NEXT:    bx lr1858entry:1859  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1860  %a = ashr <8 x i16> %x, %y1861  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1862  ret <8 x i16> %b1863}1864 1865define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1866; CHECK-LABEL: ashr_v16i8_y:1867; CHECK:       @ %bb.0: @ %entry1868; CHECK-NEXT:    vneg.s8 q2, q11869; CHECK-NEXT:    vctp.8 r01870; CHECK-NEXT:    vpst1871; CHECK-NEXT:    vshlt.s8 q1, q0, q21872; CHECK-NEXT:    vmov q0, q11873; CHECK-NEXT:    bx lr1874entry:1875  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1876  %a = ashr <16 x i8> %x, %y1877  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1878  ret <16 x i8> %b1879}1880 1881define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1882; CHECK-LABEL: lshr_v4i32_y:1883; CHECK:       @ %bb.0: @ %entry1884; CHECK-NEXT:    vneg.s32 q2, q11885; CHECK-NEXT:    vctp.32 r01886; CHECK-NEXT:    vpst1887; CHECK-NEXT:    vshlt.u32 q1, q0, q21888; CHECK-NEXT:    vmov q0, q11889; CHECK-NEXT:    bx lr1890entry:1891  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1892  %a = lshr <4 x i32> %x, %y1893  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1894  ret <4 x i32> %b1895}1896 1897define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1898; CHECK-LABEL: lshr_v8i16_y:1899; CHECK:       @ %bb.0: @ %entry1900; CHECK-NEXT:    vneg.s16 q2, q11901; CHECK-NEXT:    vctp.16 r01902; CHECK-NEXT:    vpst1903; CHECK-NEXT:    vshlt.u16 q1, q0, q21904; CHECK-NEXT:    vmov q0, q11905; CHECK-NEXT:    bx lr1906entry:1907  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1908  %a = lshr <8 x i16> %x, %y1909  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1910  ret <8 x i16> %b1911}1912 1913define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1914; CHECK-LABEL: lshr_v16i8_y:1915; CHECK:       @ %bb.0: @ %entry1916; CHECK-NEXT:    vneg.s8 q2, q11917; CHECK-NEXT:    vctp.8 r01918; CHECK-NEXT:    vpst1919; CHECK-NEXT:    vshlt.u8 q1, q0, q21920; CHECK-NEXT:    vmov q0, q11921; CHECK-NEXT:    bx lr1922entry:1923  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1924  %a = lshr <16 x i8> %x, %y1925  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1926  ret <16 x i8> %b1927}1928 1929define arm_aapcs_vfpcc <4 x i32> @andnot_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1930; CHECK-LABEL: andnot_v4i32_y:1931; CHECK:       @ %bb.0: @ %entry1932; CHECK-NEXT:    vctp.32 r01933; CHECK-NEXT:    vpst1934; CHECK-NEXT:    vbict q1, q0, q11935; CHECK-NEXT:    vmov q0, q11936; CHECK-NEXT:    bx lr1937entry:1938  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1939  %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>1940  %a = and <4 x i32> %x, %y11941  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1942  ret <4 x i32> %b1943}1944 1945define arm_aapcs_vfpcc <8 x i16> @andnot_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1946; CHECK-LABEL: andnot_v8i16_y:1947; CHECK:       @ %bb.0: @ %entry1948; CHECK-NEXT:    vctp.16 r01949; CHECK-NEXT:    vpst1950; CHECK-NEXT:    vbict q1, q0, q11951; CHECK-NEXT:    vmov q0, q11952; CHECK-NEXT:    bx lr1953entry:1954  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1955  %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1956  %a = and <8 x i16> %x, %y11957  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1958  ret <8 x i16> %b1959}1960 1961define arm_aapcs_vfpcc <16 x i8> @andnot_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1962; CHECK-LABEL: andnot_v16i8_y:1963; CHECK:       @ %bb.0: @ %entry1964; CHECK-NEXT:    vctp.8 r01965; CHECK-NEXT:    vpst1966; CHECK-NEXT:    vbict q1, q0, q11967; CHECK-NEXT:    vmov q0, q11968; CHECK-NEXT:    bx lr1969entry:1970  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1971  %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1972  %a = and <16 x i8> %x, %y11973  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1974  ret <16 x i8> %b1975}1976 1977define arm_aapcs_vfpcc <4 x i32> @ornot_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1978; CHECK-LABEL: ornot_v4i32_y:1979; CHECK:       @ %bb.0: @ %entry1980; CHECK-NEXT:    vctp.32 r01981; CHECK-NEXT:    vpst1982; CHECK-NEXT:    vornt q1, q0, q11983; CHECK-NEXT:    vmov q0, q11984; CHECK-NEXT:    bx lr1985entry:1986  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1987  %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>1988  %a = or <4 x i32> %x, %y11989  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1990  ret <4 x i32> %b1991}1992 1993define arm_aapcs_vfpcc <8 x i16> @ornot_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1994; CHECK-LABEL: ornot_v8i16_y:1995; CHECK:       @ %bb.0: @ %entry1996; CHECK-NEXT:    vctp.16 r01997; CHECK-NEXT:    vpst1998; CHECK-NEXT:    vornt q1, q0, q11999; CHECK-NEXT:    vmov q0, q12000; CHECK-NEXT:    bx lr2001entry:2002  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2003  %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>2004  %a = or <8 x i16> %x, %y12005  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2006  ret <8 x i16> %b2007}2008 2009define arm_aapcs_vfpcc <16 x i8> @ornot_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2010; CHECK-LABEL: ornot_v16i8_y:2011; CHECK:       @ %bb.0: @ %entry2012; CHECK-NEXT:    vctp.8 r02013; CHECK-NEXT:    vpst2014; CHECK-NEXT:    vornt q1, q0, q12015; CHECK-NEXT:    vmov q0, q12016; CHECK-NEXT:    bx lr2017entry:2018  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2019  %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>2020  %a = or <16 x i8> %x, %y12021  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2022  ret <16 x i8> %b2023}2024 2025define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2026; CHECK-LABEL: fadd_v4f32_y:2027; CHECK:       @ %bb.0: @ %entry2028; CHECK-NEXT:    vctp.32 r02029; CHECK-NEXT:    vpst2030; CHECK-NEXT:    vaddt.f32 q1, q0, q12031; CHECK-NEXT:    vmov q0, q12032; CHECK-NEXT:    bx lr2033entry:2034  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2035  %a = fadd <4 x float> %x, %y2036  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2037  ret <4 x float> %b2038}2039 2040define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2041; CHECK-LABEL: fadd_v8f16_y:2042; CHECK:       @ %bb.0: @ %entry2043; CHECK-NEXT:    vctp.16 r02044; CHECK-NEXT:    vpst2045; CHECK-NEXT:    vaddt.f16 q1, q0, q12046; CHECK-NEXT:    vmov q0, q12047; CHECK-NEXT:    bx lr2048entry:2049  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2050  %a = fadd <8 x half> %x, %y2051  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2052  ret <8 x half> %b2053}2054 2055define arm_aapcs_vfpcc <4 x float> @fsub_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2056; CHECK-LABEL: fsub_v4f32_y:2057; CHECK:       @ %bb.0: @ %entry2058; CHECK-NEXT:    vctp.32 r02059; CHECK-NEXT:    vpst2060; CHECK-NEXT:    vsubt.f32 q1, q0, q12061; CHECK-NEXT:    vmov q0, q12062; CHECK-NEXT:    bx lr2063entry:2064  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2065  %a = fsub <4 x float> %x, %y2066  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2067  ret <4 x float> %b2068}2069 2070define arm_aapcs_vfpcc <8 x half> @fsub_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2071; CHECK-LABEL: fsub_v8f16_y:2072; CHECK:       @ %bb.0: @ %entry2073; CHECK-NEXT:    vctp.16 r02074; CHECK-NEXT:    vpst2075; CHECK-NEXT:    vsubt.f16 q1, q0, q12076; CHECK-NEXT:    vmov q0, q12077; CHECK-NEXT:    bx lr2078entry:2079  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2080  %a = fsub <8 x half> %x, %y2081  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2082  ret <8 x half> %b2083}2084 2085define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2086; CHECK-LABEL: fmul_v4f32_y:2087; CHECK:       @ %bb.0: @ %entry2088; CHECK-NEXT:    vctp.32 r02089; CHECK-NEXT:    vpst2090; CHECK-NEXT:    vmult.f32 q1, q0, q12091; CHECK-NEXT:    vmov q0, q12092; CHECK-NEXT:    bx lr2093entry:2094  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2095  %a = fmul <4 x float> %x, %y2096  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2097  ret <4 x float> %b2098}2099 2100define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2101; CHECK-LABEL: fmul_v8f16_y:2102; CHECK:       @ %bb.0: @ %entry2103; CHECK-NEXT:    vctp.16 r02104; CHECK-NEXT:    vpst2105; CHECK-NEXT:    vmult.f16 q1, q0, q12106; CHECK-NEXT:    vmov q0, q12107; CHECK-NEXT:    bx lr2108entry:2109  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2110  %a = fmul <8 x half> %x, %y2111  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2112  ret <8 x half> %b2113}2114 2115define arm_aapcs_vfpcc <4 x float> @fdiv_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2116; CHECK-LABEL: fdiv_v4f32_y:2117; CHECK:       @ %bb.0: @ %entry2118; CHECK-NEXT:    vdiv.f32 s3, s3, s72119; CHECK-NEXT:    vctp.32 r02120; CHECK-NEXT:    vdiv.f32 s2, s2, s62121; CHECK-NEXT:    vdiv.f32 s1, s1, s52122; CHECK-NEXT:    vdiv.f32 s0, s0, s42123; CHECK-NEXT:    vpst2124; CHECK-NEXT:    vmovt q1, q02125; CHECK-NEXT:    vmov q0, q12126; CHECK-NEXT:    bx lr2127entry:2128  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2129  %a = fdiv <4 x float> %x, %y2130  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2131  ret <4 x float> %b2132}2133 2134define arm_aapcs_vfpcc <8 x half> @fdiv_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2135; CHECK-LABEL: fdiv_v8f16_y:2136; CHECK:       @ %bb.0: @ %entry2137; CHECK-NEXT:    vmovx.f16 s10, s02138; CHECK-NEXT:    vmovx.f16 s8, s42139; CHECK-NEXT:    vdiv.f16 s8, s10, s82140; CHECK-NEXT:    vdiv.f16 s0, s0, s42141; CHECK-NEXT:    vins.f16 s0, s82142; CHECK-NEXT:    vmovx.f16 s10, s12143; CHECK-NEXT:    vmovx.f16 s8, s52144; CHECK-NEXT:    vdiv.f16 s1, s1, s52145; CHECK-NEXT:    vdiv.f16 s8, s10, s82146; CHECK-NEXT:    vmovx.f16 s10, s22147; CHECK-NEXT:    vins.f16 s1, s82148; CHECK-NEXT:    vmovx.f16 s8, s62149; CHECK-NEXT:    vdiv.f16 s8, s10, s82150; CHECK-NEXT:    vdiv.f16 s2, s2, s62151; CHECK-NEXT:    vins.f16 s2, s82152; CHECK-NEXT:    vmovx.f16 s10, s32153; CHECK-NEXT:    vmovx.f16 s8, s72154; CHECK-NEXT:    vdiv.f16 s3, s3, s72155; CHECK-NEXT:    vdiv.f16 s8, s10, s82156; CHECK-NEXT:    vctp.16 r02157; CHECK-NEXT:    vins.f16 s3, s82158; CHECK-NEXT:    vpst2159; CHECK-NEXT:    vmovt q1, q02160; CHECK-NEXT:    vmov q0, q12161; CHECK-NEXT:    bx lr2162entry:2163  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2164  %a = fdiv <8 x half> %x, %y2165  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2166  ret <8 x half> %b2167}2168 2169define arm_aapcs_vfpcc <4 x float> @fmai_v4f32_y(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {2170; CHECK-LABEL: fmai_v4f32_y:2171; CHECK:       @ %bb.0: @ %entry2172; CHECK-NEXT:    vfma.f32 q0, q1, q22173; CHECK-NEXT:    vctp.32 r02174; CHECK-NEXT:    vpst2175; CHECK-NEXT:    vmovt q1, q02176; CHECK-NEXT:    vmov q0, q12177; CHECK-NEXT:    bx lr2178entry:2179  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2180  %a = call <4 x float> @llvm.fma.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %x)2181  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2182  ret <4 x float> %b2183}2184 2185define arm_aapcs_vfpcc <8 x half> @fmai_v8f16_y(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {2186; CHECK-LABEL: fmai_v8f16_y:2187; CHECK:       @ %bb.0: @ %entry2188; CHECK-NEXT:    vfma.f16 q0, q1, q22189; CHECK-NEXT:    vctp.16 r02190; CHECK-NEXT:    vpst2191; CHECK-NEXT:    vmovt q1, q02192; CHECK-NEXT:    vmov q0, q12193; CHECK-NEXT:    bx lr2194entry:2195  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2196  %a = call <8 x half> @llvm.fma.v8f16(<8 x half> %y, <8 x half> %z, <8 x half> %x)2197  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2198  ret <8 x half> %b2199}2200 2201define arm_aapcs_vfpcc <4 x float> @fma_v4f32_y(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {2202; CHECK-LABEL: fma_v4f32_y:2203; CHECK:       @ %bb.0: @ %entry2204; CHECK-NEXT:    vfma.f32 q0, q1, q22205; CHECK-NEXT:    vctp.32 r02206; CHECK-NEXT:    vpst2207; CHECK-NEXT:    vmovt q1, q02208; CHECK-NEXT:    vmov q0, q12209; CHECK-NEXT:    bx lr2210entry:2211  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2212  %m = fmul fast <4 x float> %y, %z2213  %a = fadd fast <4 x float> %m, %x2214  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2215  ret <4 x float> %b2216}2217 2218define arm_aapcs_vfpcc <8 x half> @fma_v8f16_y(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {2219; CHECK-LABEL: fma_v8f16_y:2220; CHECK:       @ %bb.0: @ %entry2221; CHECK-NEXT:    vfma.f16 q0, q1, q22222; CHECK-NEXT:    vctp.16 r02223; CHECK-NEXT:    vpst2224; CHECK-NEXT:    vmovt q1, q02225; CHECK-NEXT:    vmov q0, q12226; CHECK-NEXT:    bx lr2227entry:2228  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2229  %m = fmul fast <8 x half> %y, %z2230  %a = fadd fast <8 x half> %m, %x2231  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2232  ret <8 x half> %b2233}2234 2235define arm_aapcs_vfpcc <4 x i32> @icmp_slt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2236; CHECK-LABEL: icmp_slt_v4i32_y:2237; CHECK:       @ %bb.0: @ %entry2238; CHECK-NEXT:    vctp.32 r02239; CHECK-NEXT:    vpst2240; CHECK-NEXT:    vmint.s32 q1, q0, q12241; CHECK-NEXT:    vmov q0, q12242; CHECK-NEXT:    bx lr2243entry:2244  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2245  %a1 = icmp slt <4 x i32> %x, %y2246  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y2247  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2248  ret <4 x i32> %b2249}2250 2251define arm_aapcs_vfpcc <8 x i16> @icmp_slt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2252; CHECK-LABEL: icmp_slt_v8i16_y:2253; CHECK:       @ %bb.0: @ %entry2254; CHECK-NEXT:    vctp.16 r02255; CHECK-NEXT:    vpst2256; CHECK-NEXT:    vmint.s16 q1, q0, q12257; CHECK-NEXT:    vmov q0, q12258; CHECK-NEXT:    bx lr2259entry:2260  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2261  %a1 = icmp slt <8 x i16> %x, %y2262  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y2263  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2264  ret <8 x i16> %b2265}2266 2267define arm_aapcs_vfpcc <16 x i8> @icmp_slt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2268; CHECK-LABEL: icmp_slt_v16i8_y:2269; CHECK:       @ %bb.0: @ %entry2270; CHECK-NEXT:    vctp.8 r02271; CHECK-NEXT:    vpst2272; CHECK-NEXT:    vmint.s8 q1, q0, q12273; CHECK-NEXT:    vmov q0, q12274; CHECK-NEXT:    bx lr2275entry:2276  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2277  %a1 = icmp slt <16 x i8> %x, %y2278  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y2279  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2280  ret <16 x i8> %b2281}2282 2283define arm_aapcs_vfpcc <4 x i32> @icmp_sgt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2284; CHECK-LABEL: icmp_sgt_v4i32_y:2285; CHECK:       @ %bb.0: @ %entry2286; CHECK-NEXT:    vctp.32 r02287; CHECK-NEXT:    vpst2288; CHECK-NEXT:    vmaxt.s32 q1, q0, q12289; CHECK-NEXT:    vmov q0, q12290; CHECK-NEXT:    bx lr2291entry:2292  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2293  %a1 = icmp sgt <4 x i32> %x, %y2294  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y2295  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2296  ret <4 x i32> %b2297}2298 2299define arm_aapcs_vfpcc <8 x i16> @icmp_sgt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2300; CHECK-LABEL: icmp_sgt_v8i16_y:2301; CHECK:       @ %bb.0: @ %entry2302; CHECK-NEXT:    vctp.16 r02303; CHECK-NEXT:    vpst2304; CHECK-NEXT:    vmaxt.s16 q1, q0, q12305; CHECK-NEXT:    vmov q0, q12306; CHECK-NEXT:    bx lr2307entry:2308  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2309  %a1 = icmp sgt <8 x i16> %x, %y2310  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y2311  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2312  ret <8 x i16> %b2313}2314 2315define arm_aapcs_vfpcc <16 x i8> @icmp_sgt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2316; CHECK-LABEL: icmp_sgt_v16i8_y:2317; CHECK:       @ %bb.0: @ %entry2318; CHECK-NEXT:    vctp.8 r02319; CHECK-NEXT:    vpst2320; CHECK-NEXT:    vmaxt.s8 q1, q0, q12321; CHECK-NEXT:    vmov q0, q12322; CHECK-NEXT:    bx lr2323entry:2324  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2325  %a1 = icmp sgt <16 x i8> %x, %y2326  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y2327  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2328  ret <16 x i8> %b2329}2330 2331define arm_aapcs_vfpcc <4 x i32> @icmp_ult_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2332; CHECK-LABEL: icmp_ult_v4i32_y:2333; CHECK:       @ %bb.0: @ %entry2334; CHECK-NEXT:    vctp.32 r02335; CHECK-NEXT:    vpst2336; CHECK-NEXT:    vmint.u32 q1, q0, q12337; CHECK-NEXT:    vmov q0, q12338; CHECK-NEXT:    bx lr2339entry:2340  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2341  %a1 = icmp ult <4 x i32> %x, %y2342  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y2343  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2344  ret <4 x i32> %b2345}2346 2347define arm_aapcs_vfpcc <8 x i16> @icmp_ult_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2348; CHECK-LABEL: icmp_ult_v8i16_y:2349; CHECK:       @ %bb.0: @ %entry2350; CHECK-NEXT:    vctp.16 r02351; CHECK-NEXT:    vpst2352; CHECK-NEXT:    vmint.u16 q1, q0, q12353; CHECK-NEXT:    vmov q0, q12354; CHECK-NEXT:    bx lr2355entry:2356  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2357  %a1 = icmp ult <8 x i16> %x, %y2358  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y2359  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2360  ret <8 x i16> %b2361}2362 2363define arm_aapcs_vfpcc <16 x i8> @icmp_ult_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2364; CHECK-LABEL: icmp_ult_v16i8_y:2365; CHECK:       @ %bb.0: @ %entry2366; CHECK-NEXT:    vctp.8 r02367; CHECK-NEXT:    vpst2368; CHECK-NEXT:    vmint.u8 q1, q0, q12369; CHECK-NEXT:    vmov q0, q12370; CHECK-NEXT:    bx lr2371entry:2372  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2373  %a1 = icmp ult <16 x i8> %x, %y2374  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y2375  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2376  ret <16 x i8> %b2377}2378 2379define arm_aapcs_vfpcc <4 x i32> @icmp_ugt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2380; CHECK-LABEL: icmp_ugt_v4i32_y:2381; CHECK:       @ %bb.0: @ %entry2382; CHECK-NEXT:    vctp.32 r02383; CHECK-NEXT:    vpst2384; CHECK-NEXT:    vmaxt.u32 q1, q0, q12385; CHECK-NEXT:    vmov q0, q12386; CHECK-NEXT:    bx lr2387entry:2388  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2389  %a1 = icmp ugt <4 x i32> %x, %y2390  %a = select <4 x i1> %a1, <4 x i32> %x, <4 x i32> %y2391  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2392  ret <4 x i32> %b2393}2394 2395define arm_aapcs_vfpcc <8 x i16> @icmp_ugt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2396; CHECK-LABEL: icmp_ugt_v8i16_y:2397; CHECK:       @ %bb.0: @ %entry2398; CHECK-NEXT:    vctp.16 r02399; CHECK-NEXT:    vpst2400; CHECK-NEXT:    vmaxt.u16 q1, q0, q12401; CHECK-NEXT:    vmov q0, q12402; CHECK-NEXT:    bx lr2403entry:2404  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2405  %a1 = icmp ugt <8 x i16> %x, %y2406  %a = select <8 x i1> %a1, <8 x i16> %x, <8 x i16> %y2407  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2408  ret <8 x i16> %b2409}2410 2411define arm_aapcs_vfpcc <16 x i8> @icmp_ugt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2412; CHECK-LABEL: icmp_ugt_v16i8_y:2413; CHECK:       @ %bb.0: @ %entry2414; CHECK-NEXT:    vctp.8 r02415; CHECK-NEXT:    vpst2416; CHECK-NEXT:    vmaxt.u8 q1, q0, q12417; CHECK-NEXT:    vmov q0, q12418; CHECK-NEXT:    bx lr2419entry:2420  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2421  %a1 = icmp ugt <16 x i8> %x, %y2422  %a = select <16 x i1> %a1, <16 x i8> %x, <16 x i8> %y2423  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2424  ret <16 x i8> %b2425}2426 2427define arm_aapcs_vfpcc <4 x float> @fcmp_fast_olt_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2428; CHECK-LABEL: fcmp_fast_olt_v4f32_y:2429; CHECK:       @ %bb.0: @ %entry2430; CHECK-NEXT:    vctp.32 r02431; CHECK-NEXT:    vpst2432; CHECK-NEXT:    vminnmt.f32 q1, q0, q12433; CHECK-NEXT:    vmov q0, q12434; CHECK-NEXT:    bx lr2435entry:2436  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2437  %a1 = fcmp fast olt <4 x float> %x, %y2438  %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y2439  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2440  ret <4 x float> %b2441}2442 2443define arm_aapcs_vfpcc <8 x half> @fcmp_fast_olt_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2444; CHECK-LABEL: fcmp_fast_olt_v8f16_y:2445; CHECK:       @ %bb.0: @ %entry2446; CHECK-NEXT:    vctp.16 r02447; CHECK-NEXT:    vpst2448; CHECK-NEXT:    vminnmt.f16 q1, q0, q12449; CHECK-NEXT:    vmov q0, q12450; CHECK-NEXT:    bx lr2451entry:2452  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2453  %a1 = fcmp fast olt <8 x half> %x, %y2454  %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y2455  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2456  ret <8 x half> %b2457}2458 2459define arm_aapcs_vfpcc <4 x float> @fcmp_fast_ogt_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2460; CHECK-LABEL: fcmp_fast_ogt_v4f32_y:2461; CHECK:       @ %bb.0: @ %entry2462; CHECK-NEXT:    vctp.32 r02463; CHECK-NEXT:    vpst2464; CHECK-NEXT:    vmaxnmt.f32 q1, q0, q12465; CHECK-NEXT:    vmov q0, q12466; CHECK-NEXT:    bx lr2467entry:2468  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2469  %a1 = fcmp fast ogt <4 x float> %x, %y2470  %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y2471  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2472  ret <4 x float> %b2473}2474 2475define arm_aapcs_vfpcc <8 x half> @fcmp_fast_ogt_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2476; CHECK-LABEL: fcmp_fast_ogt_v8f16_y:2477; CHECK:       @ %bb.0: @ %entry2478; CHECK-NEXT:    vctp.16 r02479; CHECK-NEXT:    vpst2480; CHECK-NEXT:    vmaxnmt.f16 q1, q0, q12481; CHECK-NEXT:    vmov q0, q12482; CHECK-NEXT:    bx lr2483entry:2484  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2485  %a1 = fcmp fast ogt <8 x half> %x, %y2486  %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y2487  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2488  ret <8 x half> %b2489}2490 2491define arm_aapcs_vfpcc <4 x i32> @sadd_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2492; CHECK-LABEL: sadd_sat_v4i32_y:2493; CHECK:       @ %bb.0: @ %entry2494; CHECK-NEXT:    vctp.32 r02495; CHECK-NEXT:    vpst2496; CHECK-NEXT:    vqaddt.s32 q1, q0, q12497; CHECK-NEXT:    vmov q0, q12498; CHECK-NEXT:    bx lr2499entry:2500  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2501  %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2502  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2503  ret <4 x i32> %b2504}2505 2506define arm_aapcs_vfpcc <8 x i16> @sadd_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2507; CHECK-LABEL: sadd_sat_v8i16_y:2508; CHECK:       @ %bb.0: @ %entry2509; CHECK-NEXT:    vctp.16 r02510; CHECK-NEXT:    vpst2511; CHECK-NEXT:    vqaddt.s16 q1, q0, q12512; CHECK-NEXT:    vmov q0, q12513; CHECK-NEXT:    bx lr2514entry:2515  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2516  %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2517  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2518  ret <8 x i16> %b2519}2520 2521define arm_aapcs_vfpcc <16 x i8> @sadd_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2522; CHECK-LABEL: sadd_sat_v16i8_y:2523; CHECK:       @ %bb.0: @ %entry2524; CHECK-NEXT:    vctp.8 r02525; CHECK-NEXT:    vpst2526; CHECK-NEXT:    vqaddt.s8 q1, q0, q12527; CHECK-NEXT:    vmov q0, q12528; CHECK-NEXT:    bx lr2529entry:2530  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2531  %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2532  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2533  ret <16 x i8> %b2534}2535 2536define arm_aapcs_vfpcc <4 x i32> @uadd_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2537; CHECK-LABEL: uadd_sat_v4i32_y:2538; CHECK:       @ %bb.0: @ %entry2539; CHECK-NEXT:    vctp.32 r02540; CHECK-NEXT:    vpst2541; CHECK-NEXT:    vqaddt.u32 q1, q0, q12542; CHECK-NEXT:    vmov q0, q12543; CHECK-NEXT:    bx lr2544entry:2545  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2546  %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2547  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2548  ret <4 x i32> %b2549}2550 2551define arm_aapcs_vfpcc <8 x i16> @uadd_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2552; CHECK-LABEL: uadd_sat_v8i16_y:2553; CHECK:       @ %bb.0: @ %entry2554; CHECK-NEXT:    vctp.16 r02555; CHECK-NEXT:    vpst2556; CHECK-NEXT:    vqaddt.u16 q1, q0, q12557; CHECK-NEXT:    vmov q0, q12558; CHECK-NEXT:    bx lr2559entry:2560  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2561  %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2562  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2563  ret <8 x i16> %b2564}2565 2566define arm_aapcs_vfpcc <16 x i8> @uadd_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2567; CHECK-LABEL: uadd_sat_v16i8_y:2568; CHECK:       @ %bb.0: @ %entry2569; CHECK-NEXT:    vctp.8 r02570; CHECK-NEXT:    vpst2571; CHECK-NEXT:    vqaddt.u8 q1, q0, q12572; CHECK-NEXT:    vmov q0, q12573; CHECK-NEXT:    bx lr2574entry:2575  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2576  %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2577  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2578  ret <16 x i8> %b2579}2580 2581define arm_aapcs_vfpcc <4 x i32> @ssub_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2582; CHECK-LABEL: ssub_sat_v4i32_y:2583; CHECK:       @ %bb.0: @ %entry2584; CHECK-NEXT:    vctp.32 r02585; CHECK-NEXT:    vpst2586; CHECK-NEXT:    vqsubt.s32 q1, q0, q12587; CHECK-NEXT:    vmov q0, q12588; CHECK-NEXT:    bx lr2589entry:2590  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2591  %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2592  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2593  ret <4 x i32> %b2594}2595 2596define arm_aapcs_vfpcc <8 x i16> @ssub_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2597; CHECK-LABEL: ssub_sat_v8i16_y:2598; CHECK:       @ %bb.0: @ %entry2599; CHECK-NEXT:    vctp.16 r02600; CHECK-NEXT:    vpst2601; CHECK-NEXT:    vqsubt.s16 q1, q0, q12602; CHECK-NEXT:    vmov q0, q12603; CHECK-NEXT:    bx lr2604entry:2605  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2606  %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2607  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2608  ret <8 x i16> %b2609}2610 2611define arm_aapcs_vfpcc <16 x i8> @ssub_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2612; CHECK-LABEL: ssub_sat_v16i8_y:2613; CHECK:       @ %bb.0: @ %entry2614; CHECK-NEXT:    vctp.8 r02615; CHECK-NEXT:    vpst2616; CHECK-NEXT:    vqsubt.s8 q1, q0, q12617; CHECK-NEXT:    vmov q0, q12618; CHECK-NEXT:    bx lr2619entry:2620  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2621  %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2622  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2623  ret <16 x i8> %b2624}2625 2626define arm_aapcs_vfpcc <4 x i32> @usub_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2627; CHECK-LABEL: usub_sat_v4i32_y:2628; CHECK:       @ %bb.0: @ %entry2629; CHECK-NEXT:    vctp.32 r02630; CHECK-NEXT:    vpst2631; CHECK-NEXT:    vqsubt.u32 q1, q0, q12632; CHECK-NEXT:    vmov q0, q12633; CHECK-NEXT:    bx lr2634entry:2635  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2636  %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2637  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2638  ret <4 x i32> %b2639}2640 2641define arm_aapcs_vfpcc <8 x i16> @usub_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2642; CHECK-LABEL: usub_sat_v8i16_y:2643; CHECK:       @ %bb.0: @ %entry2644; CHECK-NEXT:    vctp.16 r02645; CHECK-NEXT:    vpst2646; CHECK-NEXT:    vqsubt.u16 q1, q0, q12647; CHECK-NEXT:    vmov q0, q12648; CHECK-NEXT:    bx lr2649entry:2650  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2651  %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2652  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2653  ret <8 x i16> %b2654}2655 2656define arm_aapcs_vfpcc <16 x i8> @usub_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2657; CHECK-LABEL: usub_sat_v16i8_y:2658; CHECK:       @ %bb.0: @ %entry2659; CHECK-NEXT:    vctp.8 r02660; CHECK-NEXT:    vpst2661; CHECK-NEXT:    vqsubt.u8 q1, q0, q12662; CHECK-NEXT:    vmov q0, q12663; CHECK-NEXT:    bx lr2664entry:2665  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2666  %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2667  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2668  ret <16 x i8> %b2669}2670 2671define arm_aapcs_vfpcc <4 x i32> @addqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2672; CHECK-LABEL: addqr_v4i32_y:2673; CHECK:       @ %bb.0: @ %entry2674; CHECK-NEXT:    vdup.32 q1, r02675; CHECK-NEXT:    vctp.32 r12676; CHECK-NEXT:    vpst2677; CHECK-NEXT:    vaddt.i32 q1, q0, r02678; CHECK-NEXT:    vmov q0, q12679; CHECK-NEXT:    bx lr2680entry:2681  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2682  %i = insertelement <4 x i32> undef, i32 %y, i32 02683  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2684  %a = add <4 x i32> %x, %ys2685  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys2686  ret <4 x i32> %b2687}2688 2689define arm_aapcs_vfpcc <8 x i16> @addqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2690; CHECK-LABEL: addqr_v8i16_y:2691; CHECK:       @ %bb.0: @ %entry2692; CHECK-NEXT:    vdup.16 q1, r02693; CHECK-NEXT:    vctp.16 r12694; CHECK-NEXT:    vpst2695; CHECK-NEXT:    vaddt.i16 q1, q0, r02696; CHECK-NEXT:    vmov q0, q12697; CHECK-NEXT:    bx lr2698entry:2699  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2700  %i = insertelement <8 x i16> undef, i16 %y, i32 02701  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2702  %a = add <8 x i16> %x, %ys2703  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys2704  ret <8 x i16> %b2705}2706 2707define arm_aapcs_vfpcc <16 x i8> @addqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2708; CHECK-LABEL: addqr_v16i8_y:2709; CHECK:       @ %bb.0: @ %entry2710; CHECK-NEXT:    vdup.8 q1, r02711; CHECK-NEXT:    vctp.8 r12712; CHECK-NEXT:    vpst2713; CHECK-NEXT:    vaddt.i8 q1, q0, r02714; CHECK-NEXT:    vmov q0, q12715; CHECK-NEXT:    bx lr2716entry:2717  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2718  %i = insertelement <16 x i8> undef, i8 %y, i32 02719  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2720  %a = add <16 x i8> %x, %ys2721  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys2722  ret <16 x i8> %b2723}2724 2725define arm_aapcs_vfpcc <4 x i32> @subqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2726; CHECK-LABEL: subqr_v4i32_y:2727; CHECK:       @ %bb.0: @ %entry2728; CHECK-NEXT:    vdup.32 q1, r02729; CHECK-NEXT:    vctp.32 r12730; CHECK-NEXT:    vpst2731; CHECK-NEXT:    vsubt.i32 q1, q0, r02732; CHECK-NEXT:    vmov q0, q12733; CHECK-NEXT:    bx lr2734entry:2735  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2736  %i = insertelement <4 x i32> undef, i32 %y, i32 02737  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2738  %a = sub <4 x i32> %x, %ys2739  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys2740  ret <4 x i32> %b2741}2742 2743define arm_aapcs_vfpcc <8 x i16> @subqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2744; CHECK-LABEL: subqr_v8i16_y:2745; CHECK:       @ %bb.0: @ %entry2746; CHECK-NEXT:    vdup.16 q1, r02747; CHECK-NEXT:    vctp.16 r12748; CHECK-NEXT:    vpst2749; CHECK-NEXT:    vsubt.i16 q1, q0, r02750; CHECK-NEXT:    vmov q0, q12751; CHECK-NEXT:    bx lr2752entry:2753  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2754  %i = insertelement <8 x i16> undef, i16 %y, i32 02755  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2756  %a = sub <8 x i16> %x, %ys2757  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys2758  ret <8 x i16> %b2759}2760 2761define arm_aapcs_vfpcc <16 x i8> @subqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2762; CHECK-LABEL: subqr_v16i8_y:2763; CHECK:       @ %bb.0: @ %entry2764; CHECK-NEXT:    vdup.8 q1, r02765; CHECK-NEXT:    vctp.8 r12766; CHECK-NEXT:    vpst2767; CHECK-NEXT:    vsubt.i8 q1, q0, r02768; CHECK-NEXT:    vmov q0, q12769; CHECK-NEXT:    bx lr2770entry:2771  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2772  %i = insertelement <16 x i8> undef, i8 %y, i32 02773  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2774  %a = sub <16 x i8> %x, %ys2775  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys2776  ret <16 x i8> %b2777}2778 2779define arm_aapcs_vfpcc <4 x i32> @mulqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2780; CHECK-LABEL: mulqr_v4i32_y:2781; CHECK:       @ %bb.0: @ %entry2782; CHECK-NEXT:    vdup.32 q1, r02783; CHECK-NEXT:    vctp.32 r12784; CHECK-NEXT:    vpst2785; CHECK-NEXT:    vmult.i32 q1, q0, r02786; CHECK-NEXT:    vmov q0, q12787; CHECK-NEXT:    bx lr2788entry:2789  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2790  %i = insertelement <4 x i32> undef, i32 %y, i32 02791  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2792  %a = mul <4 x i32> %x, %ys2793  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys2794  ret <4 x i32> %b2795}2796 2797define arm_aapcs_vfpcc <8 x i16> @mulqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2798; CHECK-LABEL: mulqr_v8i16_y:2799; CHECK:       @ %bb.0: @ %entry2800; CHECK-NEXT:    vdup.16 q1, r02801; CHECK-NEXT:    vctp.16 r12802; CHECK-NEXT:    vpst2803; CHECK-NEXT:    vmult.i16 q1, q0, r02804; CHECK-NEXT:    vmov q0, q12805; CHECK-NEXT:    bx lr2806entry:2807  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2808  %i = insertelement <8 x i16> undef, i16 %y, i32 02809  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2810  %a = mul <8 x i16> %x, %ys2811  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys2812  ret <8 x i16> %b2813}2814 2815define arm_aapcs_vfpcc <16 x i8> @mulqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2816; CHECK-LABEL: mulqr_v16i8_y:2817; CHECK:       @ %bb.0: @ %entry2818; CHECK-NEXT:    vdup.8 q1, r02819; CHECK-NEXT:    vctp.8 r12820; CHECK-NEXT:    vpst2821; CHECK-NEXT:    vmult.i8 q1, q0, r02822; CHECK-NEXT:    vmov q0, q12823; CHECK-NEXT:    bx lr2824entry:2825  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2826  %i = insertelement <16 x i8> undef, i8 %y, i32 02827  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2828  %a = mul <16 x i8> %x, %ys2829  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys2830  ret <16 x i8> %b2831}2832 2833define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2834; CHECK-LABEL: faddqr_v4f32_y:2835; CHECK:       @ %bb.0: @ %entry2836; CHECK-NEXT:    vmov r1, s42837; CHECK-NEXT:    vctp.32 r02838; CHECK-NEXT:    vdup.32 q1, r12839; CHECK-NEXT:    vpst2840; CHECK-NEXT:    vaddt.f32 q1, q0, r12841; CHECK-NEXT:    vmov q0, q12842; CHECK-NEXT:    bx lr2843entry:2844  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2845  %i = insertelement <4 x float> undef, float %y, i32 02846  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2847  %a = fadd <4 x float> %x, %ys2848  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %ys2849  ret <4 x float> %b2850}2851 2852define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2853; CHECK-LABEL: faddqr_v8f16_y:2854; CHECK:       @ %bb.0: @ %entry2855; CHECK-NEXT:    vmov.f16 r1, s42856; CHECK-NEXT:    vctp.16 r02857; CHECK-NEXT:    vdup.16 q1, r12858; CHECK-NEXT:    vpst2859; CHECK-NEXT:    vaddt.f16 q1, q0, r12860; CHECK-NEXT:    vmov q0, q12861; CHECK-NEXT:    bx lr2862entry:2863  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2864  %i = insertelement <8 x half> undef, half %y, i32 02865  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2866  %a = fadd <8 x half> %x, %ys2867  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %ys2868  ret <8 x half> %b2869}2870 2871define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2872; CHECK-LABEL: fsubqr_v4f32_y:2873; CHECK:       @ %bb.0: @ %entry2874; CHECK-NEXT:    vmov r1, s42875; CHECK-NEXT:    vctp.32 r02876; CHECK-NEXT:    vdup.32 q1, r12877; CHECK-NEXT:    vpst2878; CHECK-NEXT:    vsubt.f32 q1, q0, r12879; CHECK-NEXT:    vmov q0, q12880; CHECK-NEXT:    bx lr2881entry:2882  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2883  %i = insertelement <4 x float> undef, float %y, i32 02884  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2885  %a = fsub <4 x float> %x, %ys2886  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %ys2887  ret <4 x float> %b2888}2889 2890define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2891; CHECK-LABEL: fsubqr_v8f16_y:2892; CHECK:       @ %bb.0: @ %entry2893; CHECK-NEXT:    vmov.f16 r1, s42894; CHECK-NEXT:    vctp.16 r02895; CHECK-NEXT:    vdup.16 q1, r12896; CHECK-NEXT:    vpst2897; CHECK-NEXT:    vsubt.f16 q1, q0, r12898; CHECK-NEXT:    vmov q0, q12899; CHECK-NEXT:    bx lr2900entry:2901  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2902  %i = insertelement <8 x half> undef, half %y, i32 02903  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2904  %a = fsub <8 x half> %x, %ys2905  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %ys2906  ret <8 x half> %b2907}2908 2909define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2910; CHECK-LABEL: fmulqr_v4f32_y:2911; CHECK:       @ %bb.0: @ %entry2912; CHECK-NEXT:    vmov r1, s42913; CHECK-NEXT:    vctp.32 r02914; CHECK-NEXT:    vdup.32 q1, r12915; CHECK-NEXT:    vpst2916; CHECK-NEXT:    vmult.f32 q1, q0, r12917; CHECK-NEXT:    vmov q0, q12918; CHECK-NEXT:    bx lr2919entry:2920  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2921  %i = insertelement <4 x float> undef, float %y, i32 02922  %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2923  %a = fmul <4 x float> %x, %ys2924  %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %ys2925  ret <4 x float> %b2926}2927 2928define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2929; CHECK-LABEL: fmulqr_v8f16_y:2930; CHECK:       @ %bb.0: @ %entry2931; CHECK-NEXT:    vmov.f16 r1, s42932; CHECK-NEXT:    vctp.16 r02933; CHECK-NEXT:    vdup.16 q1, r12934; CHECK-NEXT:    vpst2935; CHECK-NEXT:    vmult.f16 q1, q0, r12936; CHECK-NEXT:    vmov q0, q12937; CHECK-NEXT:    bx lr2938entry:2939  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2940  %i = insertelement <8 x half> undef, half %y, i32 02941  %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2942  %a = fmul <8 x half> %x, %ys2943  %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %ys2944  ret <8 x half> %b2945}2946 2947define arm_aapcs_vfpcc <4 x i32> @sadd_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2948; CHECK-LABEL: sadd_satqr_v4i32_y:2949; CHECK:       @ %bb.0: @ %entry2950; CHECK-NEXT:    vdup.32 q1, r02951; CHECK-NEXT:    vctp.32 r12952; CHECK-NEXT:    vpst2953; CHECK-NEXT:    vqaddt.s32 q1, q0, r02954; CHECK-NEXT:    vmov q0, q12955; CHECK-NEXT:    bx lr2956entry:2957  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2958  %i = insertelement <4 x i32> undef, i32 %y, i32 02959  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2960  %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)2961  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys2962  ret <4 x i32> %b2963}2964 2965define arm_aapcs_vfpcc <8 x i16> @sadd_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2966; CHECK-LABEL: sadd_satqr_v8i16_y:2967; CHECK:       @ %bb.0: @ %entry2968; CHECK-NEXT:    vdup.16 q1, r02969; CHECK-NEXT:    vctp.16 r12970; CHECK-NEXT:    vpst2971; CHECK-NEXT:    vqaddt.s16 q1, q0, r02972; CHECK-NEXT:    vmov q0, q12973; CHECK-NEXT:    bx lr2974entry:2975  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2976  %i = insertelement <8 x i16> undef, i16 %y, i32 02977  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2978  %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)2979  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys2980  ret <8 x i16> %b2981}2982 2983define arm_aapcs_vfpcc <16 x i8> @sadd_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2984; CHECK-LABEL: sadd_satqr_v16i8_y:2985; CHECK:       @ %bb.0: @ %entry2986; CHECK-NEXT:    vdup.8 q1, r02987; CHECK-NEXT:    vctp.8 r12988; CHECK-NEXT:    vpst2989; CHECK-NEXT:    vqaddt.s8 q1, q0, r02990; CHECK-NEXT:    vmov q0, q12991; CHECK-NEXT:    bx lr2992entry:2993  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2994  %i = insertelement <16 x i8> undef, i8 %y, i32 02995  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2996  %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)2997  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys2998  ret <16 x i8> %b2999}3000 3001define arm_aapcs_vfpcc <4 x i32> @uadd_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3002; CHECK-LABEL: uadd_satqr_v4i32_y:3003; CHECK:       @ %bb.0: @ %entry3004; CHECK-NEXT:    vdup.32 q1, r03005; CHECK-NEXT:    vctp.32 r13006; CHECK-NEXT:    vpst3007; CHECK-NEXT:    vqaddt.u32 q1, q0, r03008; CHECK-NEXT:    vmov q0, q13009; CHECK-NEXT:    bx lr3010entry:3011  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3012  %i = insertelement <4 x i32> undef, i32 %y, i32 03013  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3014  %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3015  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3016  ret <4 x i32> %b3017}3018 3019define arm_aapcs_vfpcc <8 x i16> @uadd_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3020; CHECK-LABEL: uadd_satqr_v8i16_y:3021; CHECK:       @ %bb.0: @ %entry3022; CHECK-NEXT:    vdup.16 q1, r03023; CHECK-NEXT:    vctp.16 r13024; CHECK-NEXT:    vpst3025; CHECK-NEXT:    vqaddt.u16 q1, q0, r03026; CHECK-NEXT:    vmov q0, q13027; CHECK-NEXT:    bx lr3028entry:3029  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3030  %i = insertelement <8 x i16> undef, i16 %y, i32 03031  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3032  %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3033  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3034  ret <8 x i16> %b3035}3036 3037define arm_aapcs_vfpcc <16 x i8> @uadd_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3038; CHECK-LABEL: uadd_satqr_v16i8_y:3039; CHECK:       @ %bb.0: @ %entry3040; CHECK-NEXT:    vdup.8 q1, r03041; CHECK-NEXT:    vctp.8 r13042; CHECK-NEXT:    vpst3043; CHECK-NEXT:    vqaddt.u8 q1, q0, r03044; CHECK-NEXT:    vmov q0, q13045; CHECK-NEXT:    bx lr3046entry:3047  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3048  %i = insertelement <16 x i8> undef, i8 %y, i32 03049  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3050  %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3051  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3052  ret <16 x i8> %b3053}3054 3055define arm_aapcs_vfpcc <4 x i32> @ssub_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3056; CHECK-LABEL: ssub_satqr_v4i32_y:3057; CHECK:       @ %bb.0: @ %entry3058; CHECK-NEXT:    vdup.32 q1, r03059; CHECK-NEXT:    vctp.32 r13060; CHECK-NEXT:    vpst3061; CHECK-NEXT:    vqsubt.s32 q1, q0, r03062; CHECK-NEXT:    vmov q0, q13063; CHECK-NEXT:    bx lr3064entry:3065  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3066  %i = insertelement <4 x i32> undef, i32 %y, i32 03067  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3068  %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3069  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3070  ret <4 x i32> %b3071}3072 3073define arm_aapcs_vfpcc <8 x i16> @ssub_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3074; CHECK-LABEL: ssub_satqr_v8i16_y:3075; CHECK:       @ %bb.0: @ %entry3076; CHECK-NEXT:    vdup.16 q1, r03077; CHECK-NEXT:    vctp.16 r13078; CHECK-NEXT:    vpst3079; CHECK-NEXT:    vqsubt.s16 q1, q0, r03080; CHECK-NEXT:    vmov q0, q13081; CHECK-NEXT:    bx lr3082entry:3083  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3084  %i = insertelement <8 x i16> undef, i16 %y, i32 03085  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3086  %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3087  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3088  ret <8 x i16> %b3089}3090 3091define arm_aapcs_vfpcc <16 x i8> @ssub_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3092; CHECK-LABEL: ssub_satqr_v16i8_y:3093; CHECK:       @ %bb.0: @ %entry3094; CHECK-NEXT:    vdup.8 q1, r03095; CHECK-NEXT:    vctp.8 r13096; CHECK-NEXT:    vpst3097; CHECK-NEXT:    vqsubt.s8 q1, q0, r03098; CHECK-NEXT:    vmov q0, q13099; CHECK-NEXT:    bx lr3100entry:3101  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3102  %i = insertelement <16 x i8> undef, i8 %y, i32 03103  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3104  %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3105  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3106  ret <16 x i8> %b3107}3108 3109define arm_aapcs_vfpcc <4 x i32> @usub_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3110; CHECK-LABEL: usub_satqr_v4i32_y:3111; CHECK:       @ %bb.0: @ %entry3112; CHECK-NEXT:    vdup.32 q1, r03113; CHECK-NEXT:    vctp.32 r13114; CHECK-NEXT:    vpst3115; CHECK-NEXT:    vqsubt.u32 q1, q0, r03116; CHECK-NEXT:    vmov q0, q13117; CHECK-NEXT:    bx lr3118entry:3119  %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3120  %i = insertelement <4 x i32> undef, i32 %y, i32 03121  %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3122  %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3123  %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3124  ret <4 x i32> %b3125}3126 3127define arm_aapcs_vfpcc <8 x i16> @usub_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3128; CHECK-LABEL: usub_satqr_v8i16_y:3129; CHECK:       @ %bb.0: @ %entry3130; CHECK-NEXT:    vdup.16 q1, r03131; CHECK-NEXT:    vctp.16 r13132; CHECK-NEXT:    vpst3133; CHECK-NEXT:    vqsubt.u16 q1, q0, r03134; CHECK-NEXT:    vmov q0, q13135; CHECK-NEXT:    bx lr3136entry:3137  %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3138  %i = insertelement <8 x i16> undef, i16 %y, i32 03139  %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3140  %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3141  %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3142  ret <8 x i16> %b3143}3144 3145define arm_aapcs_vfpcc <16 x i8> @usub_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3146; CHECK-LABEL: usub_satqr_v16i8_y:3147; CHECK:       @ %bb.0: @ %entry3148; CHECK-NEXT:    vdup.8 q1, r03149; CHECK-NEXT:    vctp.8 r13150; CHECK-NEXT:    vpst3151; CHECK-NEXT:    vqsubt.u8 q1, q0, r03152; CHECK-NEXT:    vmov q0, q13153; CHECK-NEXT:    bx lr3154entry:3155  %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3156  %i = insertelement <16 x i8> undef, i8 %y, i32 03157  %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3158  %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3159  %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3160  ret <16 x i8> %b3161}3162 3163declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)3164declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)3165declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)3166declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)3167declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)3168declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)3169declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)3170declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)3171declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)3172declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)3173declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)3174declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)3175 3176declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)3177declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)3178 3179declare <16 x i1> @llvm.arm.mve.vctp8(i32)3180declare <8 x i1> @llvm.arm.mve.vctp16(i32)3181declare <4 x i1> @llvm.arm.mve.vctp32(i32)3182