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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc <4 x i32> @add_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {5; CHECK-LABEL: add_v4i32_x:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vctp.32 r08; CHECK-NEXT: vpst9; CHECK-NEXT: vaddt.i32 q0, q0, q110; CHECK-NEXT: bx lr11entry:12 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)13 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer14 %b = add <4 x i32> %a, %x15 ret <4 x i32> %b16}17 18define arm_aapcs_vfpcc <8 x i16> @add_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {19; CHECK-LABEL: add_v8i16_x:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vctp.16 r022; CHECK-NEXT: vpst23; CHECK-NEXT: vaddt.i16 q0, q0, q124; CHECK-NEXT: bx lr25entry:26 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)27 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer28 %b = add <8 x i16> %a, %x29 ret <8 x i16> %b30}31 32define arm_aapcs_vfpcc <16 x i8> @add_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {33; CHECK-LABEL: add_v16i8_x:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vctp.8 r036; CHECK-NEXT: vpst37; CHECK-NEXT: vaddt.i8 q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)41 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer42 %b = add <16 x i8> %a, %x43 ret <16 x i8> %b44}45 46define arm_aapcs_vfpcc <4 x i32> @sub_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {47; CHECK-LABEL: sub_v4i32_x:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vctp.32 r050; CHECK-NEXT: vpst51; CHECK-NEXT: vsubt.i32 q0, q0, q152; CHECK-NEXT: bx lr53entry:54 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)55 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer56 %b = sub <4 x i32> %x, %a57 ret <4 x i32> %b58}59 60define arm_aapcs_vfpcc <8 x i16> @sub_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {61; CHECK-LABEL: sub_v8i16_x:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vctp.16 r064; CHECK-NEXT: vpst65; CHECK-NEXT: vsubt.i16 q0, q0, q166; CHECK-NEXT: bx lr67entry:68 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)69 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer70 %b = sub <8 x i16> %x, %a71 ret <8 x i16> %b72}73 74define arm_aapcs_vfpcc <16 x i8> @sub_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {75; CHECK-LABEL: sub_v16i8_x:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vctp.8 r078; CHECK-NEXT: vpst79; CHECK-NEXT: vsubt.i8 q0, q0, q180; CHECK-NEXT: bx lr81entry:82 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)83 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer84 %b = sub <16 x i8> %x, %a85 ret <16 x i8> %b86}87 88define arm_aapcs_vfpcc <4 x i32> @mul_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {89; CHECK-LABEL: mul_v4i32_x:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vctp.32 r092; CHECK-NEXT: vpst93; CHECK-NEXT: vmult.i32 q0, q0, q194; CHECK-NEXT: bx lr95entry:96 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)97 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> <i32 1, i32 1, i32 1, i32 1>98 %b = mul <4 x i32> %a, %x99 ret <4 x i32> %b100}101 102define arm_aapcs_vfpcc <8 x i16> @mul_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {103; CHECK-LABEL: mul_v8i16_x:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vctp.16 r0106; CHECK-NEXT: vpst107; CHECK-NEXT: vmult.i16 q0, q0, q1108; CHECK-NEXT: bx lr109entry:110 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)111 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>112 %b = mul <8 x i16> %a, %x113 ret <8 x i16> %b114}115 116define arm_aapcs_vfpcc <16 x i8> @mul_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {117; CHECK-LABEL: mul_v16i8_x:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vctp.8 r0120; CHECK-NEXT: vpst121; CHECK-NEXT: vmult.i8 q0, q0, q1122; CHECK-NEXT: bx lr123entry:124 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)125 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>126 %b = mul <16 x i8> %a, %x127 ret <16 x i8> %b128}129 130define arm_aapcs_vfpcc <4 x i32> @and_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {131; CHECK-LABEL: and_v4i32_x:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vctp.32 r0134; CHECK-NEXT: vpst135; CHECK-NEXT: vandt q0, q0, q1136; CHECK-NEXT: bx lr137entry:138 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)139 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>140 %b = and <4 x i32> %a, %x141 ret <4 x i32> %b142}143 144define arm_aapcs_vfpcc <8 x i16> @and_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {145; CHECK-LABEL: and_v8i16_x:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vctp.16 r0148; CHECK-NEXT: vpst149; CHECK-NEXT: vandt q0, q0, q1150; CHECK-NEXT: bx lr151entry:152 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)153 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>154 %b = and <8 x i16> %a, %x155 ret <8 x i16> %b156}157 158define arm_aapcs_vfpcc <16 x i8> @and_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {159; CHECK-LABEL: and_v16i8_x:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: vctp.8 r0162; CHECK-NEXT: vpst163; CHECK-NEXT: vandt q0, q0, q1164; CHECK-NEXT: bx lr165entry:166 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)167 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>168 %b = and <16 x i8> %a, %x169 ret <16 x i8> %b170}171 172define arm_aapcs_vfpcc <4 x i32> @or_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {173; CHECK-LABEL: or_v4i32_x:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vctp.32 r0176; CHECK-NEXT: vpst177; CHECK-NEXT: vorrt q0, q0, q1178; CHECK-NEXT: bx lr179entry:180 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)181 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer182 %b = or <4 x i32> %a, %x183 ret <4 x i32> %b184}185 186define arm_aapcs_vfpcc <8 x i16> @or_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {187; CHECK-LABEL: or_v8i16_x:188; CHECK: @ %bb.0: @ %entry189; CHECK-NEXT: vctp.16 r0190; CHECK-NEXT: vpst191; CHECK-NEXT: vorrt q0, q0, q1192; CHECK-NEXT: bx lr193entry:194 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)195 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer196 %b = or <8 x i16> %a, %x197 ret <8 x i16> %b198}199 200define arm_aapcs_vfpcc <16 x i8> @or_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {201; CHECK-LABEL: or_v16i8_x:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vctp.8 r0204; CHECK-NEXT: vpst205; CHECK-NEXT: vorrt q0, q0, q1206; CHECK-NEXT: bx lr207entry:208 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)209 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer210 %b = or <16 x i8> %a, %x211 ret <16 x i8> %b212}213 214define arm_aapcs_vfpcc <4 x i32> @xor_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {215; CHECK-LABEL: xor_v4i32_x:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vctp.32 r0218; CHECK-NEXT: vpst219; CHECK-NEXT: veort q0, q0, q1220; CHECK-NEXT: bx lr221entry:222 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)223 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer224 %b = xor <4 x i32> %a, %x225 ret <4 x i32> %b226}227 228define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {229; CHECK-LABEL: xor_v8i16_x:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vctp.16 r0232; CHECK-NEXT: vpst233; CHECK-NEXT: veort q0, q0, q1234; CHECK-NEXT: bx lr235entry:236 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)237 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer238 %b = xor <8 x i16> %a, %x239 ret <8 x i16> %b240}241 242define arm_aapcs_vfpcc <16 x i8> @xor_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {243; CHECK-LABEL: xor_v16i8_x:244; CHECK: @ %bb.0: @ %entry245; CHECK-NEXT: vctp.8 r0246; CHECK-NEXT: vpst247; CHECK-NEXT: veort q0, q0, q1248; CHECK-NEXT: bx lr249entry:250 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)251 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer252 %b = xor <16 x i8> %a, %x253 ret <16 x i8> %b254}255 256define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {257; CHECK-LABEL: shl_v4i32_x:258; CHECK: @ %bb.0: @ %entry259; CHECK-NEXT: vctp.32 r0260; CHECK-NEXT: vpst261; CHECK-NEXT: vshlt.u32 q0, q0, q1262; CHECK-NEXT: bx lr263entry:264 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)265 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer266 %b = shl <4 x i32> %x, %a267 ret <4 x i32> %b268}269 270define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {271; CHECK-LABEL: shl_v8i16_x:272; CHECK: @ %bb.0: @ %entry273; CHECK-NEXT: vctp.16 r0274; CHECK-NEXT: vpst275; CHECK-NEXT: vshlt.u16 q0, q0, q1276; CHECK-NEXT: bx lr277entry:278 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)279 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer280 %b = shl <8 x i16> %x, %a281 ret <8 x i16> %b282}283 284define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {285; CHECK-LABEL: shl_v16i8_x:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vctp.8 r0288; CHECK-NEXT: vpst289; CHECK-NEXT: vshlt.u8 q0, q0, q1290; CHECK-NEXT: bx lr291entry:292 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)293 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer294 %b = shl <16 x i8> %x, %a295 ret <16 x i8> %b296}297 298define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {299; CHECK-LABEL: ashr_v4i32_x:300; CHECK: @ %bb.0: @ %entry301; CHECK-NEXT: vneg.s32 q1, q1302; CHECK-NEXT: vctp.32 r0303; CHECK-NEXT: vpst304; CHECK-NEXT: vshlt.s32 q0, q0, q1305; CHECK-NEXT: bx lr306entry:307 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)308 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer309 %b = ashr <4 x i32> %x, %a310 ret <4 x i32> %b311}312 313define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {314; CHECK-LABEL: ashr_v8i16_x:315; CHECK: @ %bb.0: @ %entry316; CHECK-NEXT: vneg.s16 q1, q1317; CHECK-NEXT: vctp.16 r0318; CHECK-NEXT: vpst319; CHECK-NEXT: vshlt.s16 q0, q0, q1320; CHECK-NEXT: bx lr321entry:322 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)323 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer324 %b = ashr <8 x i16> %x, %a325 ret <8 x i16> %b326}327 328define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {329; CHECK-LABEL: ashr_v16i8_x:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vneg.s8 q1, q1332; CHECK-NEXT: vctp.8 r0333; CHECK-NEXT: vpst334; CHECK-NEXT: vshlt.s8 q0, q0, q1335; CHECK-NEXT: bx lr336entry:337 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)338 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer339 %b = ashr <16 x i8> %x, %a340 ret <16 x i8> %b341}342 343define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {344; CHECK-LABEL: lshr_v4i32_x:345; CHECK: @ %bb.0: @ %entry346; CHECK-NEXT: vneg.s32 q1, q1347; CHECK-NEXT: vctp.32 r0348; CHECK-NEXT: vpst349; CHECK-NEXT: vshlt.u32 q0, q0, q1350; CHECK-NEXT: bx lr351entry:352 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)353 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> zeroinitializer354 %b = lshr <4 x i32> %x, %a355 ret <4 x i32> %b356}357 358define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {359; CHECK-LABEL: lshr_v8i16_x:360; CHECK: @ %bb.0: @ %entry361; CHECK-NEXT: vneg.s16 q1, q1362; CHECK-NEXT: vctp.16 r0363; CHECK-NEXT: vpst364; CHECK-NEXT: vshlt.u16 q0, q0, q1365; CHECK-NEXT: bx lr366entry:367 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)368 %a = select <8 x i1> %c, <8 x i16> %y, <8 x i16> zeroinitializer369 %b = lshr <8 x i16> %x, %a370 ret <8 x i16> %b371}372 373define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {374; CHECK-LABEL: lshr_v16i8_x:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: vneg.s8 q1, q1377; CHECK-NEXT: vctp.8 r0378; CHECK-NEXT: vpst379; CHECK-NEXT: vshlt.u8 q0, q0, q1380; CHECK-NEXT: bx lr381entry:382 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)383 %a = select <16 x i1> %c, <16 x i8> %y, <16 x i8> zeroinitializer384 %b = lshr <16 x i8> %x, %a385 ret <16 x i8> %b386}387 388define arm_aapcs_vfpcc <4 x i32> @andnot_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {389; CHECK-LABEL: andnot_v4i32_x:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vctp.32 r0392; CHECK-NEXT: vpst393; CHECK-NEXT: vbict q0, q0, q1394; CHECK-NEXT: bx lr395entry:396 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)397 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>398 %a = select <4 x i1> %c, <4 x i32> %y1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>399 %b = and <4 x i32> %a, %x400 ret <4 x i32> %b401}402 403define arm_aapcs_vfpcc <8 x i16> @andnot_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {404; CHECK-LABEL: andnot_v8i16_x:405; CHECK: @ %bb.0: @ %entry406; CHECK-NEXT: vctp.16 r0407; CHECK-NEXT: vpst408; CHECK-NEXT: vbict q0, q0, q1409; CHECK-NEXT: bx lr410entry:411 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)412 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>413 %a = select <8 x i1> %c, <8 x i16> %y1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>414 %b = and <8 x i16> %a, %x415 ret <8 x i16> %b416}417 418define arm_aapcs_vfpcc <16 x i8> @andnot_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {419; CHECK-LABEL: andnot_v16i8_x:420; CHECK: @ %bb.0: @ %entry421; CHECK-NEXT: vctp.8 r0422; CHECK-NEXT: vpst423; CHECK-NEXT: vbict q0, q0, q1424; CHECK-NEXT: bx lr425entry:426 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)427 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>428 %a = select <16 x i1> %c, <16 x i8> %y1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>429 %b = and <16 x i8> %a, %x430 ret <16 x i8> %b431}432 433define arm_aapcs_vfpcc <4 x i32> @ornot_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {434; CHECK-LABEL: ornot_v4i32_x:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: vctp.32 r0437; CHECK-NEXT: vpst438; CHECK-NEXT: vornt q0, q0, q1439; CHECK-NEXT: bx lr440entry:441 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)442 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>443 %a = select <4 x i1> %c, <4 x i32> %y1, <4 x i32> zeroinitializer444 %b = or <4 x i32> %a, %x445 ret <4 x i32> %b446}447 448define arm_aapcs_vfpcc <8 x i16> @ornot_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {449; CHECK-LABEL: ornot_v8i16_x:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: vctp.16 r0452; CHECK-NEXT: vpst453; CHECK-NEXT: vornt q0, q0, q1454; CHECK-NEXT: bx lr455entry:456 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)457 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>458 %a = select <8 x i1> %c, <8 x i16> %y1, <8 x i16> zeroinitializer459 %b = or <8 x i16> %a, %x460 ret <8 x i16> %b461}462 463define arm_aapcs_vfpcc <16 x i8> @ornot_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {464; CHECK-LABEL: ornot_v16i8_x:465; CHECK: @ %bb.0: @ %entry466; CHECK-NEXT: vctp.8 r0467; CHECK-NEXT: vpst468; CHECK-NEXT: vornt q0, q0, q1469; CHECK-NEXT: bx lr470entry:471 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)472 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>473 %a = select <16 x i1> %c, <16 x i8> %y1, <16 x i8> zeroinitializer474 %b = or <16 x i8> %a, %x475 ret <16 x i8> %b476}477 478define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {479; CHECK-LABEL: fadd_v4f32_x:480; CHECK: @ %bb.0: @ %entry481; CHECK-NEXT: vctp.32 r0482; CHECK-NEXT: vpst483; CHECK-NEXT: vaddt.f32 q0, q0, q1484; CHECK-NEXT: bx lr485entry:486 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)487 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>488 %b = fadd <4 x float> %a, %x489 ret <4 x float> %b490}491 492define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_x2(<4 x float> %x, <4 x float> %y, i32 %n) {493; CHECK-LABEL: fadd_v4f32_x2:494; CHECK: @ %bb.0: @ %entry495; CHECK-NEXT: vmov.i32 q2, #0x0496; CHECK-NEXT: vctp.32 r0497; CHECK-NEXT: vpst498; CHECK-NEXT: vmovt q2, q1499; CHECK-NEXT: vadd.f32 q0, q2, q0500; CHECK-NEXT: bx lr501entry:502 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)503 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>504 %b = fadd <4 x float> %a, %x505 ret <4 x float> %b506}507 508define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_x3(<4 x float> %x, <4 x float> %y, i32 %n) {509; CHECK-LABEL: fadd_v4f32_x3:510; CHECK: @ %bb.0: @ %entry511; CHECK-NEXT: vctp.32 r0512; CHECK-NEXT: vpst513; CHECK-NEXT: vaddt.f32 q0, q0, q1514; CHECK-NEXT: bx lr515entry:516 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)517 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>518 %b = fadd nsz <4 x float> %a, %x519 ret <4 x float> %b520}521 522define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {523; CHECK-LABEL: fadd_v8f16_x:524; CHECK: @ %bb.0: @ %entry525; CHECK-NEXT: vctp.16 r0526; CHECK-NEXT: vpst527; CHECK-NEXT: vaddt.f16 q0, q0, q1528; CHECK-NEXT: bx lr529entry:530 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)531 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>532 %b = fadd <8 x half> %a, %x533 ret <8 x half> %b534}535 536define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_x2(<8 x half> %x, <8 x half> %y, i32 %n) {537; CHECK-LABEL: fadd_v8f16_x2:538; CHECK: @ %bb.0: @ %entry539; CHECK-NEXT: vmov.i32 q2, #0x0540; CHECK-NEXT: vctp.16 r0541; CHECK-NEXT: vpst542; CHECK-NEXT: vmovt q2, q1543; CHECK-NEXT: vadd.f16 q0, q2, q0544; CHECK-NEXT: bx lr545entry:546 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)547 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> <half 0x0000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000>548 %b = fadd <8 x half> %a, %x549 ret <8 x half> %b550}551 552define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_x3(<8 x half> %x, <8 x half> %y, i32 %n) {553; CHECK-LABEL: fadd_v8f16_x3:554; CHECK: @ %bb.0: @ %entry555; CHECK-NEXT: vctp.16 r0556; CHECK-NEXT: vpst557; CHECK-NEXT: vaddt.f16 q0, q0, q1558; CHECK-NEXT: bx lr559entry:560 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)561 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> <half 0x0000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000, half 0x00000>562 %b = fadd nsz <8 x half> %a, %x563 ret <8 x half> %b564}565 566define arm_aapcs_vfpcc <4 x float> @fsub_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {567; CHECK-LABEL: fsub_v4f32_x:568; CHECK: @ %bb.0: @ %entry569; CHECK-NEXT: vctp.32 r0570; CHECK-NEXT: vpst571; CHECK-NEXT: vsubt.f32 q0, q0, q1572; CHECK-NEXT: bx lr573entry:574 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)575 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> zeroinitializer576 %b = fsub <4 x float> %x, %a577 ret <4 x float> %b578}579 580define arm_aapcs_vfpcc <8 x half> @fsub_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {581; CHECK-LABEL: fsub_v8f16_x:582; CHECK: @ %bb.0: @ %entry583; CHECK-NEXT: vctp.16 r0584; CHECK-NEXT: vpst585; CHECK-NEXT: vsubt.f16 q0, q0, q1586; CHECK-NEXT: bx lr587entry:588 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)589 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> zeroinitializer590 %b = fsub <8 x half> %x, %a591 ret <8 x half> %b592}593 594define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {595; CHECK-LABEL: fmul_v4f32_x:596; CHECK: @ %bb.0: @ %entry597; CHECK-NEXT: vctp.32 r0598; CHECK-NEXT: vpst599; CHECK-NEXT: vmult.f32 q0, q0, q1600; CHECK-NEXT: bx lr601entry:602 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)603 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>604 %b = fmul <4 x float> %a, %x605 ret <4 x float> %b606}607 608define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {609; CHECK-LABEL: fmul_v8f16_x:610; CHECK: @ %bb.0: @ %entry611; CHECK-NEXT: vctp.16 r0612; CHECK-NEXT: vpst613; CHECK-NEXT: vmult.f16 q0, q0, q1614; CHECK-NEXT: bx lr615entry:616 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)617 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>618 %b = fmul <8 x half> %a, %x619 ret <8 x half> %b620}621 622define arm_aapcs_vfpcc <4 x float> @fdiv_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {623; CHECK-LABEL: fdiv_v4f32_x:624; CHECK: @ %bb.0: @ %entry625; CHECK-NEXT: vdiv.f32 s7, s3, s7626; CHECK-NEXT: vctp.32 r0627; CHECK-NEXT: vdiv.f32 s6, s2, s6628; CHECK-NEXT: vdiv.f32 s5, s1, s5629; CHECK-NEXT: vdiv.f32 s4, s0, s4630; CHECK-NEXT: vpst631; CHECK-NEXT: vmovt q0, q1632; CHECK-NEXT: bx lr633entry:634 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)635 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>636 %b = fdiv <4 x float> %x, %a637 ret <4 x float> %b638}639 640define arm_aapcs_vfpcc <8 x half> @fdiv_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {641; CHECK-LABEL: fdiv_v8f16_x:642; CHECK: @ %bb.0: @ %entry643; CHECK-NEXT: vmovx.f16 s8, s4644; CHECK-NEXT: vmovx.f16 s10, s0645; CHECK-NEXT: vdiv.f16 s8, s10, s8646; CHECK-NEXT: vdiv.f16 s4, s0, s4647; CHECK-NEXT: vins.f16 s4, s8648; CHECK-NEXT: vmovx.f16 s8, s5649; CHECK-NEXT: vmovx.f16 s10, s1650; CHECK-NEXT: vdiv.f16 s5, s1, s5651; CHECK-NEXT: vdiv.f16 s8, s10, s8652; CHECK-NEXT: vmovx.f16 s10, s2653; CHECK-NEXT: vins.f16 s5, s8654; CHECK-NEXT: vmovx.f16 s8, s6655; CHECK-NEXT: vdiv.f16 s8, s10, s8656; CHECK-NEXT: vdiv.f16 s6, s2, s6657; CHECK-NEXT: vins.f16 s6, s8658; CHECK-NEXT: vmovx.f16 s8, s7659; CHECK-NEXT: vmovx.f16 s10, s3660; CHECK-NEXT: vdiv.f16 s7, s3, s7661; CHECK-NEXT: vdiv.f16 s8, s10, s8662; CHECK-NEXT: vctp.16 r0663; CHECK-NEXT: vins.f16 s7, s8664; CHECK-NEXT: vpst665; CHECK-NEXT: vmovt q0, q1666; CHECK-NEXT: bx lr667entry:668 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)669 %a = select <8 x i1> %c, <8 x half> %y, <8 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>670 %b = fdiv <8 x half> %x, %a671 ret <8 x half> %b672}673 674define arm_aapcs_vfpcc <4 x float> @fmai_v4f32_x(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {675; CHECK-LABEL: fmai_v4f32_x:676; CHECK: @ %bb.0: @ %entry677; CHECK-NEXT: vmov.i32 q3, #0x80000000678; CHECK-NEXT: vctp.32 r0679; CHECK-NEXT: vpst680; CHECK-NEXT: vmovt q3, q0681; CHECK-NEXT: vfma.f32 q3, q1, q2682; CHECK-NEXT: vmov q0, q3683; CHECK-NEXT: bx lr684entry:685 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)686 %a = select <4 x i1> %c, <4 x float> %x, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>687 %b = call <4 x float> @llvm.fma.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %a)688 ret <4 x float> %b689}690 691define arm_aapcs_vfpcc <8 x half> @fmai_v8f16_x(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {692; CHECK-LABEL: fmai_v8f16_x:693; CHECK: @ %bb.0: @ %entry694; CHECK-NEXT: vmov.i16 q3, #0x8000695; CHECK-NEXT: vctp.16 r0696; CHECK-NEXT: vpst697; CHECK-NEXT: vmovt q3, q0698; CHECK-NEXT: vfma.f16 q3, q1, q2699; CHECK-NEXT: vmov q0, q3700; CHECK-NEXT: bx lr701entry:702 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)703 %a = select <8 x i1> %c, <8 x half> %x, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>704 %b = call <8 x half> @llvm.fma.v8f16(<8 x half> %y, <8 x half> %z, <8 x half> %a)705 ret <8 x half> %b706}707 708define arm_aapcs_vfpcc <4 x float> @fma_v4f32_x(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {709; CHECK-LABEL: fma_v4f32_x:710; CHECK: @ %bb.0: @ %entry711; CHECK-NEXT: vctp.32 r0712; CHECK-NEXT: vpst713; CHECK-NEXT: vfmat.f32 q0, q1, q2714; CHECK-NEXT: bx lr715entry:716 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)717 %m = fmul fast <4 x float> %y, %z718 %a = select <4 x i1> %c, <4 x float> %m, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>719 %b = fadd fast <4 x float> %a, %x720 ret <4 x float> %b721}722 723define arm_aapcs_vfpcc <8 x half> @fma_v8f16_x(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {724; CHECK-LABEL: fma_v8f16_x:725; CHECK: @ %bb.0: @ %entry726; CHECK-NEXT: vctp.16 r0727; CHECK-NEXT: vpst728; CHECK-NEXT: vfmat.f16 q0, q1, q2729; CHECK-NEXT: bx lr730entry:731 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)732 %m = fmul fast <8 x half> %y, %z733 %a = select <8 x i1> %c, <8 x half> %m, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>734 %b = fadd fast <8 x half> %a, %x735 ret <8 x half> %b736}737 738define arm_aapcs_vfpcc <4 x i32> @icmp_slt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {739; CHECK-LABEL: icmp_slt_v4i32_x:740; CHECK: @ %bb.0: @ %entry741; CHECK-NEXT: vctp.32 r0742; CHECK-NEXT: vpst743; CHECK-NEXT: vmint.s32 q0, q0, q1744; CHECK-NEXT: bx lr745entry:746 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)747 %a = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> %y)748 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x749 ret <4 x i32> %b750}751 752define arm_aapcs_vfpcc <8 x i16> @icmp_slt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {753; CHECK-LABEL: icmp_slt_v8i16_x:754; CHECK: @ %bb.0: @ %entry755; CHECK-NEXT: vctp.16 r0756; CHECK-NEXT: vpst757; CHECK-NEXT: vmint.s16 q0, q0, q1758; CHECK-NEXT: bx lr759entry:760 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)761 %a = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %x, <8 x i16> %y)762 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x763 ret <8 x i16> %b764}765 766define arm_aapcs_vfpcc <16 x i8> @icmp_slt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {767; CHECK-LABEL: icmp_slt_v16i8_x:768; CHECK: @ %bb.0: @ %entry769; CHECK-NEXT: vctp.8 r0770; CHECK-NEXT: vpst771; CHECK-NEXT: vmint.s8 q0, q0, q1772; CHECK-NEXT: bx lr773entry:774 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)775 %a = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %x, <16 x i8> %y)776 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x777 ret <16 x i8> %b778}779 780define arm_aapcs_vfpcc <4 x i32> @icmp_sgt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {781; CHECK-LABEL: icmp_sgt_v4i32_x:782; CHECK: @ %bb.0: @ %entry783; CHECK-NEXT: vctp.32 r0784; CHECK-NEXT: vpst785; CHECK-NEXT: vmaxt.s32 q0, q0, q1786; CHECK-NEXT: bx lr787entry:788 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)789 %a = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> %y)790 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x791 ret <4 x i32> %b792}793 794define arm_aapcs_vfpcc <8 x i16> @icmp_sgt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {795; CHECK-LABEL: icmp_sgt_v8i16_x:796; CHECK: @ %bb.0: @ %entry797; CHECK-NEXT: vctp.16 r0798; CHECK-NEXT: vpst799; CHECK-NEXT: vmaxt.s16 q0, q0, q1800; CHECK-NEXT: bx lr801entry:802 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)803 %a = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %x, <8 x i16> %y)804 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x805 ret <8 x i16> %b806}807 808define arm_aapcs_vfpcc <16 x i8> @icmp_sgt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {809; CHECK-LABEL: icmp_sgt_v16i8_x:810; CHECK: @ %bb.0: @ %entry811; CHECK-NEXT: vctp.8 r0812; CHECK-NEXT: vpst813; CHECK-NEXT: vmaxt.s8 q0, q0, q1814; CHECK-NEXT: bx lr815entry:816 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)817 %a = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %x, <16 x i8> %y)818 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x819 ret <16 x i8> %b820}821 822define arm_aapcs_vfpcc <4 x i32> @icmp_ult_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {823; CHECK-LABEL: icmp_ult_v4i32_x:824; CHECK: @ %bb.0: @ %entry825; CHECK-NEXT: vctp.32 r0826; CHECK-NEXT: vpst827; CHECK-NEXT: vmint.u32 q0, q0, q1828; CHECK-NEXT: bx lr829entry:830 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)831 %a = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> %y)832 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x833 ret <4 x i32> %b834}835 836define arm_aapcs_vfpcc <8 x i16> @icmp_ult_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {837; CHECK-LABEL: icmp_ult_v8i16_x:838; CHECK: @ %bb.0: @ %entry839; CHECK-NEXT: vctp.16 r0840; CHECK-NEXT: vpst841; CHECK-NEXT: vmint.u16 q0, q0, q1842; CHECK-NEXT: bx lr843entry:844 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)845 %a = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %x, <8 x i16> %y)846 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x847 ret <8 x i16> %b848}849 850define arm_aapcs_vfpcc <16 x i8> @icmp_ult_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {851; CHECK-LABEL: icmp_ult_v16i8_x:852; CHECK: @ %bb.0: @ %entry853; CHECK-NEXT: vctp.8 r0854; CHECK-NEXT: vpst855; CHECK-NEXT: vmint.u8 q0, q0, q1856; CHECK-NEXT: bx lr857entry:858 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)859 %a = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %x, <16 x i8> %y)860 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x861 ret <16 x i8> %b862}863 864define arm_aapcs_vfpcc <4 x i32> @icmp_ugt_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {865; CHECK-LABEL: icmp_ugt_v4i32_x:866; CHECK: @ %bb.0: @ %entry867; CHECK-NEXT: vctp.32 r0868; CHECK-NEXT: vpst869; CHECK-NEXT: vmaxt.u32 q0, q0, q1870; CHECK-NEXT: bx lr871entry:872 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)873 %a = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> %y)874 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x875 ret <4 x i32> %b876}877 878define arm_aapcs_vfpcc <8 x i16> @icmp_ugt_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {879; CHECK-LABEL: icmp_ugt_v8i16_x:880; CHECK: @ %bb.0: @ %entry881; CHECK-NEXT: vctp.16 r0882; CHECK-NEXT: vpst883; CHECK-NEXT: vmaxt.u16 q0, q0, q1884; CHECK-NEXT: bx lr885entry:886 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)887 %a = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %x, <8 x i16> %y)888 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x889 ret <8 x i16> %b890}891 892define arm_aapcs_vfpcc <16 x i8> @icmp_ugt_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {893; CHECK-LABEL: icmp_ugt_v16i8_x:894; CHECK: @ %bb.0: @ %entry895; CHECK-NEXT: vctp.8 r0896; CHECK-NEXT: vpst897; CHECK-NEXT: vmaxt.u8 q0, q0, q1898; CHECK-NEXT: bx lr899entry:900 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)901 %a = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %x, <16 x i8> %y)902 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x903 ret <16 x i8> %b904}905 906define arm_aapcs_vfpcc <4 x float> @fcmp_fast_olt_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {907; CHECK-LABEL: fcmp_fast_olt_v4f32_x:908; CHECK: @ %bb.0: @ %entry909; CHECK-NEXT: vctp.32 r0910; CHECK-NEXT: vpst911; CHECK-NEXT: vminnmt.f32 q0, q0, q1912; CHECK-NEXT: bx lr913entry:914 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)915 %a1 = fcmp fast olt <4 x float> %x, %y916 %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y917 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x918 ret <4 x float> %b919}920 921define arm_aapcs_vfpcc <8 x half> @fcmp_fast_olt_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {922; CHECK-LABEL: fcmp_fast_olt_v8f16_x:923; CHECK: @ %bb.0: @ %entry924; CHECK-NEXT: vctp.16 r0925; CHECK-NEXT: vpst926; CHECK-NEXT: vminnmt.f16 q0, q0, q1927; CHECK-NEXT: bx lr928entry:929 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)930 %a1 = fcmp fast olt <8 x half> %x, %y931 %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y932 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x933 ret <8 x half> %b934}935 936define arm_aapcs_vfpcc <4 x float> @fcmp_fast_ogt_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {937; CHECK-LABEL: fcmp_fast_ogt_v4f32_x:938; CHECK: @ %bb.0: @ %entry939; CHECK-NEXT: vctp.32 r0940; CHECK-NEXT: vpst941; CHECK-NEXT: vmaxnmt.f32 q0, q0, q1942; CHECK-NEXT: bx lr943entry:944 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)945 %a1 = fcmp fast ogt <4 x float> %x, %y946 %a = select <4 x i1> %a1, <4 x float> %x, <4 x float> %y947 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %x948 ret <4 x float> %b949}950 951define arm_aapcs_vfpcc <8 x half> @fcmp_fast_ogt_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {952; CHECK-LABEL: fcmp_fast_ogt_v8f16_x:953; CHECK: @ %bb.0: @ %entry954; CHECK-NEXT: vctp.16 r0955; CHECK-NEXT: vpst956; CHECK-NEXT: vmaxnmt.f16 q0, q0, q1957; CHECK-NEXT: bx lr958entry:959 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)960 %a1 = fcmp fast ogt <8 x half> %x, %y961 %a = select <8 x i1> %a1, <8 x half> %x, <8 x half> %y962 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %x963 ret <8 x half> %b964}965 966define arm_aapcs_vfpcc <4 x i32> @sadd_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {967; CHECK-LABEL: sadd_sat_v4i32_x:968; CHECK: @ %bb.0: @ %entry969; CHECK-NEXT: vctp.32 r0970; CHECK-NEXT: vpst971; CHECK-NEXT: vqaddt.s32 q0, q0, q1972; CHECK-NEXT: bx lr973entry:974 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)975 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)976 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x977 ret <4 x i32> %b978}979 980define arm_aapcs_vfpcc <8 x i16> @sadd_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {981; CHECK-LABEL: sadd_sat_v8i16_x:982; CHECK: @ %bb.0: @ %entry983; CHECK-NEXT: vctp.16 r0984; CHECK-NEXT: vpst985; CHECK-NEXT: vqaddt.s16 q0, q0, q1986; CHECK-NEXT: bx lr987entry:988 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)989 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)990 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x991 ret <8 x i16> %b992}993 994define arm_aapcs_vfpcc <16 x i8> @sadd_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {995; CHECK-LABEL: sadd_sat_v16i8_x:996; CHECK: @ %bb.0: @ %entry997; CHECK-NEXT: vctp.8 r0998; CHECK-NEXT: vpst999; CHECK-NEXT: vqaddt.s8 q0, q0, q11000; CHECK-NEXT: bx lr1001entry:1002 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1003 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1004 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1005 ret <16 x i8> %b1006}1007 1008define arm_aapcs_vfpcc <4 x i32> @uadd_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {1009; CHECK-LABEL: uadd_sat_v4i32_x:1010; CHECK: @ %bb.0: @ %entry1011; CHECK-NEXT: vctp.32 r01012; CHECK-NEXT: vpst1013; CHECK-NEXT: vqaddt.u32 q0, q0, q11014; CHECK-NEXT: bx lr1015entry:1016 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1017 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)1018 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1019 ret <4 x i32> %b1020}1021 1022define arm_aapcs_vfpcc <8 x i16> @uadd_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {1023; CHECK-LABEL: uadd_sat_v8i16_x:1024; CHECK: @ %bb.0: @ %entry1025; CHECK-NEXT: vctp.16 r01026; CHECK-NEXT: vpst1027; CHECK-NEXT: vqaddt.u16 q0, q0, q11028; CHECK-NEXT: bx lr1029entry:1030 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1031 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)1032 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1033 ret <8 x i16> %b1034}1035 1036define arm_aapcs_vfpcc <16 x i8> @uadd_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {1037; CHECK-LABEL: uadd_sat_v16i8_x:1038; CHECK: @ %bb.0: @ %entry1039; CHECK-NEXT: vctp.8 r01040; CHECK-NEXT: vpst1041; CHECK-NEXT: vqaddt.u8 q0, q0, q11042; CHECK-NEXT: bx lr1043entry:1044 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1045 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1046 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1047 ret <16 x i8> %b1048}1049 1050define arm_aapcs_vfpcc <4 x i32> @ssub_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {1051; CHECK-LABEL: ssub_sat_v4i32_x:1052; CHECK: @ %bb.0: @ %entry1053; CHECK-NEXT: vctp.32 r01054; CHECK-NEXT: vpst1055; CHECK-NEXT: vqsubt.s32 q0, q0, q11056; CHECK-NEXT: bx lr1057entry:1058 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1059 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)1060 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1061 ret <4 x i32> %b1062}1063 1064define arm_aapcs_vfpcc <8 x i16> @ssub_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {1065; CHECK-LABEL: ssub_sat_v8i16_x:1066; CHECK: @ %bb.0: @ %entry1067; CHECK-NEXT: vctp.16 r01068; CHECK-NEXT: vpst1069; CHECK-NEXT: vqsubt.s16 q0, q0, q11070; CHECK-NEXT: bx lr1071entry:1072 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1073 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)1074 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1075 ret <8 x i16> %b1076}1077 1078define arm_aapcs_vfpcc <16 x i8> @ssub_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {1079; CHECK-LABEL: ssub_sat_v16i8_x:1080; CHECK: @ %bb.0: @ %entry1081; CHECK-NEXT: vctp.8 r01082; CHECK-NEXT: vpst1083; CHECK-NEXT: vqsubt.s8 q0, q0, q11084; CHECK-NEXT: bx lr1085entry:1086 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1087 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1088 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1089 ret <16 x i8> %b1090}1091 1092define arm_aapcs_vfpcc <4 x i32> @usub_sat_v4i32_x(<4 x i32> %x, <4 x i32> %y, i32 %n) {1093; CHECK-LABEL: usub_sat_v4i32_x:1094; CHECK: @ %bb.0: @ %entry1095; CHECK-NEXT: vctp.32 r01096; CHECK-NEXT: vpst1097; CHECK-NEXT: vqsubt.u32 q0, q0, q11098; CHECK-NEXT: bx lr1099entry:1100 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1101 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)1102 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1103 ret <4 x i32> %b1104}1105 1106define arm_aapcs_vfpcc <8 x i16> @usub_sat_v8i16_x(<8 x i16> %x, <8 x i16> %y, i32 %n) {1107; CHECK-LABEL: usub_sat_v8i16_x:1108; CHECK: @ %bb.0: @ %entry1109; CHECK-NEXT: vctp.16 r01110; CHECK-NEXT: vpst1111; CHECK-NEXT: vqsubt.u16 q0, q0, q11112; CHECK-NEXT: bx lr1113entry:1114 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1115 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)1116 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1117 ret <8 x i16> %b1118}1119 1120define arm_aapcs_vfpcc <16 x i8> @usub_sat_v16i8_x(<16 x i8> %x, <16 x i8> %y, i32 %n) {1121; CHECK-LABEL: usub_sat_v16i8_x:1122; CHECK: @ %bb.0: @ %entry1123; CHECK-NEXT: vctp.8 r01124; CHECK-NEXT: vpst1125; CHECK-NEXT: vqsubt.u8 q0, q0, q11126; CHECK-NEXT: bx lr1127entry:1128 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1129 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)1130 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1131 ret <16 x i8> %b1132}1133 1134define arm_aapcs_vfpcc <4 x i32> @addqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1135; CHECK-LABEL: addqr_v4i32_x:1136; CHECK: @ %bb.0: @ %entry1137; CHECK-NEXT: vctp.32 r11138; CHECK-NEXT: vpst1139; CHECK-NEXT: vaddt.i32 q0, q0, r01140; CHECK-NEXT: bx lr1141entry:1142 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1143 %i = insertelement <4 x i32> undef, i32 %y, i64 01144 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1145 %a = select <4 x i1> %c, <4 x i32> %ys, <4 x i32> zeroinitializer1146 %b = add <4 x i32> %a, %x1147 ret <4 x i32> %b1148}1149 1150define arm_aapcs_vfpcc <8 x i16> @addqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1151; CHECK-LABEL: addqr_v8i16_x:1152; CHECK: @ %bb.0: @ %entry1153; CHECK-NEXT: vctp.16 r11154; CHECK-NEXT: vpst1155; CHECK-NEXT: vaddt.i16 q0, q0, r01156; CHECK-NEXT: bx lr1157entry:1158 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1159 %i = insertelement <8 x i16> undef, i16 %y, i64 01160 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1161 %a = select <8 x i1> %c, <8 x i16> %ys, <8 x i16> zeroinitializer1162 %b = add <8 x i16> %a, %x1163 ret <8 x i16> %b1164}1165 1166define arm_aapcs_vfpcc <16 x i8> @addqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1167; CHECK-LABEL: addqr_v16i8_x:1168; CHECK: @ %bb.0: @ %entry1169; CHECK-NEXT: vctp.8 r11170; CHECK-NEXT: vpst1171; CHECK-NEXT: vaddt.i8 q0, q0, r01172; CHECK-NEXT: bx lr1173entry:1174 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1175 %i = insertelement <16 x i8> undef, i8 %y, i64 01176 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1177 %a = select <16 x i1> %c, <16 x i8> %ys, <16 x i8> zeroinitializer1178 %b = add <16 x i8> %a, %x1179 ret <16 x i8> %b1180}1181 1182define arm_aapcs_vfpcc <4 x i32> @subqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1183; CHECK-LABEL: subqr_v4i32_x:1184; CHECK: @ %bb.0: @ %entry1185; CHECK-NEXT: vctp.32 r11186; CHECK-NEXT: vpst1187; CHECK-NEXT: vsubt.i32 q0, q0, r01188; CHECK-NEXT: bx lr1189entry:1190 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1191 %i = insertelement <4 x i32> undef, i32 %y, i64 01192 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1193 %a = select <4 x i1> %c, <4 x i32> %ys, <4 x i32> zeroinitializer1194 %b = sub <4 x i32> %x, %a1195 ret <4 x i32> %b1196}1197 1198define arm_aapcs_vfpcc <8 x i16> @subqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1199; CHECK-LABEL: subqr_v8i16_x:1200; CHECK: @ %bb.0: @ %entry1201; CHECK-NEXT: vctp.16 r11202; CHECK-NEXT: vpst1203; CHECK-NEXT: vsubt.i16 q0, q0, r01204; CHECK-NEXT: bx lr1205entry:1206 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1207 %i = insertelement <8 x i16> undef, i16 %y, i64 01208 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1209 %a = select <8 x i1> %c, <8 x i16> %ys, <8 x i16> zeroinitializer1210 %b = sub <8 x i16> %x, %a1211 ret <8 x i16> %b1212}1213 1214define arm_aapcs_vfpcc <16 x i8> @subqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1215; CHECK-LABEL: subqr_v16i8_x:1216; CHECK: @ %bb.0: @ %entry1217; CHECK-NEXT: vctp.8 r11218; CHECK-NEXT: vpst1219; CHECK-NEXT: vsubt.i8 q0, q0, r01220; CHECK-NEXT: bx lr1221entry:1222 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1223 %i = insertelement <16 x i8> undef, i8 %y, i64 01224 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1225 %a = select <16 x i1> %c, <16 x i8> %ys, <16 x i8> zeroinitializer1226 %b = sub <16 x i8> %x, %a1227 ret <16 x i8> %b1228}1229 1230define arm_aapcs_vfpcc <4 x i32> @mulqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1231; CHECK-LABEL: mulqr_v4i32_x:1232; CHECK: @ %bb.0: @ %entry1233; CHECK-NEXT: vctp.32 r11234; CHECK-NEXT: vpst1235; CHECK-NEXT: vmult.i32 q0, q0, r01236; CHECK-NEXT: bx lr1237entry:1238 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1239 %i = insertelement <4 x i32> undef, i32 %y, i64 01240 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1241 %a = select <4 x i1> %c, <4 x i32> %ys, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1242 %b = mul <4 x i32> %a, %x1243 ret <4 x i32> %b1244}1245 1246define arm_aapcs_vfpcc <8 x i16> @mulqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1247; CHECK-LABEL: mulqr_v8i16_x:1248; CHECK: @ %bb.0: @ %entry1249; CHECK-NEXT: vctp.16 r11250; CHECK-NEXT: vpst1251; CHECK-NEXT: vmult.i16 q0, q0, r01252; CHECK-NEXT: bx lr1253entry:1254 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1255 %i = insertelement <8 x i16> undef, i16 %y, i64 01256 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1257 %a = select <8 x i1> %c, <8 x i16> %ys, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1258 %b = mul <8 x i16> %a, %x1259 ret <8 x i16> %b1260}1261 1262define arm_aapcs_vfpcc <16 x i8> @mulqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1263; CHECK-LABEL: mulqr_v16i8_x:1264; CHECK: @ %bb.0: @ %entry1265; CHECK-NEXT: vctp.8 r11266; CHECK-NEXT: vpst1267; CHECK-NEXT: vmult.i8 q0, q0, r01268; CHECK-NEXT: bx lr1269entry:1270 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1271 %i = insertelement <16 x i8> undef, i8 %y, i64 01272 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1273 %a = select <16 x i1> %c, <16 x i8> %ys, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1274 %b = mul <16 x i8> %a, %x1275 ret <16 x i8> %b1276}1277 1278define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1279; CHECK-LABEL: faddqr_v4f32_x:1280; CHECK: @ %bb.0: @ %entry1281; CHECK-NEXT: vmov r1, s41282; CHECK-NEXT: vctp.32 r01283; CHECK-NEXT: vpst1284; CHECK-NEXT: vaddt.f32 q0, q0, r11285; CHECK-NEXT: bx lr1286entry:1287 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1288 %i = insertelement <4 x float> undef, float %y, i64 01289 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1290 %a = select <4 x i1> %c, <4 x float> %ys, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>1291 %b = fadd <4 x float> %a, %x1292 ret <4 x float> %b1293}1294 1295define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1296; CHECK-LABEL: faddqr_v8f16_x:1297; CHECK: @ %bb.0: @ %entry1298; CHECK-NEXT: vmov.f16 r1, s41299; CHECK-NEXT: vctp.16 r01300; CHECK-NEXT: vpst1301; CHECK-NEXT: vaddt.f16 q0, q0, r11302; CHECK-NEXT: bx lr1303entry:1304 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1305 %i = insertelement <8 x half> undef, half %y, i64 01306 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1307 %a = select <8 x i1> %c, <8 x half> %ys, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>1308 %b = fadd <8 x half> %a, %x1309 ret <8 x half> %b1310}1311 1312define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1313; CHECK-LABEL: fsubqr_v4f32_x:1314; CHECK: @ %bb.0: @ %entry1315; CHECK-NEXT: vmov r1, s41316; CHECK-NEXT: vctp.32 r01317; CHECK-NEXT: vpst1318; CHECK-NEXT: vsubt.f32 q0, q0, r11319; CHECK-NEXT: bx lr1320entry:1321 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1322 %i = insertelement <4 x float> undef, float %y, i64 01323 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1324 %a = select <4 x i1> %c, <4 x float> %ys, <4 x float> zeroinitializer1325 %b = fsub <4 x float> %x, %a1326 ret <4 x float> %b1327}1328 1329define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1330; CHECK-LABEL: fsubqr_v8f16_x:1331; CHECK: @ %bb.0: @ %entry1332; CHECK-NEXT: vmov.f16 r1, s41333; CHECK-NEXT: vctp.16 r01334; CHECK-NEXT: vpst1335; CHECK-NEXT: vsubt.f16 q0, q0, r11336; CHECK-NEXT: bx lr1337entry:1338 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1339 %i = insertelement <8 x half> undef, half %y, i64 01340 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1341 %a = select <8 x i1> %c, <8 x half> %ys, <8 x half> zeroinitializer1342 %b = fsub <8 x half> %x, %a1343 ret <8 x half> %b1344}1345 1346define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {1347; CHECK-LABEL: fmulqr_v4f32_x:1348; CHECK: @ %bb.0: @ %entry1349; CHECK-NEXT: vmov r1, s41350; CHECK-NEXT: vctp.32 r01351; CHECK-NEXT: vpst1352; CHECK-NEXT: vmult.f32 q0, q0, r11353; CHECK-NEXT: bx lr1354entry:1355 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1356 %i = insertelement <4 x float> undef, float %y, i64 01357 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1358 %a = select <4 x i1> %c, <4 x float> %ys, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>1359 %b = fmul <4 x float> %a, %x1360 ret <4 x float> %b1361}1362 1363define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_x(<8 x half> %x, half %y, i32 %n) {1364; CHECK-LABEL: fmulqr_v8f16_x:1365; CHECK: @ %bb.0: @ %entry1366; CHECK-NEXT: vmov.f16 r1, s41367; CHECK-NEXT: vctp.16 r01368; CHECK-NEXT: vpst1369; CHECK-NEXT: vmult.f16 q0, q0, r11370; CHECK-NEXT: bx lr1371entry:1372 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1373 %i = insertelement <8 x half> undef, half %y, i64 01374 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1375 %a = select <8 x i1> %c, <8 x half> %ys, <8 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>1376 %b = fmul <8 x half> %a, %x1377 ret <8 x half> %b1378}1379 1380define arm_aapcs_vfpcc <4 x i32> @sadd_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1381; CHECK-LABEL: sadd_satqr_v4i32_x:1382; CHECK: @ %bb.0: @ %entry1383; CHECK-NEXT: vctp.32 r11384; CHECK-NEXT: vpst1385; CHECK-NEXT: vqaddt.s32 q0, q0, r01386; CHECK-NEXT: bx lr1387entry:1388 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1389 %i = insertelement <4 x i32> undef, i32 %y, i64 01390 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1391 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1392 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1393 ret <4 x i32> %b1394}1395 1396define arm_aapcs_vfpcc <8 x i16> @sadd_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1397; CHECK-LABEL: sadd_satqr_v8i16_x:1398; CHECK: @ %bb.0: @ %entry1399; CHECK-NEXT: vctp.16 r11400; CHECK-NEXT: vpst1401; CHECK-NEXT: vqaddt.s16 q0, q0, r01402; CHECK-NEXT: bx lr1403entry:1404 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1405 %i = insertelement <8 x i16> undef, i16 %y, i64 01406 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1407 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1408 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1409 ret <8 x i16> %b1410}1411 1412define arm_aapcs_vfpcc <16 x i8> @sadd_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1413; CHECK-LABEL: sadd_satqr_v16i8_x:1414; CHECK: @ %bb.0: @ %entry1415; CHECK-NEXT: vctp.8 r11416; CHECK-NEXT: vpst1417; CHECK-NEXT: vqaddt.s8 q0, q0, r01418; CHECK-NEXT: bx lr1419entry:1420 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1421 %i = insertelement <16 x i8> undef, i8 %y, i64 01422 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1423 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1424 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1425 ret <16 x i8> %b1426}1427 1428define arm_aapcs_vfpcc <4 x i32> @uadd_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1429; CHECK-LABEL: uadd_satqr_v4i32_x:1430; CHECK: @ %bb.0: @ %entry1431; CHECK-NEXT: vctp.32 r11432; CHECK-NEXT: vpst1433; CHECK-NEXT: vqaddt.u32 q0, q0, r01434; CHECK-NEXT: bx lr1435entry:1436 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1437 %i = insertelement <4 x i32> undef, i32 %y, i64 01438 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1439 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1440 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1441 ret <4 x i32> %b1442}1443 1444define arm_aapcs_vfpcc <8 x i16> @uadd_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1445; CHECK-LABEL: uadd_satqr_v8i16_x:1446; CHECK: @ %bb.0: @ %entry1447; CHECK-NEXT: vctp.16 r11448; CHECK-NEXT: vpst1449; CHECK-NEXT: vqaddt.u16 q0, q0, r01450; CHECK-NEXT: bx lr1451entry:1452 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1453 %i = insertelement <8 x i16> undef, i16 %y, i64 01454 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1455 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1456 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1457 ret <8 x i16> %b1458}1459 1460define arm_aapcs_vfpcc <16 x i8> @uadd_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1461; CHECK-LABEL: uadd_satqr_v16i8_x:1462; CHECK: @ %bb.0: @ %entry1463; CHECK-NEXT: vctp.8 r11464; CHECK-NEXT: vpst1465; CHECK-NEXT: vqaddt.u8 q0, q0, r01466; CHECK-NEXT: bx lr1467entry:1468 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1469 %i = insertelement <16 x i8> undef, i8 %y, i64 01470 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1471 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1472 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1473 ret <16 x i8> %b1474}1475 1476define arm_aapcs_vfpcc <4 x i32> @ssub_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1477; CHECK-LABEL: ssub_satqr_v4i32_x:1478; CHECK: @ %bb.0: @ %entry1479; CHECK-NEXT: vctp.32 r11480; CHECK-NEXT: vpst1481; CHECK-NEXT: vqsubt.s32 q0, q0, r01482; CHECK-NEXT: bx lr1483entry:1484 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1485 %i = insertelement <4 x i32> undef, i32 %y, i64 01486 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1487 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1488 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1489 ret <4 x i32> %b1490}1491 1492define arm_aapcs_vfpcc <8 x i16> @ssub_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1493; CHECK-LABEL: ssub_satqr_v8i16_x:1494; CHECK: @ %bb.0: @ %entry1495; CHECK-NEXT: vctp.16 r11496; CHECK-NEXT: vpst1497; CHECK-NEXT: vqsubt.s16 q0, q0, r01498; CHECK-NEXT: bx lr1499entry:1500 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1501 %i = insertelement <8 x i16> undef, i16 %y, i64 01502 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1503 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1504 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1505 ret <8 x i16> %b1506}1507 1508define arm_aapcs_vfpcc <16 x i8> @ssub_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1509; CHECK-LABEL: ssub_satqr_v16i8_x:1510; CHECK: @ %bb.0: @ %entry1511; CHECK-NEXT: vctp.8 r11512; CHECK-NEXT: vpst1513; CHECK-NEXT: vqsubt.s8 q0, q0, r01514; CHECK-NEXT: bx lr1515entry:1516 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1517 %i = insertelement <16 x i8> undef, i8 %y, i64 01518 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1519 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1520 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1521 ret <16 x i8> %b1522}1523 1524define arm_aapcs_vfpcc <4 x i32> @usub_satqr_v4i32_x(<4 x i32> %x, i32 %y, i32 %n) {1525; CHECK-LABEL: usub_satqr_v4i32_x:1526; CHECK: @ %bb.0: @ %entry1527; CHECK-NEXT: vctp.32 r11528; CHECK-NEXT: vpst1529; CHECK-NEXT: vqsubt.u32 q0, q0, r01530; CHECK-NEXT: bx lr1531entry:1532 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1533 %i = insertelement <4 x i32> undef, i32 %y, i64 01534 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer1535 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)1536 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %x1537 ret <4 x i32> %b1538}1539 1540define arm_aapcs_vfpcc <8 x i16> @usub_satqr_v8i16_x(<8 x i16> %x, i16 %y, i32 %n) {1541; CHECK-LABEL: usub_satqr_v8i16_x:1542; CHECK: @ %bb.0: @ %entry1543; CHECK-NEXT: vctp.16 r11544; CHECK-NEXT: vpst1545; CHECK-NEXT: vqsubt.u16 q0, q0, r01546; CHECK-NEXT: bx lr1547entry:1548 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1549 %i = insertelement <8 x i16> undef, i16 %y, i64 01550 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer1551 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)1552 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %x1553 ret <8 x i16> %b1554}1555 1556define arm_aapcs_vfpcc <16 x i8> @usub_satqr_v16i8_x(<16 x i8> %x, i8 %y, i32 %n) {1557; CHECK-LABEL: usub_satqr_v16i8_x:1558; CHECK: @ %bb.0: @ %entry1559; CHECK-NEXT: vctp.8 r11560; CHECK-NEXT: vpst1561; CHECK-NEXT: vqsubt.u8 q0, q0, r01562; CHECK-NEXT: bx lr1563entry:1564 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1565 %i = insertelement <16 x i8> undef, i8 %y, i64 01566 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer1567 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)1568 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %x1569 ret <16 x i8> %b1570}1571 1572define arm_aapcs_vfpcc <4 x i32> @add_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1573; CHECK-LABEL: add_v4i32_y:1574; CHECK: @ %bb.0: @ %entry1575; CHECK-NEXT: vctp.32 r01576; CHECK-NEXT: vpst1577; CHECK-NEXT: vaddt.i32 q1, q1, q01578; CHECK-NEXT: vmov q0, q11579; CHECK-NEXT: bx lr1580entry:1581 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1582 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer1583 %b = add <4 x i32> %a, %y1584 ret <4 x i32> %b1585}1586 1587define arm_aapcs_vfpcc <8 x i16> @add_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1588; CHECK-LABEL: add_v8i16_y:1589; CHECK: @ %bb.0: @ %entry1590; CHECK-NEXT: vctp.16 r01591; CHECK-NEXT: vpst1592; CHECK-NEXT: vaddt.i16 q1, q1, q01593; CHECK-NEXT: vmov q0, q11594; CHECK-NEXT: bx lr1595entry:1596 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1597 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer1598 %b = add <8 x i16> %a, %y1599 ret <8 x i16> %b1600}1601 1602define arm_aapcs_vfpcc <16 x i8> @add_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1603; CHECK-LABEL: add_v16i8_y:1604; CHECK: @ %bb.0: @ %entry1605; CHECK-NEXT: vctp.8 r01606; CHECK-NEXT: vpst1607; CHECK-NEXT: vaddt.i8 q1, q1, q01608; CHECK-NEXT: vmov q0, q11609; CHECK-NEXT: bx lr1610entry:1611 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1612 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer1613 %b = add <16 x i8> %a, %y1614 ret <16 x i8> %b1615}1616 1617define arm_aapcs_vfpcc <4 x i32> @sub_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1618; CHECK-LABEL: sub_v4i32_y:1619; CHECK: @ %bb.0: @ %entry1620; CHECK-NEXT: vctp.32 r01621; CHECK-NEXT: vpst1622; CHECK-NEXT: vsubt.i32 q1, q0, q11623; CHECK-NEXT: vmov q0, q11624; CHECK-NEXT: bx lr1625entry:1626 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1627 %a = sub <4 x i32> %x, %y1628 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1629 ret <4 x i32> %b1630}1631 1632define arm_aapcs_vfpcc <8 x i16> @sub_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1633; CHECK-LABEL: sub_v8i16_y:1634; CHECK: @ %bb.0: @ %entry1635; CHECK-NEXT: vctp.16 r01636; CHECK-NEXT: vpst1637; CHECK-NEXT: vsubt.i16 q1, q0, q11638; CHECK-NEXT: vmov q0, q11639; CHECK-NEXT: bx lr1640entry:1641 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1642 %a = sub <8 x i16> %x, %y1643 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1644 ret <8 x i16> %b1645}1646 1647define arm_aapcs_vfpcc <16 x i8> @sub_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1648; CHECK-LABEL: sub_v16i8_y:1649; CHECK: @ %bb.0: @ %entry1650; CHECK-NEXT: vctp.8 r01651; CHECK-NEXT: vpst1652; CHECK-NEXT: vsubt.i8 q1, q0, q11653; CHECK-NEXT: vmov q0, q11654; CHECK-NEXT: bx lr1655entry:1656 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1657 %a = sub <16 x i8> %x, %y1658 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1659 ret <16 x i8> %b1660}1661 1662define arm_aapcs_vfpcc <4 x i32> @mul_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1663; CHECK-LABEL: mul_v4i32_y:1664; CHECK: @ %bb.0: @ %entry1665; CHECK-NEXT: vctp.32 r01666; CHECK-NEXT: vpst1667; CHECK-NEXT: vmult.i32 q1, q1, q01668; CHECK-NEXT: vmov q0, q11669; CHECK-NEXT: bx lr1670entry:1671 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1672 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 1, i32 1, i32 1, i32 1>1673 %b = mul <4 x i32> %a, %y1674 ret <4 x i32> %b1675}1676 1677define arm_aapcs_vfpcc <8 x i16> @mul_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1678; CHECK-LABEL: mul_v8i16_y:1679; CHECK: @ %bb.0: @ %entry1680; CHECK-NEXT: vctp.16 r01681; CHECK-NEXT: vpst1682; CHECK-NEXT: vmult.i16 q1, q1, q01683; CHECK-NEXT: vmov q0, q11684; CHECK-NEXT: bx lr1685entry:1686 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1687 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1688 %b = mul <8 x i16> %a, %y1689 ret <8 x i16> %b1690}1691 1692define arm_aapcs_vfpcc <16 x i8> @mul_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1693; CHECK-LABEL: mul_v16i8_y:1694; CHECK: @ %bb.0: @ %entry1695; CHECK-NEXT: vctp.8 r01696; CHECK-NEXT: vpst1697; CHECK-NEXT: vmult.i8 q1, q1, q01698; CHECK-NEXT: vmov q0, q11699; CHECK-NEXT: bx lr1700entry:1701 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1702 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1703 %b = mul <16 x i8> %a, %y1704 ret <16 x i8> %b1705}1706 1707define arm_aapcs_vfpcc <4 x i32> @and_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1708; CHECK-LABEL: and_v4i32_y:1709; CHECK: @ %bb.0: @ %entry1710; CHECK-NEXT: vctp.32 r01711; CHECK-NEXT: vpst1712; CHECK-NEXT: vandt q1, q1, q01713; CHECK-NEXT: vmov q0, q11714; CHECK-NEXT: bx lr1715entry:1716 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1717 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>1718 %b = and <4 x i32> %a, %y1719 ret <4 x i32> %b1720}1721 1722define arm_aapcs_vfpcc <8 x i16> @and_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1723; CHECK-LABEL: and_v8i16_y:1724; CHECK: @ %bb.0: @ %entry1725; CHECK-NEXT: vctp.16 r01726; CHECK-NEXT: vpst1727; CHECK-NEXT: vandt q1, q1, q01728; CHECK-NEXT: vmov q0, q11729; CHECK-NEXT: bx lr1730entry:1731 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1732 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1733 %b = and <8 x i16> %a, %y1734 ret <8 x i16> %b1735}1736 1737define arm_aapcs_vfpcc <16 x i8> @and_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1738; CHECK-LABEL: and_v16i8_y:1739; CHECK: @ %bb.0: @ %entry1740; CHECK-NEXT: vctp.8 r01741; CHECK-NEXT: vpst1742; CHECK-NEXT: vandt q1, q1, q01743; CHECK-NEXT: vmov q0, q11744; CHECK-NEXT: bx lr1745entry:1746 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1747 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1748 %b = and <16 x i8> %a, %y1749 ret <16 x i8> %b1750}1751 1752define arm_aapcs_vfpcc <4 x i32> @or_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1753; CHECK-LABEL: or_v4i32_y:1754; CHECK: @ %bb.0: @ %entry1755; CHECK-NEXT: vctp.32 r01756; CHECK-NEXT: vpst1757; CHECK-NEXT: vorrt q1, q1, q01758; CHECK-NEXT: vmov q0, q11759; CHECK-NEXT: bx lr1760entry:1761 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1762 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer1763 %b = or <4 x i32> %a, %y1764 ret <4 x i32> %b1765}1766 1767define arm_aapcs_vfpcc <8 x i16> @or_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1768; CHECK-LABEL: or_v8i16_y:1769; CHECK: @ %bb.0: @ %entry1770; CHECK-NEXT: vctp.16 r01771; CHECK-NEXT: vpst1772; CHECK-NEXT: vorrt q1, q1, q01773; CHECK-NEXT: vmov q0, q11774; CHECK-NEXT: bx lr1775entry:1776 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1777 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer1778 %b = or <8 x i16> %a, %y1779 ret <8 x i16> %b1780}1781 1782define arm_aapcs_vfpcc <16 x i8> @or_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1783; CHECK-LABEL: or_v16i8_y:1784; CHECK: @ %bb.0: @ %entry1785; CHECK-NEXT: vctp.8 r01786; CHECK-NEXT: vpst1787; CHECK-NEXT: vorrt q1, q1, q01788; CHECK-NEXT: vmov q0, q11789; CHECK-NEXT: bx lr1790entry:1791 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1792 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer1793 %b = or <16 x i8> %a, %y1794 ret <16 x i8> %b1795}1796 1797define arm_aapcs_vfpcc <4 x i32> @xor_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1798; CHECK-LABEL: xor_v4i32_y:1799; CHECK: @ %bb.0: @ %entry1800; CHECK-NEXT: vctp.32 r01801; CHECK-NEXT: vpst1802; CHECK-NEXT: veort q1, q1, q01803; CHECK-NEXT: vmov q0, q11804; CHECK-NEXT: bx lr1805entry:1806 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1807 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer1808 %b = xor <4 x i32> %a, %y1809 ret <4 x i32> %b1810}1811 1812define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1813; CHECK-LABEL: xor_v8i16_y:1814; CHECK: @ %bb.0: @ %entry1815; CHECK-NEXT: vctp.16 r01816; CHECK-NEXT: vpst1817; CHECK-NEXT: veort q1, q1, q01818; CHECK-NEXT: vmov q0, q11819; CHECK-NEXT: bx lr1820entry:1821 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1822 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer1823 %b = xor <8 x i16> %a, %y1824 ret <8 x i16> %b1825}1826 1827define arm_aapcs_vfpcc <16 x i8> @xor_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1828; CHECK-LABEL: xor_v16i8_y:1829; CHECK: @ %bb.0: @ %entry1830; CHECK-NEXT: vctp.8 r01831; CHECK-NEXT: vpst1832; CHECK-NEXT: veort q1, q1, q01833; CHECK-NEXT: vmov q0, q11834; CHECK-NEXT: bx lr1835entry:1836 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1837 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer1838 %b = xor <16 x i8> %a, %y1839 ret <16 x i8> %b1840}1841 1842define arm_aapcs_vfpcc <4 x i32> @shl_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1843; CHECK-LABEL: shl_v4i32_y:1844; CHECK: @ %bb.0: @ %entry1845; CHECK-NEXT: vctp.32 r01846; CHECK-NEXT: vpst1847; CHECK-NEXT: vshlt.u32 q1, q0, q11848; CHECK-NEXT: vmov q0, q11849; CHECK-NEXT: bx lr1850entry:1851 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1852 %a = shl <4 x i32> %x, %y1853 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1854 ret <4 x i32> %b1855}1856 1857define arm_aapcs_vfpcc <8 x i16> @shl_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1858; CHECK-LABEL: shl_v8i16_y:1859; CHECK: @ %bb.0: @ %entry1860; CHECK-NEXT: vctp.16 r01861; CHECK-NEXT: vpst1862; CHECK-NEXT: vshlt.u16 q1, q0, q11863; CHECK-NEXT: vmov q0, q11864; CHECK-NEXT: bx lr1865entry:1866 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1867 %a = shl <8 x i16> %x, %y1868 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1869 ret <8 x i16> %b1870}1871 1872define arm_aapcs_vfpcc <16 x i8> @shl_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1873; CHECK-LABEL: shl_v16i8_y:1874; CHECK: @ %bb.0: @ %entry1875; CHECK-NEXT: vctp.8 r01876; CHECK-NEXT: vpst1877; CHECK-NEXT: vshlt.u8 q1, q0, q11878; CHECK-NEXT: vmov q0, q11879; CHECK-NEXT: bx lr1880entry:1881 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1882 %a = shl <16 x i8> %x, %y1883 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1884 ret <16 x i8> %b1885}1886 1887define arm_aapcs_vfpcc <4 x i32> @ashr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1888; CHECK-LABEL: ashr_v4i32_y:1889; CHECK: @ %bb.0: @ %entry1890; CHECK-NEXT: vneg.s32 q2, q11891; CHECK-NEXT: vctp.32 r01892; CHECK-NEXT: vpst1893; CHECK-NEXT: vshlt.s32 q1, q0, q21894; CHECK-NEXT: vmov q0, q11895; CHECK-NEXT: bx lr1896entry:1897 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1898 %a = ashr <4 x i32> %x, %y1899 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1900 ret <4 x i32> %b1901}1902 1903define arm_aapcs_vfpcc <8 x i16> @ashr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1904; CHECK-LABEL: ashr_v8i16_y:1905; CHECK: @ %bb.0: @ %entry1906; CHECK-NEXT: vneg.s16 q2, q11907; CHECK-NEXT: vctp.16 r01908; CHECK-NEXT: vpst1909; CHECK-NEXT: vshlt.s16 q1, q0, q21910; CHECK-NEXT: vmov q0, q11911; CHECK-NEXT: bx lr1912entry:1913 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1914 %a = ashr <8 x i16> %x, %y1915 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1916 ret <8 x i16> %b1917}1918 1919define arm_aapcs_vfpcc <16 x i8> @ashr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1920; CHECK-LABEL: ashr_v16i8_y:1921; CHECK: @ %bb.0: @ %entry1922; CHECK-NEXT: vneg.s8 q2, q11923; CHECK-NEXT: vctp.8 r01924; CHECK-NEXT: vpst1925; CHECK-NEXT: vshlt.s8 q1, q0, q21926; CHECK-NEXT: vmov q0, q11927; CHECK-NEXT: bx lr1928entry:1929 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1930 %a = ashr <16 x i8> %x, %y1931 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1932 ret <16 x i8> %b1933}1934 1935define arm_aapcs_vfpcc <4 x i32> @lshr_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1936; CHECK-LABEL: lshr_v4i32_y:1937; CHECK: @ %bb.0: @ %entry1938; CHECK-NEXT: vneg.s32 q2, q11939; CHECK-NEXT: vctp.32 r01940; CHECK-NEXT: vpst1941; CHECK-NEXT: vshlt.u32 q1, q0, q21942; CHECK-NEXT: vmov q0, q11943; CHECK-NEXT: bx lr1944entry:1945 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1946 %a = lshr <4 x i32> %x, %y1947 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1948 ret <4 x i32> %b1949}1950 1951define arm_aapcs_vfpcc <8 x i16> @lshr_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {1952; CHECK-LABEL: lshr_v8i16_y:1953; CHECK: @ %bb.0: @ %entry1954; CHECK-NEXT: vneg.s16 q2, q11955; CHECK-NEXT: vctp.16 r01956; CHECK-NEXT: vpst1957; CHECK-NEXT: vshlt.u16 q1, q0, q21958; CHECK-NEXT: vmov q0, q11959; CHECK-NEXT: bx lr1960entry:1961 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)1962 %a = lshr <8 x i16> %x, %y1963 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y1964 ret <8 x i16> %b1965}1966 1967define arm_aapcs_vfpcc <16 x i8> @lshr_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {1968; CHECK-LABEL: lshr_v16i8_y:1969; CHECK: @ %bb.0: @ %entry1970; CHECK-NEXT: vneg.s8 q2, q11971; CHECK-NEXT: vctp.8 r01972; CHECK-NEXT: vpst1973; CHECK-NEXT: vshlt.u8 q1, q0, q21974; CHECK-NEXT: vmov q0, q11975; CHECK-NEXT: bx lr1976entry:1977 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)1978 %a = lshr <16 x i8> %x, %y1979 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y1980 ret <16 x i8> %b1981}1982 1983define arm_aapcs_vfpcc <4 x i32> @andnot_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {1984; CHECK-LABEL: andnot_v4i32_y:1985; CHECK: @ %bb.0: @ %entry1986; CHECK-NEXT: vctp.32 r01987; CHECK-NEXT: vpst1988; CHECK-NEXT: vbict q1, q0, q11989; CHECK-NEXT: vmov q0, q11990; CHECK-NEXT: bx lr1991entry:1992 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)1993 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>1994 %a = and <4 x i32> %y1, %x1995 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y1996 ret <4 x i32> %b1997}1998 1999define arm_aapcs_vfpcc <8 x i16> @andnot_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2000; CHECK-LABEL: andnot_v8i16_y:2001; CHECK: @ %bb.0: @ %entry2002; CHECK-NEXT: vctp.16 r02003; CHECK-NEXT: vpst2004; CHECK-NEXT: vbict q1, q0, q12005; CHECK-NEXT: vmov q0, q12006; CHECK-NEXT: bx lr2007entry:2008 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2009 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>2010 %a = and <8 x i16> %y1, %x2011 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2012 ret <8 x i16> %b2013}2014 2015define arm_aapcs_vfpcc <16 x i8> @andnot_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2016; CHECK-LABEL: andnot_v16i8_y:2017; CHECK: @ %bb.0: @ %entry2018; CHECK-NEXT: vctp.8 r02019; CHECK-NEXT: vpst2020; CHECK-NEXT: vbict q1, q0, q12021; CHECK-NEXT: vmov q0, q12022; CHECK-NEXT: bx lr2023entry:2024 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2025 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>2026 %a = and <16 x i8> %y1, %x2027 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2028 ret <16 x i8> %b2029}2030 2031define arm_aapcs_vfpcc <4 x i32> @ornot_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2032; CHECK-LABEL: ornot_v4i32_y:2033; CHECK: @ %bb.0: @ %entry2034; CHECK-NEXT: vctp.32 r02035; CHECK-NEXT: vpst2036; CHECK-NEXT: vornt q1, q0, q12037; CHECK-NEXT: vmov q0, q12038; CHECK-NEXT: bx lr2039entry:2040 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2041 %y1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>2042 %a = or <4 x i32> %y1, %x2043 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2044 ret <4 x i32> %b2045}2046 2047define arm_aapcs_vfpcc <8 x i16> @ornot_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2048; CHECK-LABEL: ornot_v8i16_y:2049; CHECK: @ %bb.0: @ %entry2050; CHECK-NEXT: vctp.16 r02051; CHECK-NEXT: vpst2052; CHECK-NEXT: vornt q1, q0, q12053; CHECK-NEXT: vmov q0, q12054; CHECK-NEXT: bx lr2055entry:2056 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2057 %y1 = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>2058 %a = or <8 x i16> %y1, %x2059 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2060 ret <8 x i16> %b2061}2062 2063define arm_aapcs_vfpcc <16 x i8> @ornot_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2064; CHECK-LABEL: ornot_v16i8_y:2065; CHECK: @ %bb.0: @ %entry2066; CHECK-NEXT: vctp.8 r02067; CHECK-NEXT: vpst2068; CHECK-NEXT: vornt q1, q0, q12069; CHECK-NEXT: vmov q0, q12070; CHECK-NEXT: bx lr2071entry:2072 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2073 %y1 = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>2074 %a = or <16 x i8> %y1, %x2075 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2076 ret <16 x i8> %b2077}2078 2079define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2080; CHECK-LABEL: fadd_v4f32_y:2081; CHECK: @ %bb.0: @ %entry2082; CHECK-NEXT: vctp.32 r02083; CHECK-NEXT: vpst2084; CHECK-NEXT: vaddt.f32 q1, q1, q02085; CHECK-NEXT: vmov q0, q12086; CHECK-NEXT: bx lr2087entry:2088 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2089 %a = select <4 x i1> %c, <4 x float> %x, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>2090 %b = fadd <4 x float> %a, %y2091 ret <4 x float> %b2092}2093 2094define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2095; CHECK-LABEL: fadd_v8f16_y:2096; CHECK: @ %bb.0: @ %entry2097; CHECK-NEXT: vctp.16 r02098; CHECK-NEXT: vpst2099; CHECK-NEXT: vaddt.f16 q1, q1, q02100; CHECK-NEXT: vmov q0, q12101; CHECK-NEXT: bx lr2102entry:2103 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2104 %a = select <8 x i1> %c, <8 x half> %x, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>2105 %b = fadd <8 x half> %a, %y2106 ret <8 x half> %b2107}2108 2109define arm_aapcs_vfpcc <4 x float> @fsub_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2110; CHECK-LABEL: fsub_v4f32_y:2111; CHECK: @ %bb.0: @ %entry2112; CHECK-NEXT: vctp.32 r02113; CHECK-NEXT: vpst2114; CHECK-NEXT: vsubt.f32 q1, q0, q12115; CHECK-NEXT: vmov q0, q12116; CHECK-NEXT: bx lr2117entry:2118 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2119 %a = fsub <4 x float> %x, %y2120 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2121 ret <4 x float> %b2122}2123 2124define arm_aapcs_vfpcc <8 x half> @fsub_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2125; CHECK-LABEL: fsub_v8f16_y:2126; CHECK: @ %bb.0: @ %entry2127; CHECK-NEXT: vctp.16 r02128; CHECK-NEXT: vpst2129; CHECK-NEXT: vsubt.f16 q1, q0, q12130; CHECK-NEXT: vmov q0, q12131; CHECK-NEXT: bx lr2132entry:2133 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2134 %a = fsub <8 x half> %x, %y2135 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2136 ret <8 x half> %b2137}2138 2139define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2140; CHECK-LABEL: fmul_v4f32_y:2141; CHECK: @ %bb.0: @ %entry2142; CHECK-NEXT: vctp.32 r02143; CHECK-NEXT: vpst2144; CHECK-NEXT: vmult.f32 q1, q1, q02145; CHECK-NEXT: vmov q0, q12146; CHECK-NEXT: bx lr2147entry:2148 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2149 %a = select <4 x i1> %c, <4 x float> %x, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>2150 %b = fmul <4 x float> %a, %y2151 ret <4 x float> %b2152}2153 2154define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2155; CHECK-LABEL: fmul_v8f16_y:2156; CHECK: @ %bb.0: @ %entry2157; CHECK-NEXT: vctp.16 r02158; CHECK-NEXT: vpst2159; CHECK-NEXT: vmult.f16 q1, q1, q02160; CHECK-NEXT: vmov q0, q12161; CHECK-NEXT: bx lr2162entry:2163 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2164 %a = select <8 x i1> %c, <8 x half> %x, <8 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>2165 %b = fmul <8 x half> %a, %y2166 ret <8 x half> %b2167}2168 2169define arm_aapcs_vfpcc <4 x float> @fdiv_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2170; CHECK-LABEL: fdiv_v4f32_y:2171; CHECK: @ %bb.0: @ %entry2172; CHECK-NEXT: vdiv.f32 s3, s3, s72173; CHECK-NEXT: vctp.32 r02174; CHECK-NEXT: vdiv.f32 s2, s2, s62175; CHECK-NEXT: vdiv.f32 s1, s1, s52176; CHECK-NEXT: vdiv.f32 s0, s0, s42177; CHECK-NEXT: vpst2178; CHECK-NEXT: vmovt q1, q02179; CHECK-NEXT: vmov q0, q12180; CHECK-NEXT: bx lr2181entry:2182 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2183 %a = fdiv <4 x float> %x, %y2184 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2185 ret <4 x float> %b2186}2187 2188define arm_aapcs_vfpcc <8 x half> @fdiv_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2189; CHECK-LABEL: fdiv_v8f16_y:2190; CHECK: @ %bb.0: @ %entry2191; CHECK-NEXT: vmovx.f16 s10, s02192; CHECK-NEXT: vmovx.f16 s8, s42193; CHECK-NEXT: vdiv.f16 s8, s10, s82194; CHECK-NEXT: vdiv.f16 s0, s0, s42195; CHECK-NEXT: vins.f16 s0, s82196; CHECK-NEXT: vmovx.f16 s10, s12197; CHECK-NEXT: vmovx.f16 s8, s52198; CHECK-NEXT: vdiv.f16 s1, s1, s52199; CHECK-NEXT: vdiv.f16 s8, s10, s82200; CHECK-NEXT: vmovx.f16 s10, s22201; CHECK-NEXT: vins.f16 s1, s82202; CHECK-NEXT: vmovx.f16 s8, s62203; CHECK-NEXT: vdiv.f16 s8, s10, s82204; CHECK-NEXT: vdiv.f16 s2, s2, s62205; CHECK-NEXT: vins.f16 s2, s82206; CHECK-NEXT: vmovx.f16 s10, s32207; CHECK-NEXT: vmovx.f16 s8, s72208; CHECK-NEXT: vdiv.f16 s3, s3, s72209; CHECK-NEXT: vdiv.f16 s8, s10, s82210; CHECK-NEXT: vctp.16 r02211; CHECK-NEXT: vins.f16 s3, s82212; CHECK-NEXT: vpst2213; CHECK-NEXT: vmovt q1, q02214; CHECK-NEXT: vmov q0, q12215; CHECK-NEXT: bx lr2216entry:2217 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2218 %a = fdiv <8 x half> %x, %y2219 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2220 ret <8 x half> %b2221}2222 2223define arm_aapcs_vfpcc <4 x float> @fmai_v4f32_y(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {2224; CHECK-LABEL: fmai_v4f32_y:2225; CHECK: @ %bb.0: @ %entry2226; CHECK-NEXT: vfma.f32 q0, q1, q22227; CHECK-NEXT: vctp.32 r02228; CHECK-NEXT: vpst2229; CHECK-NEXT: vmovt q1, q02230; CHECK-NEXT: vmov q0, q12231; CHECK-NEXT: bx lr2232entry:2233 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2234 %a = call <4 x float> @llvm.fma.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %x)2235 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2236 ret <4 x float> %b2237}2238 2239define arm_aapcs_vfpcc <8 x half> @fmai_v8f16_y(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {2240; CHECK-LABEL: fmai_v8f16_y:2241; CHECK: @ %bb.0: @ %entry2242; CHECK-NEXT: vfma.f16 q0, q1, q22243; CHECK-NEXT: vctp.16 r02244; CHECK-NEXT: vpst2245; CHECK-NEXT: vmovt q1, q02246; CHECK-NEXT: vmov q0, q12247; CHECK-NEXT: bx lr2248entry:2249 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2250 %a = call <8 x half> @llvm.fma.v8f16(<8 x half> %y, <8 x half> %z, <8 x half> %x)2251 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2252 ret <8 x half> %b2253}2254 2255define arm_aapcs_vfpcc <4 x float> @fma_v4f32_y(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {2256; CHECK-LABEL: fma_v4f32_y:2257; CHECK: @ %bb.0: @ %entry2258; CHECK-NEXT: vfma.f32 q0, q1, q22259; CHECK-NEXT: vctp.32 r02260; CHECK-NEXT: vpst2261; CHECK-NEXT: vmovt q1, q02262; CHECK-NEXT: vmov q0, q12263; CHECK-NEXT: bx lr2264entry:2265 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2266 %m = fmul fast <4 x float> %y, %z2267 %a = fadd fast <4 x float> %m, %x2268 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %y2269 ret <4 x float> %b2270}2271 2272define arm_aapcs_vfpcc <8 x half> @fma_v8f16_y(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {2273; CHECK-LABEL: fma_v8f16_y:2274; CHECK: @ %bb.0: @ %entry2275; CHECK-NEXT: vfma.f16 q0, q1, q22276; CHECK-NEXT: vctp.16 r02277; CHECK-NEXT: vpst2278; CHECK-NEXT: vmovt q1, q02279; CHECK-NEXT: vmov q0, q12280; CHECK-NEXT: bx lr2281entry:2282 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2283 %m = fmul fast <8 x half> %y, %z2284 %a = fadd fast <8 x half> %m, %x2285 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %y2286 ret <8 x half> %b2287}2288 2289define arm_aapcs_vfpcc <4 x i32> @icmp_slt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2290; CHECK-LABEL: icmp_slt_v4i32_y:2291; CHECK: @ %bb.0: @ %entry2292; CHECK-NEXT: vctp.32 r02293; CHECK-NEXT: vpst2294; CHECK-NEXT: vmint.s32 q1, q0, q12295; CHECK-NEXT: vmov q0, q12296; CHECK-NEXT: bx lr2297entry:2298 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2299 %a = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> %y)2300 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2301 ret <4 x i32> %b2302}2303 2304define arm_aapcs_vfpcc <8 x i16> @icmp_slt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2305; CHECK-LABEL: icmp_slt_v8i16_y:2306; CHECK: @ %bb.0: @ %entry2307; CHECK-NEXT: vctp.16 r02308; CHECK-NEXT: vpst2309; CHECK-NEXT: vmint.s16 q1, q0, q12310; CHECK-NEXT: vmov q0, q12311; CHECK-NEXT: bx lr2312entry:2313 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2314 %a = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %x, <8 x i16> %y)2315 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2316 ret <8 x i16> %b2317}2318 2319define arm_aapcs_vfpcc <16 x i8> @icmp_slt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2320; CHECK-LABEL: icmp_slt_v16i8_y:2321; CHECK: @ %bb.0: @ %entry2322; CHECK-NEXT: vctp.8 r02323; CHECK-NEXT: vpst2324; CHECK-NEXT: vmint.s8 q1, q0, q12325; CHECK-NEXT: vmov q0, q12326; CHECK-NEXT: bx lr2327entry:2328 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2329 %a = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %x, <16 x i8> %y)2330 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2331 ret <16 x i8> %b2332}2333 2334define arm_aapcs_vfpcc <4 x i32> @icmp_sgt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2335; CHECK-LABEL: icmp_sgt_v4i32_y:2336; CHECK: @ %bb.0: @ %entry2337; CHECK-NEXT: vctp.32 r02338; CHECK-NEXT: vpst2339; CHECK-NEXT: vmaxt.s32 q1, q0, q12340; CHECK-NEXT: vmov q0, q12341; CHECK-NEXT: bx lr2342entry:2343 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2344 %a = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> %y)2345 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2346 ret <4 x i32> %b2347}2348 2349define arm_aapcs_vfpcc <8 x i16> @icmp_sgt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2350; CHECK-LABEL: icmp_sgt_v8i16_y:2351; CHECK: @ %bb.0: @ %entry2352; CHECK-NEXT: vctp.16 r02353; CHECK-NEXT: vpst2354; CHECK-NEXT: vmaxt.s16 q1, q0, q12355; CHECK-NEXT: vmov q0, q12356; CHECK-NEXT: bx lr2357entry:2358 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2359 %a = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %x, <8 x i16> %y)2360 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2361 ret <8 x i16> %b2362}2363 2364define arm_aapcs_vfpcc <16 x i8> @icmp_sgt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2365; CHECK-LABEL: icmp_sgt_v16i8_y:2366; CHECK: @ %bb.0: @ %entry2367; CHECK-NEXT: vctp.8 r02368; CHECK-NEXT: vpst2369; CHECK-NEXT: vmaxt.s8 q1, q0, q12370; CHECK-NEXT: vmov q0, q12371; CHECK-NEXT: bx lr2372entry:2373 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2374 %a = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %x, <16 x i8> %y)2375 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2376 ret <16 x i8> %b2377}2378 2379define arm_aapcs_vfpcc <4 x i32> @icmp_ult_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2380; CHECK-LABEL: icmp_ult_v4i32_y:2381; CHECK: @ %bb.0: @ %entry2382; CHECK-NEXT: vctp.32 r02383; CHECK-NEXT: vpst2384; CHECK-NEXT: vmint.u32 q1, q0, q12385; CHECK-NEXT: vmov q0, q12386; CHECK-NEXT: bx lr2387entry:2388 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2389 %a = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> %y)2390 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2391 ret <4 x i32> %b2392}2393 2394define arm_aapcs_vfpcc <8 x i16> @icmp_ult_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2395; CHECK-LABEL: icmp_ult_v8i16_y:2396; CHECK: @ %bb.0: @ %entry2397; CHECK-NEXT: vctp.16 r02398; CHECK-NEXT: vpst2399; CHECK-NEXT: vmint.u16 q1, q0, q12400; CHECK-NEXT: vmov q0, q12401; CHECK-NEXT: bx lr2402entry:2403 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2404 %a = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %x, <8 x i16> %y)2405 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2406 ret <8 x i16> %b2407}2408 2409define arm_aapcs_vfpcc <16 x i8> @icmp_ult_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2410; CHECK-LABEL: icmp_ult_v16i8_y:2411; CHECK: @ %bb.0: @ %entry2412; CHECK-NEXT: vctp.8 r02413; CHECK-NEXT: vpst2414; CHECK-NEXT: vmint.u8 q1, q0, q12415; CHECK-NEXT: vmov q0, q12416; CHECK-NEXT: bx lr2417entry:2418 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2419 %a = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %x, <16 x i8> %y)2420 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2421 ret <16 x i8> %b2422}2423 2424define arm_aapcs_vfpcc <4 x i32> @icmp_ugt_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2425; CHECK-LABEL: icmp_ugt_v4i32_y:2426; CHECK: @ %bb.0: @ %entry2427; CHECK-NEXT: vctp.32 r02428; CHECK-NEXT: vpst2429; CHECK-NEXT: vmaxt.u32 q1, q0, q12430; CHECK-NEXT: vmov q0, q12431; CHECK-NEXT: bx lr2432entry:2433 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2434 %a = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> %y)2435 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2436 ret <4 x i32> %b2437}2438 2439define arm_aapcs_vfpcc <8 x i16> @icmp_ugt_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2440; CHECK-LABEL: icmp_ugt_v8i16_y:2441; CHECK: @ %bb.0: @ %entry2442; CHECK-NEXT: vctp.16 r02443; CHECK-NEXT: vpst2444; CHECK-NEXT: vmaxt.u16 q1, q0, q12445; CHECK-NEXT: vmov q0, q12446; CHECK-NEXT: bx lr2447entry:2448 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2449 %a = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %x, <8 x i16> %y)2450 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2451 ret <8 x i16> %b2452}2453 2454define arm_aapcs_vfpcc <16 x i8> @icmp_ugt_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2455; CHECK-LABEL: icmp_ugt_v16i8_y:2456; CHECK: @ %bb.0: @ %entry2457; CHECK-NEXT: vctp.8 r02458; CHECK-NEXT: vpst2459; CHECK-NEXT: vmaxt.u8 q1, q0, q12460; CHECK-NEXT: vmov q0, q12461; CHECK-NEXT: bx lr2462entry:2463 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2464 %a = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %x, <16 x i8> %y)2465 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2466 ret <16 x i8> %b2467}2468 2469define arm_aapcs_vfpcc <4 x float> @fcmp_fast_olt_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2470; CHECK-LABEL: fcmp_fast_olt_v4f32_y:2471; CHECK: @ %bb.0: @ %entry2472; CHECK-NEXT: vctp.32 r02473; CHECK-NEXT: vpstt2474; CHECK-NEXT: vcmpt.f32 gt, q1, q02475; CHECK-NEXT: vmovt q1, q02476; CHECK-NEXT: vmov q0, q12477; CHECK-NEXT: bx lr2478entry:2479 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2480 %a1 = fcmp fast olt <4 x float> %x, %y2481 %0 = and <4 x i1> %c, %a12482 %b = select <4 x i1> %0, <4 x float> %x, <4 x float> %y2483 ret <4 x float> %b2484}2485 2486define arm_aapcs_vfpcc <8 x half> @fcmp_fast_olt_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2487; CHECK-LABEL: fcmp_fast_olt_v8f16_y:2488; CHECK: @ %bb.0: @ %entry2489; CHECK-NEXT: vctp.16 r02490; CHECK-NEXT: vpstt2491; CHECK-NEXT: vcmpt.f16 gt, q1, q02492; CHECK-NEXT: vmovt q1, q02493; CHECK-NEXT: vmov q0, q12494; CHECK-NEXT: bx lr2495entry:2496 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2497 %a1 = fcmp fast olt <8 x half> %x, %y2498 %0 = and <8 x i1> %c, %a12499 %b = select <8 x i1> %0, <8 x half> %x, <8 x half> %y2500 ret <8 x half> %b2501}2502 2503define arm_aapcs_vfpcc <4 x float> @fcmp_fast_ogt_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {2504; CHECK-LABEL: fcmp_fast_ogt_v4f32_y:2505; CHECK: @ %bb.0: @ %entry2506; CHECK-NEXT: vctp.32 r02507; CHECK-NEXT: vpstt2508; CHECK-NEXT: vcmpt.f32 gt, q0, q12509; CHECK-NEXT: vmovt q1, q02510; CHECK-NEXT: vmov q0, q12511; CHECK-NEXT: bx lr2512entry:2513 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2514 %a1 = fcmp fast ogt <4 x float> %x, %y2515 %0 = and <4 x i1> %c, %a12516 %b = select <4 x i1> %0, <4 x float> %x, <4 x float> %y2517 ret <4 x float> %b2518}2519 2520define arm_aapcs_vfpcc <8 x half> @fcmp_fast_ogt_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {2521; CHECK-LABEL: fcmp_fast_ogt_v8f16_y:2522; CHECK: @ %bb.0: @ %entry2523; CHECK-NEXT: vctp.16 r02524; CHECK-NEXT: vpstt2525; CHECK-NEXT: vcmpt.f16 gt, q0, q12526; CHECK-NEXT: vmovt q1, q02527; CHECK-NEXT: vmov q0, q12528; CHECK-NEXT: bx lr2529entry:2530 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2531 %a1 = fcmp fast ogt <8 x half> %x, %y2532 %0 = and <8 x i1> %c, %a12533 %b = select <8 x i1> %0, <8 x half> %x, <8 x half> %y2534 ret <8 x half> %b2535}2536 2537define arm_aapcs_vfpcc <4 x i32> @sadd_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2538; CHECK-LABEL: sadd_sat_v4i32_y:2539; CHECK: @ %bb.0: @ %entry2540; CHECK-NEXT: vctp.32 r02541; CHECK-NEXT: vpst2542; CHECK-NEXT: vqaddt.s32 q1, q0, q12543; CHECK-NEXT: vmov q0, q12544; CHECK-NEXT: bx lr2545entry:2546 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2547 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2548 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2549 ret <4 x i32> %b2550}2551 2552define arm_aapcs_vfpcc <8 x i16> @sadd_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2553; CHECK-LABEL: sadd_sat_v8i16_y:2554; CHECK: @ %bb.0: @ %entry2555; CHECK-NEXT: vctp.16 r02556; CHECK-NEXT: vpst2557; CHECK-NEXT: vqaddt.s16 q1, q0, q12558; CHECK-NEXT: vmov q0, q12559; CHECK-NEXT: bx lr2560entry:2561 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2562 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2563 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2564 ret <8 x i16> %b2565}2566 2567define arm_aapcs_vfpcc <16 x i8> @sadd_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2568; CHECK-LABEL: sadd_sat_v16i8_y:2569; CHECK: @ %bb.0: @ %entry2570; CHECK-NEXT: vctp.8 r02571; CHECK-NEXT: vpst2572; CHECK-NEXT: vqaddt.s8 q1, q0, q12573; CHECK-NEXT: vmov q0, q12574; CHECK-NEXT: bx lr2575entry:2576 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2577 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2578 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2579 ret <16 x i8> %b2580}2581 2582define arm_aapcs_vfpcc <4 x i32> @uadd_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2583; CHECK-LABEL: uadd_sat_v4i32_y:2584; CHECK: @ %bb.0: @ %entry2585; CHECK-NEXT: vctp.32 r02586; CHECK-NEXT: vpst2587; CHECK-NEXT: vqaddt.u32 q1, q0, q12588; CHECK-NEXT: vmov q0, q12589; CHECK-NEXT: bx lr2590entry:2591 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2592 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2593 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2594 ret <4 x i32> %b2595}2596 2597define arm_aapcs_vfpcc <8 x i16> @uadd_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2598; CHECK-LABEL: uadd_sat_v8i16_y:2599; CHECK: @ %bb.0: @ %entry2600; CHECK-NEXT: vctp.16 r02601; CHECK-NEXT: vpst2602; CHECK-NEXT: vqaddt.u16 q1, q0, q12603; CHECK-NEXT: vmov q0, q12604; CHECK-NEXT: bx lr2605entry:2606 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2607 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2608 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2609 ret <8 x i16> %b2610}2611 2612define arm_aapcs_vfpcc <16 x i8> @uadd_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2613; CHECK-LABEL: uadd_sat_v16i8_y:2614; CHECK: @ %bb.0: @ %entry2615; CHECK-NEXT: vctp.8 r02616; CHECK-NEXT: vpst2617; CHECK-NEXT: vqaddt.u8 q1, q0, q12618; CHECK-NEXT: vmov q0, q12619; CHECK-NEXT: bx lr2620entry:2621 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2622 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2623 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2624 ret <16 x i8> %b2625}2626 2627define arm_aapcs_vfpcc <4 x i32> @ssub_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2628; CHECK-LABEL: ssub_sat_v4i32_y:2629; CHECK: @ %bb.0: @ %entry2630; CHECK-NEXT: vctp.32 r02631; CHECK-NEXT: vpst2632; CHECK-NEXT: vqsubt.s32 q1, q0, q12633; CHECK-NEXT: vmov q0, q12634; CHECK-NEXT: bx lr2635entry:2636 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2637 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2638 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2639 ret <4 x i32> %b2640}2641 2642define arm_aapcs_vfpcc <8 x i16> @ssub_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2643; CHECK-LABEL: ssub_sat_v8i16_y:2644; CHECK: @ %bb.0: @ %entry2645; CHECK-NEXT: vctp.16 r02646; CHECK-NEXT: vpst2647; CHECK-NEXT: vqsubt.s16 q1, q0, q12648; CHECK-NEXT: vmov q0, q12649; CHECK-NEXT: bx lr2650entry:2651 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2652 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2653 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2654 ret <8 x i16> %b2655}2656 2657define arm_aapcs_vfpcc <16 x i8> @ssub_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2658; CHECK-LABEL: ssub_sat_v16i8_y:2659; CHECK: @ %bb.0: @ %entry2660; CHECK-NEXT: vctp.8 r02661; CHECK-NEXT: vpst2662; CHECK-NEXT: vqsubt.s8 q1, q0, q12663; CHECK-NEXT: vmov q0, q12664; CHECK-NEXT: bx lr2665entry:2666 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2667 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2668 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2669 ret <16 x i8> %b2670}2671 2672define arm_aapcs_vfpcc <4 x i32> @usub_sat_v4i32_y(<4 x i32> %x, <4 x i32> %y, i32 %n) {2673; CHECK-LABEL: usub_sat_v4i32_y:2674; CHECK: @ %bb.0: @ %entry2675; CHECK-NEXT: vctp.32 r02676; CHECK-NEXT: vpst2677; CHECK-NEXT: vqsubt.u32 q1, q0, q12678; CHECK-NEXT: vmov q0, q12679; CHECK-NEXT: bx lr2680entry:2681 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2682 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)2683 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %y2684 ret <4 x i32> %b2685}2686 2687define arm_aapcs_vfpcc <8 x i16> @usub_sat_v8i16_y(<8 x i16> %x, <8 x i16> %y, i32 %n) {2688; CHECK-LABEL: usub_sat_v8i16_y:2689; CHECK: @ %bb.0: @ %entry2690; CHECK-NEXT: vctp.16 r02691; CHECK-NEXT: vpst2692; CHECK-NEXT: vqsubt.u16 q1, q0, q12693; CHECK-NEXT: vmov q0, q12694; CHECK-NEXT: bx lr2695entry:2696 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2697 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)2698 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %y2699 ret <8 x i16> %b2700}2701 2702define arm_aapcs_vfpcc <16 x i8> @usub_sat_v16i8_y(<16 x i8> %x, <16 x i8> %y, i32 %n) {2703; CHECK-LABEL: usub_sat_v16i8_y:2704; CHECK: @ %bb.0: @ %entry2705; CHECK-NEXT: vctp.8 r02706; CHECK-NEXT: vpst2707; CHECK-NEXT: vqsubt.u8 q1, q0, q12708; CHECK-NEXT: vmov q0, q12709; CHECK-NEXT: bx lr2710entry:2711 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2712 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)2713 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %y2714 ret <16 x i8> %b2715}2716 2717define arm_aapcs_vfpcc <4 x i32> @addqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2718; CHECK-LABEL: addqr_v4i32_y:2719; CHECK: @ %bb.0: @ %entry2720; CHECK-NEXT: vdup.32 q1, r02721; CHECK-NEXT: vctp.32 r12722; CHECK-NEXT: vpst2723; CHECK-NEXT: vaddt.i32 q1, q0, r02724; CHECK-NEXT: vmov q0, q12725; CHECK-NEXT: bx lr2726entry:2727 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2728 %i = insertelement <4 x i32> undef, i32 %y, i64 02729 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2730 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer2731 %b = add <4 x i32> %ys, %a2732 ret <4 x i32> %b2733}2734 2735define arm_aapcs_vfpcc <8 x i16> @addqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2736; CHECK-LABEL: addqr_v8i16_y:2737; CHECK: @ %bb.0: @ %entry2738; CHECK-NEXT: vdup.16 q1, r02739; CHECK-NEXT: vctp.16 r12740; CHECK-NEXT: vpst2741; CHECK-NEXT: vaddt.i16 q1, q0, r02742; CHECK-NEXT: vmov q0, q12743; CHECK-NEXT: bx lr2744entry:2745 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2746 %i = insertelement <8 x i16> undef, i16 %y, i64 02747 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2748 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer2749 %b = add <8 x i16> %ys, %a2750 ret <8 x i16> %b2751}2752 2753define arm_aapcs_vfpcc <16 x i8> @addqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2754; CHECK-LABEL: addqr_v16i8_y:2755; CHECK: @ %bb.0: @ %entry2756; CHECK-NEXT: vdup.8 q1, r02757; CHECK-NEXT: vctp.8 r12758; CHECK-NEXT: vpst2759; CHECK-NEXT: vaddt.i8 q1, q0, r02760; CHECK-NEXT: vmov q0, q12761; CHECK-NEXT: bx lr2762entry:2763 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2764 %i = insertelement <16 x i8> undef, i8 %y, i64 02765 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2766 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer2767 %b = add <16 x i8> %ys, %a2768 ret <16 x i8> %b2769}2770 2771define arm_aapcs_vfpcc <4 x i32> @subqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2772; CHECK-LABEL: subqr_v4i32_y:2773; CHECK: @ %bb.0: @ %entry2774; CHECK-NEXT: vdup.32 q1, r02775; CHECK-NEXT: vctp.32 r12776; CHECK-NEXT: vpst2777; CHECK-NEXT: vsubt.i32 q1, q0, r02778; CHECK-NEXT: vmov q0, q12779; CHECK-NEXT: bx lr2780entry:2781 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2782 %i = insertelement <4 x i32> undef, i32 %y, i64 02783 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2784 %a = sub <4 x i32> %x, %ys2785 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys2786 ret <4 x i32> %b2787}2788 2789define arm_aapcs_vfpcc <8 x i16> @subqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2790; CHECK-LABEL: subqr_v8i16_y:2791; CHECK: @ %bb.0: @ %entry2792; CHECK-NEXT: vdup.16 q1, r02793; CHECK-NEXT: vctp.16 r12794; CHECK-NEXT: vpst2795; CHECK-NEXT: vsubt.i16 q1, q0, r02796; CHECK-NEXT: vmov q0, q12797; CHECK-NEXT: bx lr2798entry:2799 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2800 %i = insertelement <8 x i16> undef, i16 %y, i64 02801 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2802 %a = sub <8 x i16> %x, %ys2803 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys2804 ret <8 x i16> %b2805}2806 2807define arm_aapcs_vfpcc <16 x i8> @subqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2808; CHECK-LABEL: subqr_v16i8_y:2809; CHECK: @ %bb.0: @ %entry2810; CHECK-NEXT: vdup.8 q1, r02811; CHECK-NEXT: vctp.8 r12812; CHECK-NEXT: vpst2813; CHECK-NEXT: vsubt.i8 q1, q0, r02814; CHECK-NEXT: vmov q0, q12815; CHECK-NEXT: bx lr2816entry:2817 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2818 %i = insertelement <16 x i8> undef, i8 %y, i64 02819 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2820 %a = sub <16 x i8> %x, %ys2821 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys2822 ret <16 x i8> %b2823}2824 2825define arm_aapcs_vfpcc <4 x i32> @mulqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2826; CHECK-LABEL: mulqr_v4i32_y:2827; CHECK: @ %bb.0: @ %entry2828; CHECK-NEXT: vdup.32 q1, r02829; CHECK-NEXT: vctp.32 r12830; CHECK-NEXT: vpst2831; CHECK-NEXT: vmult.i32 q1, q0, r02832; CHECK-NEXT: vmov q0, q12833; CHECK-NEXT: bx lr2834entry:2835 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2836 %i = insertelement <4 x i32> undef, i32 %y, i64 02837 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer2838 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 1, i32 1, i32 1, i32 1>2839 %b = mul <4 x i32> %ys, %a2840 ret <4 x i32> %b2841}2842 2843define arm_aapcs_vfpcc <8 x i16> @mulqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {2844; CHECK-LABEL: mulqr_v8i16_y:2845; CHECK: @ %bb.0: @ %entry2846; CHECK-NEXT: vdup.16 q1, r02847; CHECK-NEXT: vctp.16 r12848; CHECK-NEXT: vpst2849; CHECK-NEXT: vmult.i16 q1, q0, r02850; CHECK-NEXT: vmov q0, q12851; CHECK-NEXT: bx lr2852entry:2853 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2854 %i = insertelement <8 x i16> undef, i16 %y, i64 02855 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer2856 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2857 %b = mul <8 x i16> %ys, %a2858 ret <8 x i16> %b2859}2860 2861define arm_aapcs_vfpcc <16 x i8> @mulqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {2862; CHECK-LABEL: mulqr_v16i8_y:2863; CHECK: @ %bb.0: @ %entry2864; CHECK-NEXT: vdup.8 q1, r02865; CHECK-NEXT: vctp.8 r12866; CHECK-NEXT: vpst2867; CHECK-NEXT: vmult.i8 q1, q0, r02868; CHECK-NEXT: vmov q0, q12869; CHECK-NEXT: bx lr2870entry:2871 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)2872 %i = insertelement <16 x i8> undef, i8 %y, i64 02873 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer2874 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>2875 %b = mul <16 x i8> %ys, %a2876 ret <16 x i8> %b2877}2878 2879define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2880; CHECK-LABEL: faddqr_v4f32_y:2881; CHECK: @ %bb.0: @ %entry2882; CHECK-NEXT: vmov r1, s42883; CHECK-NEXT: vctp.32 r02884; CHECK-NEXT: vdup.32 q1, r12885; CHECK-NEXT: vpst2886; CHECK-NEXT: vaddt.f32 q1, q0, r12887; CHECK-NEXT: vmov q0, q12888; CHECK-NEXT: bx lr2889entry:2890 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2891 %i = insertelement <4 x float> undef, float %y, i64 02892 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2893 %a = select <4 x i1> %c, <4 x float> %x, <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>2894 %b = fadd <4 x float> %ys, %a2895 ret <4 x float> %b2896}2897 2898define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2899; CHECK-LABEL: faddqr_v8f16_y:2900; CHECK: @ %bb.0: @ %entry2901; CHECK-NEXT: vmov.f16 r1, s42902; CHECK-NEXT: vctp.16 r02903; CHECK-NEXT: vdup.16 q1, r12904; CHECK-NEXT: vpst2905; CHECK-NEXT: vaddt.f16 q1, q0, r12906; CHECK-NEXT: vmov q0, q12907; CHECK-NEXT: bx lr2908entry:2909 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2910 %i = insertelement <8 x half> undef, half %y, i64 02911 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2912 %a = select <8 x i1> %c, <8 x half> %x, <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>2913 %b = fadd <8 x half> %ys, %a2914 ret <8 x half> %b2915}2916 2917define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2918; CHECK-LABEL: fsubqr_v4f32_y:2919; CHECK: @ %bb.0: @ %entry2920; CHECK-NEXT: vmov r1, s42921; CHECK-NEXT: vctp.32 r02922; CHECK-NEXT: vdup.32 q1, r12923; CHECK-NEXT: vpst2924; CHECK-NEXT: vsubt.f32 q1, q0, r12925; CHECK-NEXT: vmov q0, q12926; CHECK-NEXT: bx lr2927entry:2928 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2929 %i = insertelement <4 x float> undef, float %y, i64 02930 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2931 %a = fsub <4 x float> %x, %ys2932 %b = select <4 x i1> %c, <4 x float> %a, <4 x float> %ys2933 ret <4 x float> %b2934}2935 2936define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2937; CHECK-LABEL: fsubqr_v8f16_y:2938; CHECK: @ %bb.0: @ %entry2939; CHECK-NEXT: vmov.f16 r1, s42940; CHECK-NEXT: vctp.16 r02941; CHECK-NEXT: vdup.16 q1, r12942; CHECK-NEXT: vpst2943; CHECK-NEXT: vsubt.f16 q1, q0, r12944; CHECK-NEXT: vmov q0, q12945; CHECK-NEXT: bx lr2946entry:2947 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2948 %i = insertelement <8 x half> undef, half %y, i64 02949 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2950 %a = fsub <8 x half> %x, %ys2951 %b = select <8 x i1> %c, <8 x half> %a, <8 x half> %ys2952 ret <8 x half> %b2953}2954 2955define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {2956; CHECK-LABEL: fmulqr_v4f32_y:2957; CHECK: @ %bb.0: @ %entry2958; CHECK-NEXT: vmov r1, s42959; CHECK-NEXT: vctp.32 r02960; CHECK-NEXT: vdup.32 q1, r12961; CHECK-NEXT: vpst2962; CHECK-NEXT: vmult.f32 q1, q0, r12963; CHECK-NEXT: vmov q0, q12964; CHECK-NEXT: bx lr2965entry:2966 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)2967 %i = insertelement <4 x float> undef, float %y, i64 02968 %ys = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2969 %a = select <4 x i1> %c, <4 x float> %x, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>2970 %b = fmul <4 x float> %ys, %a2971 ret <4 x float> %b2972}2973 2974define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {2975; CHECK-LABEL: fmulqr_v8f16_y:2976; CHECK: @ %bb.0: @ %entry2977; CHECK-NEXT: vmov.f16 r1, s42978; CHECK-NEXT: vctp.16 r02979; CHECK-NEXT: vdup.16 q1, r12980; CHECK-NEXT: vpst2981; CHECK-NEXT: vmult.f16 q1, q0, r12982; CHECK-NEXT: vmov q0, q12983; CHECK-NEXT: bx lr2984entry:2985 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)2986 %i = insertelement <8 x half> undef, half %y, i64 02987 %ys = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2988 %a = select <8 x i1> %c, <8 x half> %x, <8 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>2989 %b = fmul <8 x half> %ys, %a2990 ret <8 x half> %b2991}2992 2993define arm_aapcs_vfpcc <4 x i32> @sadd_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {2994; CHECK-LABEL: sadd_satqr_v4i32_y:2995; CHECK: @ %bb.0: @ %entry2996; CHECK-NEXT: vdup.32 q1, r02997; CHECK-NEXT: vctp.32 r12998; CHECK-NEXT: vpst2999; CHECK-NEXT: vqaddt.s32 q1, q0, r03000; CHECK-NEXT: vmov q0, q13001; CHECK-NEXT: bx lr3002entry:3003 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3004 %i = insertelement <4 x i32> undef, i32 %y, i64 03005 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3006 %a = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3007 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3008 ret <4 x i32> %b3009}3010 3011define arm_aapcs_vfpcc <8 x i16> @sadd_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3012; CHECK-LABEL: sadd_satqr_v8i16_y:3013; CHECK: @ %bb.0: @ %entry3014; CHECK-NEXT: vdup.16 q1, r03015; CHECK-NEXT: vctp.16 r13016; CHECK-NEXT: vpst3017; CHECK-NEXT: vqaddt.s16 q1, q0, r03018; CHECK-NEXT: vmov q0, q13019; CHECK-NEXT: bx lr3020entry:3021 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3022 %i = insertelement <8 x i16> undef, i16 %y, i64 03023 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3024 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3025 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3026 ret <8 x i16> %b3027}3028 3029define arm_aapcs_vfpcc <16 x i8> @sadd_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3030; CHECK-LABEL: sadd_satqr_v16i8_y:3031; CHECK: @ %bb.0: @ %entry3032; CHECK-NEXT: vdup.8 q1, r03033; CHECK-NEXT: vctp.8 r13034; CHECK-NEXT: vpst3035; CHECK-NEXT: vqaddt.s8 q1, q0, r03036; CHECK-NEXT: vmov q0, q13037; CHECK-NEXT: bx lr3038entry:3039 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3040 %i = insertelement <16 x i8> undef, i8 %y, i64 03041 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3042 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3043 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3044 ret <16 x i8> %b3045}3046 3047define arm_aapcs_vfpcc <4 x i32> @uadd_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3048; CHECK-LABEL: uadd_satqr_v4i32_y:3049; CHECK: @ %bb.0: @ %entry3050; CHECK-NEXT: vdup.32 q1, r03051; CHECK-NEXT: vctp.32 r13052; CHECK-NEXT: vpst3053; CHECK-NEXT: vqaddt.u32 q1, q0, r03054; CHECK-NEXT: vmov q0, q13055; CHECK-NEXT: bx lr3056entry:3057 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3058 %i = insertelement <4 x i32> undef, i32 %y, i64 03059 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3060 %a = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3061 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3062 ret <4 x i32> %b3063}3064 3065define arm_aapcs_vfpcc <8 x i16> @uadd_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3066; CHECK-LABEL: uadd_satqr_v8i16_y:3067; CHECK: @ %bb.0: @ %entry3068; CHECK-NEXT: vdup.16 q1, r03069; CHECK-NEXT: vctp.16 r13070; CHECK-NEXT: vpst3071; CHECK-NEXT: vqaddt.u16 q1, q0, r03072; CHECK-NEXT: vmov q0, q13073; CHECK-NEXT: bx lr3074entry:3075 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3076 %i = insertelement <8 x i16> undef, i16 %y, i64 03077 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3078 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3079 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3080 ret <8 x i16> %b3081}3082 3083define arm_aapcs_vfpcc <16 x i8> @uadd_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3084; CHECK-LABEL: uadd_satqr_v16i8_y:3085; CHECK: @ %bb.0: @ %entry3086; CHECK-NEXT: vdup.8 q1, r03087; CHECK-NEXT: vctp.8 r13088; CHECK-NEXT: vpst3089; CHECK-NEXT: vqaddt.u8 q1, q0, r03090; CHECK-NEXT: vmov q0, q13091; CHECK-NEXT: bx lr3092entry:3093 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3094 %i = insertelement <16 x i8> undef, i8 %y, i64 03095 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3096 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3097 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3098 ret <16 x i8> %b3099}3100 3101define arm_aapcs_vfpcc <4 x i32> @ssub_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3102; CHECK-LABEL: ssub_satqr_v4i32_y:3103; CHECK: @ %bb.0: @ %entry3104; CHECK-NEXT: vdup.32 q1, r03105; CHECK-NEXT: vctp.32 r13106; CHECK-NEXT: vpst3107; CHECK-NEXT: vqsubt.s32 q1, q0, r03108; CHECK-NEXT: vmov q0, q13109; CHECK-NEXT: bx lr3110entry:3111 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3112 %i = insertelement <4 x i32> undef, i32 %y, i64 03113 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3114 %a = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3115 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3116 ret <4 x i32> %b3117}3118 3119define arm_aapcs_vfpcc <8 x i16> @ssub_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3120; CHECK-LABEL: ssub_satqr_v8i16_y:3121; CHECK: @ %bb.0: @ %entry3122; CHECK-NEXT: vdup.16 q1, r03123; CHECK-NEXT: vctp.16 r13124; CHECK-NEXT: vpst3125; CHECK-NEXT: vqsubt.s16 q1, q0, r03126; CHECK-NEXT: vmov q0, q13127; CHECK-NEXT: bx lr3128entry:3129 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3130 %i = insertelement <8 x i16> undef, i16 %y, i64 03131 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3132 %a = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3133 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3134 ret <8 x i16> %b3135}3136 3137define arm_aapcs_vfpcc <16 x i8> @ssub_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3138; CHECK-LABEL: ssub_satqr_v16i8_y:3139; CHECK: @ %bb.0: @ %entry3140; CHECK-NEXT: vdup.8 q1, r03141; CHECK-NEXT: vctp.8 r13142; CHECK-NEXT: vpst3143; CHECK-NEXT: vqsubt.s8 q1, q0, r03144; CHECK-NEXT: vmov q0, q13145; CHECK-NEXT: bx lr3146entry:3147 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3148 %i = insertelement <16 x i8> undef, i8 %y, i64 03149 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3150 %a = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3151 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3152 ret <16 x i8> %b3153}3154 3155define arm_aapcs_vfpcc <4 x i32> @usub_satqr_v4i32_y(<4 x i32> %x, i32 %y, i32 %n) {3156; CHECK-LABEL: usub_satqr_v4i32_y:3157; CHECK: @ %bb.0: @ %entry3158; CHECK-NEXT: vdup.32 q1, r03159; CHECK-NEXT: vctp.32 r13160; CHECK-NEXT: vpst3161; CHECK-NEXT: vqsubt.u32 q1, q0, r03162; CHECK-NEXT: vmov q0, q13163; CHECK-NEXT: bx lr3164entry:3165 %c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)3166 %i = insertelement <4 x i32> undef, i32 %y, i64 03167 %ys = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer3168 %a = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %ys)3169 %b = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %ys3170 ret <4 x i32> %b3171}3172 3173define arm_aapcs_vfpcc <8 x i16> @usub_satqr_v8i16_y(<8 x i16> %x, i16 %y, i32 %n) {3174; CHECK-LABEL: usub_satqr_v8i16_y:3175; CHECK: @ %bb.0: @ %entry3176; CHECK-NEXT: vdup.16 q1, r03177; CHECK-NEXT: vctp.16 r13178; CHECK-NEXT: vpst3179; CHECK-NEXT: vqsubt.u16 q1, q0, r03180; CHECK-NEXT: vmov q0, q13181; CHECK-NEXT: bx lr3182entry:3183 %c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)3184 %i = insertelement <8 x i16> undef, i16 %y, i64 03185 %ys = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3186 %a = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %ys)3187 %b = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %ys3188 ret <8 x i16> %b3189}3190 3191define arm_aapcs_vfpcc <16 x i8> @usub_satqr_v16i8_y(<16 x i8> %x, i8 %y, i32 %n) {3192; CHECK-LABEL: usub_satqr_v16i8_y:3193; CHECK: @ %bb.0: @ %entry3194; CHECK-NEXT: vdup.8 q1, r03195; CHECK-NEXT: vctp.8 r13196; CHECK-NEXT: vpst3197; CHECK-NEXT: vqsubt.u8 q1, q0, r03198; CHECK-NEXT: vmov q0, q13199; CHECK-NEXT: bx lr3200entry:3201 %c = call <16 x i1> @llvm.arm.mve.vctp8(i32 %n)3202 %i = insertelement <16 x i8> undef, i8 %y, i64 03203 %ys = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer3204 %a = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %ys)3205 %b = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %ys3206 ret <16 x i8> %b3207}3208 3209declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)3210declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)3211declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)3212declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)3213declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)3214declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)3215declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)3216declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)3217declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)3218declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)3219declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)3220declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)3221 3222declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)3223declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)3224declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)3225declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)3226declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)3227declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)3228declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>)3229declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>)3230declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)3231declare <16 x i8> @llvm.smax.v16i8(<16 x i8>, <16 x i8>)3232declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>)3233declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)3234 3235declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)3236declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)3237 3238declare <16 x i1> @llvm.arm.mve.vctp8(i32)3239declare <8 x i1> @llvm.arm.mve.vctp16(i32)3240declare <4 x i1> @llvm.arm.mve.vctp32(i32)3241