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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -verify-machineinstrs -o - | FileCheck %s3 4define void @arm_min_helium_f32(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult, ptr nocapture %pIndex) {5; CHECK-LABEL: arm_min_helium_f32:6; CHECK:       @ %bb.0: @ %entry7; CHECK-NEXT:    .save {r4, r5, r7, lr}8; CHECK-NEXT:    push {r4, r5, r7, lr}9; CHECK-NEXT:    movs r4, #010; CHECK-NEXT:    mov.w r12, #411; CHECK-NEXT:    vidup.u32 q2, r4, #112; CHECK-NEXT:    movw r5, #5443713; CHECK-NEXT:    movt r5, #2135214; CHECK-NEXT:    vmov.i32 q0, #0x015; CHECK-NEXT:    vdup.32 q1, r516; CHECK-NEXT:    dlstp.32 lr, r117; CHECK-NEXT:  .LBB0_1: @ %do.body18; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=119; CHECK-NEXT:    vldrw.u32 q3, [r0], #1620; CHECK-NEXT:    vptt.f32 ge, q1, q321; CHECK-NEXT:    vmovt q0, q222; CHECK-NEXT:    vmovt q1, q323; CHECK-NEXT:    vadd.i32 q2, q2, r1224; CHECK-NEXT:    letp lr, .LBB0_125; CHECK-NEXT:  @ %bb.2: @ %do.end26; CHECK-NEXT:    vldr s8, .LCPI0_027; CHECK-NEXT:    vdup.32 q3, r128; CHECK-NEXT:    vmov r0, s829; CHECK-NEXT:    vminnmv.f32 r0, q130; CHECK-NEXT:    vcmp.f32 le, q1, r031; CHECK-NEXT:    vmov s8, r032; CHECK-NEXT:    vpsel q0, q0, q333; CHECK-NEXT:    vminv.u32 r1, q034; CHECK-NEXT:    str r1, [r3]35; CHECK-NEXT:    vstr s8, [r2]36; CHECK-NEXT:    pop {r4, r5, r7, pc}37; CHECK-NEXT:    .p2align 238; CHECK-NEXT:  @ %bb.3:39; CHECK-NEXT:  .LCPI0_0:40; CHECK-NEXT:    .long 0x5368d4a5 @ float 9.99999995E+1141entry:42  %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 1)43  %1 = extractvalue { <4 x i32>, i32 } %0, 044  br label %do.body45 46do.body:                                          ; preds = %do.body, %entry47  %curExtremValVec.0 = phi <4 x float> [ <float 0x426D1A94A0000000, float 0x426D1A94A0000000, float 0x426D1A94A0000000, float 0x426D1A94A0000000>, %entry ], [ %8, %do.body ]48  %indexVec.0 = phi <4 x i32> [ %1, %entry ], [ %11, %do.body ]49  %2 = phi <4 x float> [ zeroinitializer, %entry ], [ %10, %do.body ]50  %blkCnt.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]51  %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]52  %3 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)53  %4 = bitcast ptr %pSrc.addr.0 to ptr54  %5 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %4, i32 4, <4 x i1> %3, <4 x float> zeroinitializer)55  %6 = fcmp fast ole <4 x float> %5, %curExtremValVec.056  %7 = and <4 x i1> %6, %357  %8 = select fast <4 x i1> %7, <4 x float> %5, <4 x float> %curExtremValVec.058  %9 = bitcast <4 x i32> %indexVec.0 to <4 x float>59  %10 = select fast <4 x i1> %7, <4 x float> %9, <4 x float> %260  %11 = add <4 x i32> %indexVec.0, <i32 4, i32 4, i32 4, i32 4>61  %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 462  %sub = add nsw i32 %blkCnt.0, -463  %cmp = icmp sgt i32 %blkCnt.0, 464  br i1 %cmp, label %do.body, label %do.end65 66do.end:                                           ; preds = %do.body67  %12 = bitcast <4 x float> %10 to <4 x i32>68  %13 = tail call fast float @llvm.arm.mve.minnmv.f32.v4f32(float 0x426D1A94A0000000, <4 x float> %8)69  %.splatinsert = insertelement <4 x float> undef, float %13, i32 070  %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer71  %14 = fcmp fast ole <4 x float> %8, %.splat72  %.splatinsert1 = insertelement <4 x i32> undef, i32 %blockSize, i32 073  %.splat2 = shufflevector <4 x i32> %.splatinsert1, <4 x i32> undef, <4 x i32> zeroinitializer74  %15 = select <4 x i1> %14, <4 x i32> %12, <4 x i32> %.splat275  %16 = tail call i32 @llvm.arm.mve.minv.v4i32(i32 %blockSize, <4 x i32> %15, i32 1)76  store i32 %16, ptr %pIndex, align 477  store float %13, ptr %pResult, align 478  ret void79}80 81declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #182declare <4 x i1> @llvm.arm.mve.vctp32(i32) #183declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #284declare float @llvm.arm.mve.minnmv.f32.v4f32(float, <4 x float>) #185declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #186