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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {5; CHECK-LABEL: cmpeqz_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vpt.i32 eq, q1, zr8; CHECK-NEXT: vcmpt.i32 ne, q2, zr9; CHECK-NEXT: vmrs r0, p010; CHECK-NEXT: vpt.i32 eq, q0, zr11; CHECK-NEXT: vcmpt.i32 eq, q2, zr12; CHECK-NEXT: vmrs r1, p013; CHECK-NEXT: orrs r0, r114; CHECK-NEXT: vmsr p0, r015; CHECK-NEXT: vpsel q0, q0, q116; CHECK-NEXT: bx lr17entry:18 %c1 = icmp eq <4 x i32> %a, zeroinitializer19 %c2 = icmp eq <4 x i32> %b, zeroinitializer20 %c3 = icmp eq <4 x i32> %c, zeroinitializer21 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c222 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b23 ret <4 x i32> %s24}25 26define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {27; CHECK-LABEL: cmpeqz_v8i1:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vpt.i16 eq, q1, zr30; CHECK-NEXT: vcmpt.i16 ne, q2, zr31; CHECK-NEXT: vmrs r0, p032; CHECK-NEXT: vpt.i16 eq, q0, zr33; CHECK-NEXT: vcmpt.i16 eq, q2, zr34; CHECK-NEXT: vmrs r1, p035; CHECK-NEXT: orrs r0, r136; CHECK-NEXT: vmsr p0, r037; CHECK-NEXT: vpsel q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %c1 = icmp eq <8 x i16> %a, zeroinitializer41 %c2 = icmp eq <8 x i16> %b, zeroinitializer42 %c3 = icmp eq <8 x i16> %c, zeroinitializer43 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c244 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b45 ret <8 x i16> %s46}47 48define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {49; CHECK-LABEL: cmpeqz_v16i1:50; CHECK: @ %bb.0: @ %entry51; CHECK-NEXT: vpt.i8 eq, q1, zr52; CHECK-NEXT: vcmpt.i8 ne, q2, zr53; CHECK-NEXT: vmrs r0, p054; CHECK-NEXT: vpt.i8 eq, q0, zr55; CHECK-NEXT: vcmpt.i8 eq, q2, zr56; CHECK-NEXT: vmrs r1, p057; CHECK-NEXT: orrs r0, r158; CHECK-NEXT: vmsr p0, r059; CHECK-NEXT: vpsel q0, q0, q160; CHECK-NEXT: bx lr61entry:62 %c1 = icmp eq <16 x i8> %a, zeroinitializer63 %c2 = icmp eq <16 x i8> %b, zeroinitializer64 %c3 = icmp eq <16 x i8> %c, zeroinitializer65 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c266 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b67 ret <16 x i8> %s68}69 70define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {71; CHECK-LABEL: cmpeqz_v2i1:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: vmov r0, r1, d074; CHECK-NEXT: orrs r0, r175; CHECK-NEXT: vmov r1, r2, d276; CHECK-NEXT: cset r0, eq77; CHECK-NEXT: orrs r1, r278; CHECK-NEXT: vmov r2, r3, d479; CHECK-NEXT: cset r1, eq80; CHECK-NEXT: orrs r2, r381; CHECK-NEXT: csel r0, r0, r1, eq82; CHECK-NEXT: movs r1, #083; CHECK-NEXT: rsbs r0, r0, #084; CHECK-NEXT: bfi r1, r0, #0, #885; CHECK-NEXT: vmov r0, r2, d186; CHECK-NEXT: orrs r0, r287; CHECK-NEXT: vmov r2, r3, d388; CHECK-NEXT: cset r12, eq89; CHECK-NEXT: orrs r2, r390; CHECK-NEXT: vmov r3, r0, d591; CHECK-NEXT: cset r2, eq92; CHECK-NEXT: orrs r0, r393; CHECK-NEXT: csel r0, r12, r2, eq94; CHECK-NEXT: rsbs r0, r0, #095; CHECK-NEXT: bfi r1, r0, #8, #896; CHECK-NEXT: vmsr p0, r197; CHECK-NEXT: vpsel q0, q0, q198; CHECK-NEXT: bx lr99entry:100 %c1 = icmp eq <2 x i64> %a, zeroinitializer101 %c2 = icmp eq <2 x i64> %b, zeroinitializer102 %c3 = icmp eq <2 x i64> %c, zeroinitializer103 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2104 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b105 ret <2 x i64> %s106}107 108define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {109; CHECK-LABEL: cmpnez_v4i1:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vpt.i32 ne, q1, zr112; CHECK-NEXT: vcmpt.i32 eq, q2, zr113; CHECK-NEXT: vmrs r0, p0114; CHECK-NEXT: vpt.i32 ne, q0, zr115; CHECK-NEXT: vcmpt.i32 ne, q2, zr116; CHECK-NEXT: vmrs r1, p0117; CHECK-NEXT: orrs r0, r1118; CHECK-NEXT: vmsr p0, r0119; CHECK-NEXT: vpsel q0, q0, q1120; CHECK-NEXT: bx lr121entry:122 %c1 = icmp ne <4 x i32> %a, zeroinitializer123 %c2 = icmp ne <4 x i32> %b, zeroinitializer124 %c3 = icmp ne <4 x i32> %c, zeroinitializer125 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c2126 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b127 ret <4 x i32> %s128}129 130define arm_aapcs_vfpcc <8 x i16> @cmpnez_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {131; CHECK-LABEL: cmpnez_v8i1:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vpt.i16 ne, q1, zr134; CHECK-NEXT: vcmpt.i16 eq, q2, zr135; CHECK-NEXT: vmrs r0, p0136; CHECK-NEXT: vpt.i16 ne, q0, zr137; CHECK-NEXT: vcmpt.i16 ne, q2, zr138; CHECK-NEXT: vmrs r1, p0139; CHECK-NEXT: orrs r0, r1140; CHECK-NEXT: vmsr p0, r0141; CHECK-NEXT: vpsel q0, q0, q1142; CHECK-NEXT: bx lr143entry:144 %c1 = icmp ne <8 x i16> %a, zeroinitializer145 %c2 = icmp ne <8 x i16> %b, zeroinitializer146 %c3 = icmp ne <8 x i16> %c, zeroinitializer147 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c2148 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b149 ret <8 x i16> %s150}151 152define arm_aapcs_vfpcc <16 x i8> @cmpnez_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {153; CHECK-LABEL: cmpnez_v16i1:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vpt.i8 ne, q1, zr156; CHECK-NEXT: vcmpt.i8 eq, q2, zr157; CHECK-NEXT: vmrs r0, p0158; CHECK-NEXT: vpt.i8 ne, q0, zr159; CHECK-NEXT: vcmpt.i8 ne, q2, zr160; CHECK-NEXT: vmrs r1, p0161; CHECK-NEXT: orrs r0, r1162; CHECK-NEXT: vmsr p0, r0163; CHECK-NEXT: vpsel q0, q0, q1164; CHECK-NEXT: bx lr165entry:166 %c1 = icmp ne <16 x i8> %a, zeroinitializer167 %c2 = icmp ne <16 x i8> %b, zeroinitializer168 %c3 = icmp ne <16 x i8> %c, zeroinitializer169 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c2170 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b171 ret <16 x i8> %s172}173 174define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {175; CHECK-LABEL: cmpnez_v2i1:176; CHECK: @ %bb.0: @ %entry177; CHECK-NEXT: vmov r0, r1, d0178; CHECK-NEXT: orrs r0, r1179; CHECK-NEXT: vmov r1, r2, d2180; CHECK-NEXT: cset r0, ne181; CHECK-NEXT: orrs r1, r2182; CHECK-NEXT: vmov r2, r3, d4183; CHECK-NEXT: cset r1, ne184; CHECK-NEXT: orrs r2, r3185; CHECK-NEXT: csel r0, r0, r1, ne186; CHECK-NEXT: movs r1, #0187; CHECK-NEXT: rsbs r0, r0, #0188; CHECK-NEXT: bfi r1, r0, #0, #8189; CHECK-NEXT: vmov r0, r2, d1190; CHECK-NEXT: orrs r0, r2191; CHECK-NEXT: vmov r2, r3, d3192; CHECK-NEXT: cset r12, ne193; CHECK-NEXT: orrs r2, r3194; CHECK-NEXT: vmov r3, r0, d5195; CHECK-NEXT: cset r2, ne196; CHECK-NEXT: orrs r0, r3197; CHECK-NEXT: csel r0, r12, r2, ne198; CHECK-NEXT: rsbs r0, r0, #0199; CHECK-NEXT: bfi r1, r0, #8, #8200; CHECK-NEXT: vmsr p0, r1201; CHECK-NEXT: vpsel q0, q0, q1202; CHECK-NEXT: bx lr203entry:204 %c1 = icmp ne <2 x i64> %a, zeroinitializer205 %c2 = icmp ne <2 x i64> %b, zeroinitializer206 %c3 = icmp ne <2 x i64> %c, zeroinitializer207 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2208 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b209 ret <2 x i64> %s210}211 212 213 214define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {215; CHECK-LABEL: cmpsltz_v4i1:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vpt.s32 lt, q1, zr218; CHECK-NEXT: vcmpt.s32 ge, q2, zr219; CHECK-NEXT: vmrs r0, p0220; CHECK-NEXT: vpt.s32 lt, q0, zr221; CHECK-NEXT: vcmpt.s32 lt, q2, zr222; CHECK-NEXT: vmrs r1, p0223; CHECK-NEXT: orrs r0, r1224; CHECK-NEXT: vmsr p0, r0225; CHECK-NEXT: vpsel q0, q0, q1226; CHECK-NEXT: bx lr227entry:228 %c1 = icmp slt <4 x i32> %a, zeroinitializer229 %c2 = icmp slt <4 x i32> %b, zeroinitializer230 %c3 = icmp slt <4 x i32> %c, zeroinitializer231 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c2232 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b233 ret <4 x i32> %s234}235 236define arm_aapcs_vfpcc <8 x i16> @cmpsltz_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {237; CHECK-LABEL: cmpsltz_v8i1:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vpt.s16 lt, q1, zr240; CHECK-NEXT: vcmpt.s16 ge, q2, zr241; CHECK-NEXT: vmrs r0, p0242; CHECK-NEXT: vpt.s16 lt, q0, zr243; CHECK-NEXT: vcmpt.s16 lt, q2, zr244; CHECK-NEXT: vmrs r1, p0245; CHECK-NEXT: orrs r0, r1246; CHECK-NEXT: vmsr p0, r0247; CHECK-NEXT: vpsel q0, q0, q1248; CHECK-NEXT: bx lr249entry:250 %c1 = icmp slt <8 x i16> %a, zeroinitializer251 %c2 = icmp slt <8 x i16> %b, zeroinitializer252 %c3 = icmp slt <8 x i16> %c, zeroinitializer253 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c2254 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b255 ret <8 x i16> %s256}257 258define arm_aapcs_vfpcc <16 x i8> @cmpsltz_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {259; CHECK-LABEL: cmpsltz_v16i1:260; CHECK: @ %bb.0: @ %entry261; CHECK-NEXT: vpt.s8 lt, q1, zr262; CHECK-NEXT: vcmpt.s8 ge, q2, zr263; CHECK-NEXT: vmrs r0, p0264; CHECK-NEXT: vpt.s8 lt, q0, zr265; CHECK-NEXT: vcmpt.s8 lt, q2, zr266; CHECK-NEXT: vmrs r1, p0267; CHECK-NEXT: orrs r0, r1268; CHECK-NEXT: vmsr p0, r0269; CHECK-NEXT: vpsel q0, q0, q1270; CHECK-NEXT: bx lr271entry:272 %c1 = icmp slt <16 x i8> %a, zeroinitializer273 %c2 = icmp slt <16 x i8> %b, zeroinitializer274 %c3 = icmp slt <16 x i8> %c, zeroinitializer275 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c2276 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b277 ret <16 x i8> %s278}279 280define arm_aapcs_vfpcc <2 x i64> @cmpsltz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {281; CHECK-LABEL: cmpsltz_v2i1:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: vmov r2, s9284; CHECK-NEXT: movs r3, #0285; CHECK-NEXT: vmov r0, s1286; CHECK-NEXT: vmov r1, s5287; CHECK-NEXT: cmp.w r3, r2, lsr #31288; CHECK-NEXT: vmov r2, s7289; CHECK-NEXT: csel r0, r0, r1, ne290; CHECK-NEXT: vmov r1, s3291; CHECK-NEXT: asr.w r12, r0, #31292; CHECK-NEXT: vmov r0, s11293; CHECK-NEXT: cmp.w r3, r0, lsr #31294; CHECK-NEXT: bfi r3, r12, #0, #8295; CHECK-NEXT: csel r0, r1, r2, ne296; CHECK-NEXT: asrs r0, r0, #31297; CHECK-NEXT: bfi r3, r0, #8, #8298; CHECK-NEXT: vmsr p0, r3299; CHECK-NEXT: vpsel q0, q0, q1300; CHECK-NEXT: bx lr301entry:302 %c1 = icmp slt <2 x i64> %a, zeroinitializer303 %c2 = icmp slt <2 x i64> %b, zeroinitializer304 %c3 = icmp slt <2 x i64> %c, zeroinitializer305 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2306 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b307 ret <2 x i64> %s308}309 310 311 312define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1_i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {313; CHECK-LABEL: cmpeqz_v4i1_i1:314; CHECK: @ %bb.0: @ %entry315; CHECK-NEXT: cbz r0, .LBB12_2316; CHECK-NEXT: @ %bb.1: @ %select.false317; CHECK-NEXT: vcmp.i32 eq, q1, zr318; CHECK-NEXT: vpsel q0, q0, q1319; CHECK-NEXT: bx lr320; CHECK-NEXT: .LBB12_2:321; CHECK-NEXT: vcmp.i32 eq, q0, zr322; CHECK-NEXT: vpsel q0, q0, q1323; CHECK-NEXT: bx lr324entry:325 %c1 = icmp eq <4 x i32> %a, zeroinitializer326 %c2 = icmp eq <4 x i32> %b, zeroinitializer327 %c3 = icmp eq i32 %c, 0328 %c4 = select i1 %c3, <4 x i1> %c1, <4 x i1> %c2329 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b330 ret <4 x i32> %s331}332 333define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1_i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {334; CHECK-LABEL: cmpeqz_v8i1_i1:335; CHECK: @ %bb.0: @ %entry336; CHECK-NEXT: lsls r0, r0, #16337; CHECK-NEXT: beq .LBB13_2338; CHECK-NEXT: @ %bb.1: @ %select.false339; CHECK-NEXT: vcmp.i16 eq, q1, zr340; CHECK-NEXT: vpsel q0, q0, q1341; CHECK-NEXT: bx lr342; CHECK-NEXT: .LBB13_2:343; CHECK-NEXT: vcmp.i16 eq, q0, zr344; CHECK-NEXT: vpsel q0, q0, q1345; CHECK-NEXT: bx lr346entry:347 %c1 = icmp eq <8 x i16> %a, zeroinitializer348 %c2 = icmp eq <8 x i16> %b, zeroinitializer349 %c3 = icmp eq i16 %c, 0350 %c4 = select i1 %c3, <8 x i1> %c1, <8 x i1> %c2351 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b352 ret <8 x i16> %s353}354 355define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1_i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {356; CHECK-LABEL: cmpeqz_v16i1_i1:357; CHECK: @ %bb.0: @ %entry358; CHECK-NEXT: lsls r0, r0, #24359; CHECK-NEXT: beq .LBB14_2360; CHECK-NEXT: @ %bb.1: @ %select.false361; CHECK-NEXT: vcmp.i8 eq, q1, zr362; CHECK-NEXT: vpsel q0, q0, q1363; CHECK-NEXT: bx lr364; CHECK-NEXT: .LBB14_2:365; CHECK-NEXT: vcmp.i8 eq, q0, zr366; CHECK-NEXT: vpsel q0, q0, q1367; CHECK-NEXT: bx lr368entry:369 %c1 = icmp eq <16 x i8> %a, zeroinitializer370 %c2 = icmp eq <16 x i8> %b, zeroinitializer371 %c3 = icmp eq i8 %c, 0372 %c4 = select i1 %c3, <16 x i1> %c1, <16 x i1> %c2373 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b374 ret <16 x i8> %s375}376 377define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1_i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {378; CHECK-LABEL: cmpeqz_v2i1_i1:379; CHECK: @ %bb.0: @ %entry380; CHECK-NEXT: orrs r0, r1381; CHECK-NEXT: beq .LBB15_2382; CHECK-NEXT: @ %bb.1: @ %select.false.sink383; CHECK-NEXT: vmov r0, r1, d2384; CHECK-NEXT: orrs r0, r1385; CHECK-NEXT: mov.w r1, #0386; CHECK-NEXT: csetm r0, eq387; CHECK-NEXT: bfi r1, r0, #0, #8388; CHECK-NEXT: vmov r0, r2, d3389; CHECK-NEXT: b .LBB15_3390; CHECK-NEXT: .LBB15_2: @ %select.true.sink391; CHECK-NEXT: vmov r0, r1, d0392; CHECK-NEXT: orrs r0, r1393; CHECK-NEXT: mov.w r1, #0394; CHECK-NEXT: csetm r0, eq395; CHECK-NEXT: bfi r1, r0, #0, #8396; CHECK-NEXT: vmov r0, r2, d1397; CHECK-NEXT: .LBB15_3: @ %select.end398; CHECK-NEXT: orrs r0, r2399; CHECK-NEXT: csetm r0, eq400; CHECK-NEXT: bfi r1, r0, #8, #8401; CHECK-NEXT: vmsr p0, r1402; CHECK-NEXT: vpsel q0, q0, q1403; CHECK-NEXT: bx lr404entry:405 %c1 = icmp eq <2 x i64> %a, zeroinitializer406 %c2 = icmp eq <2 x i64> %b, zeroinitializer407 %c3 = icmp eq i64 %c, zeroinitializer408 %c4 = select i1 %c3, <2 x i1> %c1, <2 x i1> %c2409 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b410 ret <2 x i64> %s411}412