531 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: cmpeqz_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i32 eq, q1, zr8; CHECK-NEXT: vmrs r0, p09; CHECK-NEXT: vcmp.i32 eq, q0, zr10; CHECK-NEXT: vmrs r1, p011; CHECK-NEXT: eors r0, r112; CHECK-NEXT: vmsr p0, r013; CHECK-NEXT: vpsel q0, q0, q114; CHECK-NEXT: bx lr15entry:16 %c1 = icmp eq <4 x i32> %a, zeroinitializer17 %c2 = icmp eq <4 x i32> %b, zeroinitializer18 %o = xor <4 x i1> %c1, %c219 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b20 ret <4 x i32> %s21}22 23define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {24; CHECK-LABEL: cmpnez_v4i1:25; CHECK: @ %bb.0: @ %entry26; CHECK-NEXT: vcmp.i32 ne, q1, zr27; CHECK-NEXT: vmrs r0, p028; CHECK-NEXT: vcmp.i32 eq, q0, zr29; CHECK-NEXT: vmrs r1, p030; CHECK-NEXT: eors r0, r131; CHECK-NEXT: vmsr p0, r032; CHECK-NEXT: vpsel q0, q0, q133; CHECK-NEXT: bx lr34entry:35 %c1 = icmp eq <4 x i32> %a, zeroinitializer36 %c2 = icmp ne <4 x i32> %b, zeroinitializer37 %o = xor <4 x i1> %c1, %c238 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b39 ret <4 x i32> %s40}41 42define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {43; CHECK-LABEL: cmpsltz_v4i1:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: vcmp.s32 lt, q1, zr46; CHECK-NEXT: vmrs r0, p047; CHECK-NEXT: vcmp.i32 eq, q0, zr48; CHECK-NEXT: vmrs r1, p049; CHECK-NEXT: eors r0, r150; CHECK-NEXT: vmsr p0, r051; CHECK-NEXT: vpsel q0, q0, q152; CHECK-NEXT: bx lr53entry:54 %c1 = icmp eq <4 x i32> %a, zeroinitializer55 %c2 = icmp slt <4 x i32> %b, zeroinitializer56 %o = xor <4 x i1> %c1, %c257 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b58 ret <4 x i32> %s59}60 61define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {62; CHECK-LABEL: cmpsgtz_v4i1:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: vcmp.s32 gt, q1, zr65; CHECK-NEXT: vmrs r0, p066; CHECK-NEXT: vcmp.i32 eq, q0, zr67; CHECK-NEXT: vmrs r1, p068; CHECK-NEXT: eors r0, r169; CHECK-NEXT: vmsr p0, r070; CHECK-NEXT: vpsel q0, q0, q171; CHECK-NEXT: bx lr72entry:73 %c1 = icmp eq <4 x i32> %a, zeroinitializer74 %c2 = icmp sgt <4 x i32> %b, zeroinitializer75 %o = xor <4 x i1> %c1, %c276 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b77 ret <4 x i32> %s78}79 80define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {81; CHECK-LABEL: cmpslez_v4i1:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vcmp.s32 le, q1, zr84; CHECK-NEXT: vmrs r0, p085; CHECK-NEXT: vcmp.i32 eq, q0, zr86; CHECK-NEXT: vmrs r1, p087; CHECK-NEXT: eors r0, r188; CHECK-NEXT: vmsr p0, r089; CHECK-NEXT: vpsel q0, q0, q190; CHECK-NEXT: bx lr91entry:92 %c1 = icmp eq <4 x i32> %a, zeroinitializer93 %c2 = icmp sle <4 x i32> %b, zeroinitializer94 %o = xor <4 x i1> %c1, %c295 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b96 ret <4 x i32> %s97}98 99define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {100; CHECK-LABEL: cmpsgez_v4i1:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: vcmp.s32 ge, q1, zr103; CHECK-NEXT: vmrs r0, p0104; CHECK-NEXT: vcmp.i32 eq, q0, zr105; CHECK-NEXT: vmrs r1, p0106; CHECK-NEXT: eors r0, r1107; CHECK-NEXT: vmsr p0, r0108; CHECK-NEXT: vpsel q0, q0, q1109; CHECK-NEXT: bx lr110entry:111 %c1 = icmp eq <4 x i32> %a, zeroinitializer112 %c2 = icmp sge <4 x i32> %b, zeroinitializer113 %o = xor <4 x i1> %c1, %c2114 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b115 ret <4 x i32> %s116}117 118define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {119; CHECK-LABEL: cmpultz_v4i1:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: vcmp.i32 eq, q0, zr122; CHECK-NEXT: vpsel q0, q0, q1123; CHECK-NEXT: bx lr124entry:125 %c1 = icmp eq <4 x i32> %a, zeroinitializer126 %c2 = icmp ult <4 x i32> %b, zeroinitializer127 %o = xor <4 x i1> %c1, %c2128 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b129 ret <4 x i32> %s130}131 132define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {133; CHECK-LABEL: cmpugtz_v4i1:134; CHECK: @ %bb.0: @ %entry135; CHECK-NEXT: vcmp.i32 ne, q1, zr136; CHECK-NEXT: vmrs r0, p0137; CHECK-NEXT: vcmp.i32 eq, q0, zr138; CHECK-NEXT: vmrs r1, p0139; CHECK-NEXT: eors r0, r1140; CHECK-NEXT: vmsr p0, r0141; CHECK-NEXT: vpsel q0, q0, q1142; CHECK-NEXT: bx lr143entry:144 %c1 = icmp eq <4 x i32> %a, zeroinitializer145 %c2 = icmp ugt <4 x i32> %b, zeroinitializer146 %o = xor <4 x i1> %c1, %c2147 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b148 ret <4 x i32> %s149}150 151define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {152; CHECK-LABEL: cmpulez_v4i1:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vmov.i32 q2, #0x0155; CHECK-NEXT: vcmp.u32 cs, q2, q1156; CHECK-NEXT: vmrs r0, p0157; CHECK-NEXT: vcmp.i32 eq, q0, zr158; CHECK-NEXT: vmrs r1, p0159; CHECK-NEXT: eors r0, r1160; CHECK-NEXT: vmsr p0, r0161; CHECK-NEXT: vpsel q0, q0, q1162; CHECK-NEXT: bx lr163entry:164 %c1 = icmp eq <4 x i32> %a, zeroinitializer165 %c2 = icmp ule <4 x i32> %b, zeroinitializer166 %o = xor <4 x i1> %c1, %c2167 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b168 ret <4 x i32> %s169}170 171define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {172; CHECK-LABEL: cmpugez_v4i1:173; CHECK: @ %bb.0: @ %entry174; CHECK-NEXT: vcmp.i32 eq, q0, zr175; CHECK-NEXT: vpsel q0, q1, q0176; CHECK-NEXT: bx lr177entry:178 %c1 = icmp eq <4 x i32> %a, zeroinitializer179 %c2 = icmp uge <4 x i32> %b, zeroinitializer180 %o = xor <4 x i1> %c1, %c2181 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b182 ret <4 x i32> %s183}184 185 186 187define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {188; CHECK-LABEL: cmpeq_v4i1:189; CHECK: @ %bb.0: @ %entry190; CHECK-NEXT: vcmp.i32 eq, q1, q2191; CHECK-NEXT: vmrs r0, p0192; CHECK-NEXT: vcmp.i32 eq, q0, zr193; CHECK-NEXT: vmrs r1, p0194; CHECK-NEXT: eors r0, r1195; CHECK-NEXT: vmsr p0, r0196; CHECK-NEXT: vpsel q0, q0, q1197; CHECK-NEXT: bx lr198entry:199 %c1 = icmp eq <4 x i32> %a, zeroinitializer200 %c2 = icmp eq <4 x i32> %b, %c201 %o = xor <4 x i1> %c1, %c2202 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b203 ret <4 x i32> %s204}205 206define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {207; CHECK-LABEL: cmpne_v4i1:208; CHECK: @ %bb.0: @ %entry209; CHECK-NEXT: vcmp.i32 ne, q1, q2210; CHECK-NEXT: vmrs r0, p0211; CHECK-NEXT: vcmp.i32 eq, q0, zr212; CHECK-NEXT: vmrs r1, p0213; CHECK-NEXT: eors r0, r1214; CHECK-NEXT: vmsr p0, r0215; CHECK-NEXT: vpsel q0, q0, q1216; CHECK-NEXT: bx lr217entry:218 %c1 = icmp eq <4 x i32> %a, zeroinitializer219 %c2 = icmp ne <4 x i32> %b, %c220 %o = xor <4 x i1> %c1, %c2221 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b222 ret <4 x i32> %s223}224 225define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {226; CHECK-LABEL: cmpslt_v4i1:227; CHECK: @ %bb.0: @ %entry228; CHECK-NEXT: vcmp.s32 gt, q2, q1229; CHECK-NEXT: vmrs r0, p0230; CHECK-NEXT: vcmp.i32 eq, q0, zr231; CHECK-NEXT: vmrs r1, p0232; CHECK-NEXT: eors r0, r1233; CHECK-NEXT: vmsr p0, r0234; CHECK-NEXT: vpsel q0, q0, q1235; CHECK-NEXT: bx lr236entry:237 %c1 = icmp eq <4 x i32> %a, zeroinitializer238 %c2 = icmp slt <4 x i32> %b, %c239 %o = xor <4 x i1> %c1, %c2240 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b241 ret <4 x i32> %s242}243 244define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {245; CHECK-LABEL: cmpsgt_v4i1:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vcmp.s32 gt, q1, q2248; CHECK-NEXT: vmrs r0, p0249; CHECK-NEXT: vcmp.i32 eq, q0, zr250; CHECK-NEXT: vmrs r1, p0251; CHECK-NEXT: eors r0, r1252; CHECK-NEXT: vmsr p0, r0253; CHECK-NEXT: vpsel q0, q0, q1254; CHECK-NEXT: bx lr255entry:256 %c1 = icmp eq <4 x i32> %a, zeroinitializer257 %c2 = icmp sgt <4 x i32> %b, %c258 %o = xor <4 x i1> %c1, %c2259 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b260 ret <4 x i32> %s261}262 263define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {264; CHECK-LABEL: cmpsle_v4i1:265; CHECK: @ %bb.0: @ %entry266; CHECK-NEXT: vcmp.s32 ge, q2, q1267; CHECK-NEXT: vmrs r0, p0268; CHECK-NEXT: vcmp.i32 eq, q0, zr269; CHECK-NEXT: vmrs r1, p0270; CHECK-NEXT: eors r0, r1271; CHECK-NEXT: vmsr p0, r0272; CHECK-NEXT: vpsel q0, q0, q1273; CHECK-NEXT: bx lr274entry:275 %c1 = icmp eq <4 x i32> %a, zeroinitializer276 %c2 = icmp sle <4 x i32> %b, %c277 %o = xor <4 x i1> %c1, %c2278 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b279 ret <4 x i32> %s280}281 282define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {283; CHECK-LABEL: cmpsge_v4i1:284; CHECK: @ %bb.0: @ %entry285; CHECK-NEXT: vcmp.s32 ge, q1, q2286; CHECK-NEXT: vmrs r0, p0287; CHECK-NEXT: vcmp.i32 eq, q0, zr288; CHECK-NEXT: vmrs r1, p0289; CHECK-NEXT: eors r0, r1290; CHECK-NEXT: vmsr p0, r0291; CHECK-NEXT: vpsel q0, q0, q1292; CHECK-NEXT: bx lr293entry:294 %c1 = icmp eq <4 x i32> %a, zeroinitializer295 %c2 = icmp sge <4 x i32> %b, %c296 %o = xor <4 x i1> %c1, %c2297 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b298 ret <4 x i32> %s299}300 301define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {302; CHECK-LABEL: cmpult_v4i1:303; CHECK: @ %bb.0: @ %entry304; CHECK-NEXT: vcmp.u32 hi, q2, q1305; CHECK-NEXT: vmrs r0, p0306; CHECK-NEXT: vcmp.i32 eq, q0, zr307; CHECK-NEXT: vmrs r1, p0308; CHECK-NEXT: eors r0, r1309; CHECK-NEXT: vmsr p0, r0310; CHECK-NEXT: vpsel q0, q0, q1311; CHECK-NEXT: bx lr312entry:313 %c1 = icmp eq <4 x i32> %a, zeroinitializer314 %c2 = icmp ult <4 x i32> %b, %c315 %o = xor <4 x i1> %c1, %c2316 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b317 ret <4 x i32> %s318}319 320define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {321; CHECK-LABEL: cmpugt_v4i1:322; CHECK: @ %bb.0: @ %entry323; CHECK-NEXT: vcmp.u32 hi, q1, q2324; CHECK-NEXT: vmrs r0, p0325; CHECK-NEXT: vcmp.i32 eq, q0, zr326; CHECK-NEXT: vmrs r1, p0327; CHECK-NEXT: eors r0, r1328; CHECK-NEXT: vmsr p0, r0329; CHECK-NEXT: vpsel q0, q0, q1330; CHECK-NEXT: bx lr331entry:332 %c1 = icmp eq <4 x i32> %a, zeroinitializer333 %c2 = icmp ugt <4 x i32> %b, %c334 %o = xor <4 x i1> %c1, %c2335 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b336 ret <4 x i32> %s337}338 339define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {340; CHECK-LABEL: cmpule_v4i1:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: vcmp.u32 cs, q2, q1343; CHECK-NEXT: vmrs r0, p0344; CHECK-NEXT: vcmp.i32 eq, q0, zr345; CHECK-NEXT: vmrs r1, p0346; CHECK-NEXT: eors r0, r1347; CHECK-NEXT: vmsr p0, r0348; CHECK-NEXT: vpsel q0, q0, q1349; CHECK-NEXT: bx lr350entry:351 %c1 = icmp eq <4 x i32> %a, zeroinitializer352 %c2 = icmp ule <4 x i32> %b, %c353 %o = xor <4 x i1> %c1, %c2354 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b355 ret <4 x i32> %s356}357 358define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {359; CHECK-LABEL: cmpuge_v4i1:360; CHECK: @ %bb.0: @ %entry361; CHECK-NEXT: vcmp.u32 cs, q1, q2362; CHECK-NEXT: vmrs r0, p0363; CHECK-NEXT: vcmp.i32 eq, q0, zr364; CHECK-NEXT: vmrs r1, p0365; CHECK-NEXT: eors r0, r1366; CHECK-NEXT: vmsr p0, r0367; CHECK-NEXT: vpsel q0, q0, q1368; CHECK-NEXT: bx lr369entry:370 %c1 = icmp eq <4 x i32> %a, zeroinitializer371 %c2 = icmp uge <4 x i32> %b, %c372 %o = xor <4 x i1> %c1, %c2373 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b374 ret <4 x i32> %s375}376 377 378 379 380define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {381; CHECK-LABEL: cmpeqz_v8i1:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: vcmp.i16 eq, q1, zr384; CHECK-NEXT: vmrs r0, p0385; CHECK-NEXT: vcmp.i16 eq, q0, zr386; CHECK-NEXT: vmrs r1, p0387; CHECK-NEXT: eors r0, r1388; CHECK-NEXT: vmsr p0, r0389; CHECK-NEXT: vpsel q0, q0, q1390; CHECK-NEXT: bx lr391entry:392 %c1 = icmp eq <8 x i16> %a, zeroinitializer393 %c2 = icmp eq <8 x i16> %b, zeroinitializer394 %o = xor <8 x i1> %c1, %c2395 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b396 ret <8 x i16> %s397}398 399define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {400; CHECK-LABEL: cmpeq_v8i1:401; CHECK: @ %bb.0: @ %entry402; CHECK-NEXT: vcmp.i16 eq, q1, q2403; CHECK-NEXT: vmrs r0, p0404; CHECK-NEXT: vcmp.i16 eq, q0, zr405; CHECK-NEXT: vmrs r1, p0406; CHECK-NEXT: eors r0, r1407; CHECK-NEXT: vmsr p0, r0408; CHECK-NEXT: vpsel q0, q0, q1409; CHECK-NEXT: bx lr410entry:411 %c1 = icmp eq <8 x i16> %a, zeroinitializer412 %c2 = icmp eq <8 x i16> %b, %c413 %o = xor <8 x i1> %c1, %c2414 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b415 ret <8 x i16> %s416}417 418 419define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {420; CHECK-LABEL: cmpeqz_v16i1:421; CHECK: @ %bb.0: @ %entry422; CHECK-NEXT: vcmp.i8 eq, q1, zr423; CHECK-NEXT: vmrs r0, p0424; CHECK-NEXT: vcmp.i8 eq, q0, zr425; CHECK-NEXT: vmrs r1, p0426; CHECK-NEXT: eors r0, r1427; CHECK-NEXT: vmsr p0, r0428; CHECK-NEXT: vpsel q0, q0, q1429; CHECK-NEXT: bx lr430entry:431 %c1 = icmp eq <16 x i8> %a, zeroinitializer432 %c2 = icmp eq <16 x i8> %b, zeroinitializer433 %o = xor <16 x i1> %c1, %c2434 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b435 ret <16 x i8> %s436}437 438define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {439; CHECK-LABEL: cmpeq_v16i1:440; CHECK: @ %bb.0: @ %entry441; CHECK-NEXT: vcmp.i8 eq, q1, q2442; CHECK-NEXT: vmrs r0, p0443; CHECK-NEXT: vcmp.i8 eq, q0, zr444; CHECK-NEXT: vmrs r1, p0445; CHECK-NEXT: eors r0, r1446; CHECK-NEXT: vmsr p0, r0447; CHECK-NEXT: vpsel q0, q0, q1448; CHECK-NEXT: bx lr449entry:450 %c1 = icmp eq <16 x i8> %a, zeroinitializer451 %c2 = icmp eq <16 x i8> %b, %c452 %o = xor <16 x i1> %c1, %c2453 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b454 ret <16 x i8> %s455}456 457 458define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {459; CHECK-LABEL: cmpeqz_v2i1:460; CHECK: @ %bb.0: @ %entry461; CHECK-NEXT: vmov r0, r1, d2462; CHECK-NEXT: orrs r0, r1463; CHECK-NEXT: vmov r1, r2, d0464; CHECK-NEXT: cset r0, eq465; CHECK-NEXT: orrs r1, r2466; CHECK-NEXT: it eq467; CHECK-NEXT: eoreq r0, r0, #1468; CHECK-NEXT: rsbs r0, r0, #0469; CHECK-NEXT: movs r1, #0470; CHECK-NEXT: bfi r1, r0, #0, #8471; CHECK-NEXT: vmov r0, r2, d3472; CHECK-NEXT: orrs r0, r2473; CHECK-NEXT: vmov r2, r3, d1474; CHECK-NEXT: cset r0, eq475; CHECK-NEXT: orrs r2, r3476; CHECK-NEXT: it eq477; CHECK-NEXT: eoreq r0, r0, #1478; CHECK-NEXT: rsbs r0, r0, #0479; CHECK-NEXT: bfi r1, r0, #8, #8480; CHECK-NEXT: vmsr p0, r1481; CHECK-NEXT: vpsel q0, q0, q1482; CHECK-NEXT: bx lr483entry:484 %c1 = icmp eq <2 x i64> %a, zeroinitializer485 %c2 = icmp eq <2 x i64> %b, zeroinitializer486 %o = xor <2 x i1> %c1, %c2487 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b488 ret <2 x i64> %s489}490 491define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {492; CHECK-LABEL: cmpeq_v2i1:493; CHECK: @ %bb.0: @ %entry494; CHECK-NEXT: vmov r0, r1, d4495; CHECK-NEXT: vmov r2, r3, d2496; CHECK-NEXT: eors r1, r3497; CHECK-NEXT: eors r0, r2498; CHECK-NEXT: orrs r0, r1499; CHECK-NEXT: vmov r1, r2, d0500; CHECK-NEXT: cset r0, eq501; CHECK-NEXT: orrs r1, r2502; CHECK-NEXT: it eq503; CHECK-NEXT: eoreq r0, r0, #1504; CHECK-NEXT: rsbs r0, r0, #0505; CHECK-NEXT: movs r1, #0506; CHECK-NEXT: bfi r1, r0, #0, #8507; CHECK-NEXT: vmov r12, r2, d5508; CHECK-NEXT: vmov r3, r0, d3509; CHECK-NEXT: eors r0, r2510; CHECK-NEXT: eor.w r2, r3, r12511; CHECK-NEXT: orrs r0, r2512; CHECK-NEXT: vmov r2, r3, d1513; CHECK-NEXT: cset r0, eq514; CHECK-NEXT: orrs r2, r3515; CHECK-NEXT: it eq516; CHECK-NEXT: eoreq r0, r0, #1517; CHECK-NEXT: rsbs r0, r0, #0518; CHECK-NEXT: bfi r1, r0, #8, #8519; CHECK-NEXT: vmsr p0, r1520; CHECK-NEXT: vpsel q0, q0, q1521; CHECK-NEXT: bx lr522entry:523 %c1 = icmp eq <2 x i64> %a, zeroinitializer524 %c2 = icmp eq <2 x i64> %b, %c525 %o = xor <2 x i1> %c1, %c2526 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b527 ret <2 x i64> %s528}529 530 531