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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @sadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: sadd_int8_t:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqadd.s8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @sadd_int16_t(<8 x i16> %src1, <8 x i16> %src2) {15; CHECK-LABEL: sadd_int16_t:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vqadd.s16 q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @sadd_int32_t(<4 x i32> %src1, <4 x i32> %src2) {25; CHECK-LABEL: sadd_int32_t:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vqadd.s32 q0, q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {35; CHECK-LABEL: sadd_int64_t:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: .save {r4, r5, r7, lr}38; CHECK-NEXT: push {r4, r5, r7, lr}39; CHECK-NEXT: vmov r0, r1, d240; CHECK-NEXT: vmov r2, r3, d041; CHECK-NEXT: adds.w r12, r2, r042; CHECK-NEXT: vmov r0, r4, d143; CHECK-NEXT: adc.w lr, r3, r144; CHECK-NEXT: subs.w r2, r12, r245; CHECK-NEXT: sbcs.w r2, lr, r346; CHECK-NEXT: cset r2, lt47; CHECK-NEXT: cmp r1, #048; CHECK-NEXT: it mi49; CHECK-NEXT: eormi r2, r2, #150; CHECK-NEXT: rsbs r1, r2, #051; CHECK-NEXT: movs r2, #052; CHECK-NEXT: bfi r2, r1, #0, #853; CHECK-NEXT: vmov r1, r3, d354; CHECK-NEXT: adds r1, r1, r055; CHECK-NEXT: adc.w r5, r4, r356; CHECK-NEXT: subs r0, r1, r057; CHECK-NEXT: sbcs.w r0, r5, r458; CHECK-NEXT: vmov q0[2], q0[0], r12, r159; CHECK-NEXT: cset r0, lt60; CHECK-NEXT: cmp r3, #061; CHECK-NEXT: it mi62; CHECK-NEXT: eormi r0, r0, #163; CHECK-NEXT: asr.w r1, lr, #3164; CHECK-NEXT: rsbs r0, r0, #065; CHECK-NEXT: vmov q0[3], q0[1], lr, r566; CHECK-NEXT: bfi r2, r0, #8, #867; CHECK-NEXT: asrs r0, r5, #3168; CHECK-NEXT: vmov q1[2], q1[0], r1, r069; CHECK-NEXT: vmsr p0, r270; CHECK-NEXT: vmov q1[3], q1[1], r1, r071; CHECK-NEXT: adr r0, .LCPI3_072; CHECK-NEXT: vldrw.u32 q2, [r0]73; CHECK-NEXT: veor q1, q1, q274; CHECK-NEXT: vpsel q0, q1, q075; CHECK-NEXT: pop {r4, r5, r7, pc}76; CHECK-NEXT: .p2align 477; CHECK-NEXT: @ %bb.1:78; CHECK-NEXT: .LCPI3_0:79; CHECK-NEXT: .long 0 @ 0x080; CHECK-NEXT: .long 2147483648 @ 0x8000000081; CHECK-NEXT: .long 0 @ 0x082; CHECK-NEXT: .long 2147483648 @ 0x8000000083entry:84 %0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)85 ret <2 x i64> %086}87 88define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {89; CHECK-LABEL: uadd_int8_t:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vqadd.u8 q0, q0, q192; CHECK-NEXT: bx lr93entry:94 %0 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)95 ret <16 x i8> %096}97 98define arm_aapcs_vfpcc <8 x i16> @uadd_int16_t(<8 x i16> %src1, <8 x i16> %src2) {99; CHECK-LABEL: uadd_int16_t:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vqadd.u16 q0, q0, q1102; CHECK-NEXT: bx lr103entry:104 %0 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)105 ret <8 x i16> %0106}107 108define arm_aapcs_vfpcc <4 x i32> @uadd_int32_t(<4 x i32> %src1, <4 x i32> %src2) {109; CHECK-LABEL: uadd_int32_t:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vqadd.u32 q0, q0, q1112; CHECK-NEXT: bx lr113entry:114 %0 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)115 ret <4 x i32> %0116}117 118define arm_aapcs_vfpcc <2 x i64> @uadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {119; CHECK-LABEL: uadd_int64_t:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: .save {r4, r5, r7, lr}122; CHECK-NEXT: push {r4, r5, r7, lr}123; CHECK-NEXT: vmov r0, r1, d3124; CHECK-NEXT: vmov r2, r3, d1125; CHECK-NEXT: adds r5, r2, r0126; CHECK-NEXT: adc.w lr, r3, r1127; CHECK-NEXT: subs r2, r5, r2128; CHECK-NEXT: sbcs.w r2, lr, r3129; CHECK-NEXT: vmov r3, r12, d2130; CHECK-NEXT: vmov r1, r4, d0131; CHECK-NEXT: csetm r2, lo132; CHECK-NEXT: adds r3, r3, r1133; CHECK-NEXT: adc.w r0, r4, r12134; CHECK-NEXT: subs r1, r3, r1135; CHECK-NEXT: sbcs.w r1, r0, r4136; CHECK-NEXT: vmov q1[2], q1[0], r3, r5137; CHECK-NEXT: csetm r1, lo138; CHECK-NEXT: vmov q1[3], q1[1], r0, lr139; CHECK-NEXT: vmov q0[2], q0[0], r1, r2140; CHECK-NEXT: vmov q0[3], q0[1], r1, r2141; CHECK-NEXT: vorr q0, q1, q0142; CHECK-NEXT: pop {r4, r5, r7, pc}143entry:144 %0 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)145 ret <2 x i64> %0146}147 148 149define arm_aapcs_vfpcc <16 x i8> @ssub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {150; CHECK-LABEL: ssub_int8_t:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vqsub.s8 q0, q0, q1153; CHECK-NEXT: bx lr154entry:155 %0 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)156 ret <16 x i8> %0157}158 159define arm_aapcs_vfpcc <8 x i16> @ssub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {160; CHECK-LABEL: ssub_int16_t:161; CHECK: @ %bb.0: @ %entry162; CHECK-NEXT: vqsub.s16 q0, q0, q1163; CHECK-NEXT: bx lr164entry:165 %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)166 ret <8 x i16> %0167}168 169define arm_aapcs_vfpcc <4 x i32> @ssub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {170; CHECK-LABEL: ssub_int32_t:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vqsub.s32 q0, q0, q1173; CHECK-NEXT: bx lr174entry:175 %0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)176 ret <4 x i32> %0177}178 179define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {180; CHECK-LABEL: ssub_int64_t:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: .save {r4, r5, r6, r7, lr}183; CHECK-NEXT: push {r4, r5, r6, r7, lr}184; CHECK-NEXT: vmov r2, r3, d2185; CHECK-NEXT: vmov r1, r0, d0186; CHECK-NEXT: vmov r4, r5, d1187; CHECK-NEXT: subs.w r12, r1, r2188; CHECK-NEXT: sbc.w lr, r0, r3189; CHECK-NEXT: subs.w r1, r12, r1190; CHECK-NEXT: sbcs.w r0, lr, r0191; CHECK-NEXT: mov.w r1, #0192; CHECK-NEXT: cset r0, lt193; CHECK-NEXT: rsbs r2, r2, #0194; CHECK-NEXT: sbcs.w r2, r1, r3195; CHECK-NEXT: it lt196; CHECK-NEXT: eorlt r0, r0, #1197; CHECK-NEXT: vmov r2, r3, d3198; CHECK-NEXT: rsbs r0, r0, #0199; CHECK-NEXT: subs r6, r4, r2200; CHECK-NEXT: sbc.w r7, r5, r3201; CHECK-NEXT: subs r4, r6, r4202; CHECK-NEXT: sbcs.w r4, r7, r5203; CHECK-NEXT: vmov q0[2], q0[0], r12, r6204; CHECK-NEXT: cset r4, lt205; CHECK-NEXT: rsbs r2, r2, #0206; CHECK-NEXT: sbcs.w r2, r1, r3207; CHECK-NEXT: bfi r1, r0, #0, #8208; CHECK-NEXT: it lt209; CHECK-NEXT: eorlt r4, r4, #1210; CHECK-NEXT: rsbs r0, r4, #0211; CHECK-NEXT: bfi r1, r0, #8, #8212; CHECK-NEXT: asrs r0, r7, #31213; CHECK-NEXT: vmsr p0, r1214; CHECK-NEXT: asr.w r1, lr, #31215; CHECK-NEXT: vmov q1[2], q1[0], r1, r0216; CHECK-NEXT: vmov q0[3], q0[1], lr, r7217; CHECK-NEXT: vmov q1[3], q1[1], r1, r0218; CHECK-NEXT: adr r0, .LCPI11_0219; CHECK-NEXT: vldrw.u32 q2, [r0]220; CHECK-NEXT: veor q1, q1, q2221; CHECK-NEXT: vpsel q0, q1, q0222; CHECK-NEXT: pop {r4, r5, r6, r7, pc}223; CHECK-NEXT: .p2align 4224; CHECK-NEXT: @ %bb.1:225; CHECK-NEXT: .LCPI11_0:226; CHECK-NEXT: .long 0 @ 0x0227; CHECK-NEXT: .long 2147483648 @ 0x80000000228; CHECK-NEXT: .long 0 @ 0x0229; CHECK-NEXT: .long 2147483648 @ 0x80000000230entry:231 %0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)232 ret <2 x i64> %0233}234 235define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {236; CHECK-LABEL: usub_int8_t:237; CHECK: @ %bb.0: @ %entry238; CHECK-NEXT: vqsub.u8 q0, q0, q1239; CHECK-NEXT: bx lr240entry:241 %0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)242 ret <16 x i8> %0243}244 245define arm_aapcs_vfpcc <8 x i16> @usub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {246; CHECK-LABEL: usub_int16_t:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vqsub.u16 q0, q0, q1249; CHECK-NEXT: bx lr250entry:251 %0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)252 ret <8 x i16> %0253}254 255define arm_aapcs_vfpcc <4 x i32> @usub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {256; CHECK-LABEL: usub_int32_t:257; CHECK: @ %bb.0: @ %entry258; CHECK-NEXT: vqsub.u32 q0, q0, q1259; CHECK-NEXT: bx lr260entry:261 %0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)262 ret <4 x i32> %0263}264 265define arm_aapcs_vfpcc <2 x i64> @usub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {266; CHECK-LABEL: usub_int64_t:267; CHECK: @ %bb.0: @ %entry268; CHECK-NEXT: .save {r4, r5, r7, lr}269; CHECK-NEXT: push {r4, r5, r7, lr}270; CHECK-NEXT: vmov r0, r1, d3271; CHECK-NEXT: vmov r2, r3, d1272; CHECK-NEXT: subs r5, r2, r0273; CHECK-NEXT: sbc.w lr, r3, r1274; CHECK-NEXT: subs r2, r2, r5275; CHECK-NEXT: sbcs.w r2, r3, lr276; CHECK-NEXT: vmov r3, r12, d2277; CHECK-NEXT: vmov r1, r4, d0278; CHECK-NEXT: csetm r2, lo279; CHECK-NEXT: subs r3, r1, r3280; CHECK-NEXT: sbc.w r0, r4, r12281; CHECK-NEXT: subs r1, r1, r3282; CHECK-NEXT: sbcs.w r1, r4, r0283; CHECK-NEXT: vmov q1[2], q1[0], r3, r5284; CHECK-NEXT: csetm r1, lo285; CHECK-NEXT: vmov q1[3], q1[1], r0, lr286; CHECK-NEXT: vmov q0[2], q0[0], r1, r2287; CHECK-NEXT: vmov q0[3], q0[1], r1, r2288; CHECK-NEXT: vbic q0, q1, q0289; CHECK-NEXT: pop {r4, r5, r7, pc}290entry:291 %0 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)292 ret <2 x i64> %0293}294 295 296declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)297declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)298declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)299declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)300declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)301declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)302declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)303declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)304declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)305declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)306declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)307declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)308declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)309declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)310declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)311declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)312