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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4; VLDRB.u16 Qd, [base, offs]5define arm_aapcs_vfpcc void @ext_unscaled_i8_i16(ptr %base, ptr %offptr, <8 x i16> %input) {6; CHECK-LABEL: ext_unscaled_i8_i16:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vldrh.u16 q1, [r1]9; CHECK-NEXT: vstrb.16 q0, [r0, q1]10; CHECK-NEXT: bx lr11entry:12 %offs = load <8 x i16>, ptr %offptr, align 213 %offs.zext = zext <8 x i16> %offs to <8 x i32>14 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext15 %t = trunc <8 x i16> %input to <8 x i8>16 call void @llvm.masked.scatter.v8i8(<8 x i8> %t, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)17 ret void18}19 20; VLDRB.u16 Qd, [base, offs]21define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i16_i8(ptr %base, ptr %offptr, <8 x i16> %input) {22; CHECK-LABEL: trunc_unsigned_unscaled_i16_i8:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vldrb.u16 q1, [r1]25; CHECK-NEXT: vstrb.16 q0, [r0, q1]26; CHECK-NEXT: bx lr27entry:28 %offs = load <8 x i8>, ptr %offptr, align 129 %offs.zext = zext <8 x i8> %offs to <8 x i32>30 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext31 %input.trunc = trunc <8 x i16> %input to <8 x i8>32 call void @llvm.masked.scatter.v8i8(<8 x i8> %input.trunc, <8 x ptr> %byte_ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)33 ret void34}35 36; VLDRH.16 Qd, [base, offs]37define arm_aapcs_vfpcc void @unscaled_i16_i16(ptr %base, ptr %offptr, <8 x i16> %input) {38; CHECK-LABEL: unscaled_i16_i16:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vldrh.u16 q1, [r1]41; CHECK-NEXT: vstrh.16 q0, [r0, q1]42; CHECK-NEXT: bx lr43entry:44 %offs = load <8 x i16>, ptr %offptr, align 245 %offs.zext = zext <8 x i16> %offs to <8 x i32>46 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext47 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>48 call void @llvm.masked.scatter.v8i16(<8 x i16> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)49 ret void50}51 52; VLDRH.s16 Qd, [base, offs]53define arm_aapcs_vfpcc void @unscaled_v8f16_i16(ptr %base, ptr %offptr, <8 x half> %input) {54; CHECK-LABEL: unscaled_v8f16_i16:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vldrh.u16 q1, [r1]57; CHECK-NEXT: vstrh.16 q0, [r0, q1]58; CHECK-NEXT: bx lr59entry:60 %offs = load <8 x i16>, ptr %offptr, align 261 %offs.zext = zext <8 x i16> %offs to <8 x i32>62 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext63 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>64 call void @llvm.masked.scatter.v8f16(<8 x half> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)65 ret void66}67 68; Expand - sext offsets69define arm_aapcs_vfpcc void @unscaled_v8i16_sext(ptr %base, ptr %offptr, <8 x i16> %input) {70; CHECK-LABEL: unscaled_v8i16_sext:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: .save {r4, r5, r6, lr}73; CHECK-NEXT: push {r4, r5, r6, lr}74; CHECK-NEXT: vldrh.s32 q1, [r1]75; CHECK-NEXT: vmov.u16 r6, q0[0]76; CHECK-NEXT: vadd.i32 q1, q1, r077; CHECK-NEXT: vmov r2, r3, d278; CHECK-NEXT: vmov r12, lr, d379; CHECK-NEXT: vldrh.s32 q1, [r1, #8]80; CHECK-NEXT: vadd.i32 q1, q1, r081; CHECK-NEXT: vmov r0, r1, d282; CHECK-NEXT: vmov r4, r5, d383; CHECK-NEXT: strh r6, [r2]84; CHECK-NEXT: vmov.u16 r2, q0[1]85; CHECK-NEXT: strh r2, [r3]86; CHECK-NEXT: vmov.u16 r2, q0[2]87; CHECK-NEXT: strh.w r2, [r12]88; CHECK-NEXT: vmov.u16 r2, q0[3]89; CHECK-NEXT: strh.w r2, [lr]90; CHECK-NEXT: vmov.u16 r2, q0[4]91; CHECK-NEXT: strh r2, [r0]92; CHECK-NEXT: vmov.u16 r0, q0[5]93; CHECK-NEXT: strh r0, [r1]94; CHECK-NEXT: vmov.u16 r0, q0[6]95; CHECK-NEXT: strh r0, [r4]96; CHECK-NEXT: vmov.u16 r0, q0[7]97; CHECK-NEXT: strh r0, [r5]98; CHECK-NEXT: pop {r4, r5, r6, pc}99entry:100 %offs = load <8 x i16>, ptr %offptr, align 2101 %offs.sext = sext <8 x i16> %offs to <8 x i32>102 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.sext103 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>104 call void @llvm.masked.scatter.v8i16(<8 x i16> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)105 ret void106}107 108; Expand - sext offsets109define arm_aapcs_vfpcc void @unscaled_v8f16_sext(ptr %base, ptr %offptr, <8 x half> %input) {110; CHECK-LABEL: unscaled_v8f16_sext:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: vldrh.s32 q2, [r1]113; CHECK-NEXT: vldrh.s32 q1, [r1, #8]114; CHECK-NEXT: vadd.i32 q2, q2, r0115; CHECK-NEXT: vadd.i32 q1, q1, r0116; CHECK-NEXT: vmov r1, r2, d4117; CHECK-NEXT: vstr.16 s0, [r1]118; CHECK-NEXT: vmovx.f16 s0, s0119; CHECK-NEXT: vstr.16 s0, [r2]120; CHECK-NEXT: vmov r1, r2, d5121; CHECK-NEXT: vmovx.f16 s0, s1122; CHECK-NEXT: vstr.16 s1, [r1]123; CHECK-NEXT: vstr.16 s0, [r2]124; CHECK-NEXT: vmov r0, r1, d2125; CHECK-NEXT: vmovx.f16 s0, s2126; CHECK-NEXT: vstr.16 s2, [r0]127; CHECK-NEXT: vstr.16 s0, [r1]128; CHECK-NEXT: vmov r0, r1, d3129; CHECK-NEXT: vmovx.f16 s0, s3130; CHECK-NEXT: vstr.16 s3, [r0]131; CHECK-NEXT: vstr.16 s0, [r1]132; CHECK-NEXT: bx lr133entry:134 %offs = load <8 x i16>, ptr %offptr, align 2135 %offs.sext = sext <8 x i16> %offs to <8 x i32>136 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.sext137 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>138 call void @llvm.masked.scatter.v8f16(<8 x half> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)139 ret void140}141 142; Expand - i32 offsets143define arm_aapcs_vfpcc void @unscaled_v8i16_noext(ptr %base, ptr %offptr, <8 x i16> %input) {144; CHECK-LABEL: unscaled_v8i16_noext:145; CHECK: @ %bb.0: @ %entry146; CHECK-NEXT: .save {r4, r5, r6, lr}147; CHECK-NEXT: push {r4, r5, r6, lr}148; CHECK-NEXT: vldrw.u32 q1, [r1]149; CHECK-NEXT: vmov.u16 r6, q0[0]150; CHECK-NEXT: vadd.i32 q1, q1, r0151; CHECK-NEXT: vmov r2, r3, d2152; CHECK-NEXT: vmov r12, lr, d3153; CHECK-NEXT: vldrw.u32 q1, [r1, #16]154; CHECK-NEXT: vadd.i32 q1, q1, r0155; CHECK-NEXT: vmov r0, r1, d2156; CHECK-NEXT: vmov r4, r5, d3157; CHECK-NEXT: strh r6, [r2]158; CHECK-NEXT: vmov.u16 r2, q0[1]159; CHECK-NEXT: strh r2, [r3]160; CHECK-NEXT: vmov.u16 r2, q0[2]161; CHECK-NEXT: strh.w r2, [r12]162; CHECK-NEXT: vmov.u16 r2, q0[3]163; CHECK-NEXT: strh.w r2, [lr]164; CHECK-NEXT: vmov.u16 r2, q0[4]165; CHECK-NEXT: strh r2, [r0]166; CHECK-NEXT: vmov.u16 r0, q0[5]167; CHECK-NEXT: strh r0, [r1]168; CHECK-NEXT: vmov.u16 r0, q0[6]169; CHECK-NEXT: strh r0, [r4]170; CHECK-NEXT: vmov.u16 r0, q0[7]171; CHECK-NEXT: strh r0, [r5]172; CHECK-NEXT: pop {r4, r5, r6, pc}173entry:174 %offs = load <8 x i32>, ptr %offptr, align 4175 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs176 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>177 call void @llvm.masked.scatter.v8i16(<8 x i16> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)178 ret void179}180 181; Expand - i32 offsets182define arm_aapcs_vfpcc void @unscaled_v8f16_noext(ptr %base, ptr %offptr, <8 x half> %input) {183; CHECK-LABEL: unscaled_v8f16_noext:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: vldrw.u32 q2, [r1]186; CHECK-NEXT: vldrw.u32 q1, [r1, #16]187; CHECK-NEXT: vadd.i32 q2, q2, r0188; CHECK-NEXT: vadd.i32 q1, q1, r0189; CHECK-NEXT: vmov r1, r2, d4190; CHECK-NEXT: vstr.16 s0, [r1]191; CHECK-NEXT: vmovx.f16 s0, s0192; CHECK-NEXT: vstr.16 s0, [r2]193; CHECK-NEXT: vmov r1, r2, d5194; CHECK-NEXT: vmovx.f16 s0, s1195; CHECK-NEXT: vstr.16 s1, [r1]196; CHECK-NEXT: vstr.16 s0, [r2]197; CHECK-NEXT: vmov r0, r1, d2198; CHECK-NEXT: vmovx.f16 s0, s2199; CHECK-NEXT: vstr.16 s2, [r0]200; CHECK-NEXT: vstr.16 s0, [r1]201; CHECK-NEXT: vmov r0, r1, d3202; CHECK-NEXT: vmovx.f16 s0, s3203; CHECK-NEXT: vstr.16 s3, [r0]204; CHECK-NEXT: vstr.16 s0, [r1]205; CHECK-NEXT: bx lr206entry:207 %offs = load <8 x i32>, ptr %offptr, align 4208 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs209 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>210 call void @llvm.masked.scatter.v8f16(<8 x half> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)211 ret void212}213 214; VLDRH.16 Qd, [base, zext(offs)]215define arm_aapcs_vfpcc void @unsigned_unscaled_i16_i8(ptr %base, ptr %offptr, <8 x i16> %input) {216; CHECK-LABEL: unsigned_unscaled_i16_i8:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: vldrb.u16 q1, [r1]219; CHECK-NEXT: vstrh.16 q0, [r0, q1]220; CHECK-NEXT: bx lr221entry:222 %offs = load <8 x i8>, ptr %offptr, align 1223 %offs.zext = zext <8 x i8> %offs to <8 x i32>224 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext225 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>226 call void @llvm.masked.scatter.v8i16(<8 x i16> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)227 ret void228}229 230; VLDRH.16 Qd, [base, zext(offs)]231define arm_aapcs_vfpcc void @unsigned_unscaled_f16_i8(ptr %base, ptr %offptr, <8 x half> %input) {232; CHECK-LABEL: unsigned_unscaled_f16_i8:233; CHECK: @ %bb.0: @ %entry234; CHECK-NEXT: vldrb.u16 q1, [r1]235; CHECK-NEXT: vstrh.16 q0, [r0, q1]236; CHECK-NEXT: bx lr237entry:238 %offs = load <8 x i8>, ptr %offptr, align 1239 %offs.zext = zext <8 x i8> %offs to <8 x i32>240 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext241 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>242 call void @llvm.masked.scatter.v8f16(<8 x half> %input, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)243 ret void244}245 246; Expand - sext offsets247define arm_aapcs_vfpcc void @trunc_signed_unscaled_i64_i8(ptr %base, ptr %offptr, <8 x i64> %input) {248; CHECK-LABEL: trunc_signed_unscaled_i64_i8:249; CHECK: @ %bb.0: @ %entry250; CHECK-NEXT: .save {r4, r5, r7, lr}251; CHECK-NEXT: push {r4, r5, r7, lr}252; CHECK-NEXT: .vsave {d8, d9}253; CHECK-NEXT: vpush {d8, d9}254; CHECK-NEXT: vldrb.s32 q4, [r1]255; CHECK-NEXT: vmov r4, s0256; CHECK-NEXT: vadd.i32 q4, q4, r0257; CHECK-NEXT: vmov r2, r3, d8258; CHECK-NEXT: vmov r12, lr, d9259; CHECK-NEXT: vldrb.s32 q4, [r1, #4]260; CHECK-NEXT: vadd.i32 q4, q4, r0261; CHECK-NEXT: vmov r0, r1, d8262; CHECK-NEXT: strh r4, [r2]263; CHECK-NEXT: vmov r2, s2264; CHECK-NEXT: vmov r4, r5, d9265; CHECK-NEXT: strh r2, [r3]266; CHECK-NEXT: vmov r2, s4267; CHECK-NEXT: strh.w r2, [r12]268; CHECK-NEXT: vmov r2, s6269; CHECK-NEXT: strh.w r2, [lr]270; CHECK-NEXT: vmov r2, s8271; CHECK-NEXT: strh r2, [r0]272; CHECK-NEXT: vmov r0, s10273; CHECK-NEXT: strh r0, [r1]274; CHECK-NEXT: vmov r0, s12275; CHECK-NEXT: strh r0, [r4]276; CHECK-NEXT: vmov r0, s14277; CHECK-NEXT: strh r0, [r5]278; CHECK-NEXT: vpop {d8, d9}279; CHECK-NEXT: pop {r4, r5, r7, pc}280entry:281 %offs = load <8 x i8>, ptr %offptr, align 1282 %offs.sext = sext <8 x i8> %offs to <8 x i32>283 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.sext284 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>285 %input.trunc = trunc <8 x i64> %input to <8 x i16>286 call void @llvm.masked.scatter.v8i16(<8 x i16> %input.trunc, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)287 ret void288}289 290define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i64_i8(ptr %base, ptr %offptr, <8 x i64> %input) {291; CHECK-LABEL: trunc_unsigned_unscaled_i64_i8:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: .vsave {d8, d9}294; CHECK-NEXT: vpush {d8, d9}295; CHECK-NEXT: vmov r3, s0296; CHECK-NEXT: vmov.16 q4[0], r3297; CHECK-NEXT: vmov r3, s2298; CHECK-NEXT: vmov.16 q4[1], r3299; CHECK-NEXT: vmov r3, s4300; CHECK-NEXT: vmov.16 q4[2], r3301; CHECK-NEXT: vmov r3, s6302; CHECK-NEXT: vmov.16 q4[3], r3303; CHECK-NEXT: vmov r3, s8304; CHECK-NEXT: vmov.16 q4[4], r3305; CHECK-NEXT: vmov r3, s10306; CHECK-NEXT: vmov.16 q4[5], r3307; CHECK-NEXT: vmov r3, s12308; CHECK-NEXT: vmov r2, s14309; CHECK-NEXT: vmov.16 q4[6], r3310; CHECK-NEXT: vldrb.u16 q0, [r1]311; CHECK-NEXT: vmov.16 q4[7], r2312; CHECK-NEXT: vstrh.16 q4, [r0, q0]313; CHECK-NEXT: vpop {d8, d9}314; CHECK-NEXT: bx lr315entry:316 %offs = load <8 x i8>, ptr %offptr, align 1317 %offs.zext = zext <8 x i8> %offs to <8 x i32>318 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext319 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>320 %input.trunc = trunc <8 x i64> %input to <8 x i16>321 call void @llvm.masked.scatter.v8i16(<8 x i16> %input.trunc, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)322 ret void323}324 325; Expand - sext offsets326define arm_aapcs_vfpcc void @trunc_signed_unscaled_i32_i8(ptr %base, ptr %offptr, <8 x i32> %input) {327; CHECK-LABEL: trunc_signed_unscaled_i32_i8:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: .save {r4, r5, r6, r7, lr}330; CHECK-NEXT: push {r4, r5, r6, r7, lr}331; CHECK-NEXT: vldrb.s32 q2, [r1]332; CHECK-NEXT: vmov r4, r5, d0333; CHECK-NEXT: vadd.i32 q2, q2, r0334; CHECK-NEXT: vmov r2, r3, d4335; CHECK-NEXT: vmov r12, lr, d5336; CHECK-NEXT: vldrb.s32 q2, [r1, #4]337; CHECK-NEXT: vadd.i32 q2, q2, r0338; CHECK-NEXT: vmov r0, r6, d1339; CHECK-NEXT: strh r4, [r2]340; CHECK-NEXT: vmov r2, r7, d4341; CHECK-NEXT: strh r5, [r3]342; CHECK-NEXT: vmov r3, r5, d5343; CHECK-NEXT: strh.w r0, [r12]344; CHECK-NEXT: vmov r0, r1, d2345; CHECK-NEXT: strh.w r6, [lr]346; CHECK-NEXT: vmov r6, r4, d3347; CHECK-NEXT: strh r0, [r2]348; CHECK-NEXT: strh r1, [r7]349; CHECK-NEXT: strh r6, [r3]350; CHECK-NEXT: strh r4, [r5]351; CHECK-NEXT: pop {r4, r5, r6, r7, pc}352entry:353 %offs = load <8 x i8>, ptr %offptr, align 1354 %offs.sext = sext <8 x i8> %offs to <8 x i32>355 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.sext356 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>357 %input.trunc = trunc <8 x i32> %input to <8 x i16>358 call void @llvm.masked.scatter.v8i16(<8 x i16> %input.trunc, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)359 ret void360}361 362define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i32_i8(ptr %base, ptr %offptr, <8 x i32> %input) {363; CHECK-LABEL: trunc_unsigned_unscaled_i32_i8:364; CHECK: @ %bb.0: @ %entry365; CHECK-NEXT: .pad #16366; CHECK-NEXT: sub sp, #16367; CHECK-NEXT: mov r2, sp368; CHECK-NEXT: vstrh.32 q1, [r2, #8]369; CHECK-NEXT: vstrh.32 q0, [r2]370; CHECK-NEXT: vldrb.u16 q0, [r1]371; CHECK-NEXT: vldrw.u32 q1, [r2]372; CHECK-NEXT: vstrh.16 q1, [r0, q0]373; CHECK-NEXT: add sp, #16374; CHECK-NEXT: bx lr375entry:376 %offs = load <8 x i8>, ptr %offptr, align 1377 %offs.zext = zext <8 x i8> %offs to <8 x i32>378 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.zext379 %ptrs = bitcast <8 x ptr> %byte_ptrs to <8 x ptr>380 %input.trunc = trunc <8 x i32> %input to <8 x i16>381 call void @llvm.masked.scatter.v8i16(<8 x i16> %input.trunc, <8 x ptr> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)382 ret void383}384 385; Expand - sext offsets386define arm_aapcs_vfpcc void @trunc_signed_unscaled_i16_i8(ptr %base, ptr %offptr, <8 x i16> %input) {387; CHECK-LABEL: trunc_signed_unscaled_i16_i8:388; CHECK: @ %bb.0: @ %entry389; CHECK-NEXT: .save {r4, r5, r6, lr}390; CHECK-NEXT: push {r4, r5, r6, lr}391; CHECK-NEXT: vldrb.s32 q1, [r1]392; CHECK-NEXT: vmov.u16 r6, q0[0]393; CHECK-NEXT: vadd.i32 q1, q1, r0394; CHECK-NEXT: vmov r2, r3, d2395; CHECK-NEXT: vmov r12, lr, d3396; CHECK-NEXT: vldrb.s32 q1, [r1, #4]397; CHECK-NEXT: vadd.i32 q1, q1, r0398; CHECK-NEXT: vmov r0, r1, d2399; CHECK-NEXT: vmov r4, r5, d3400; CHECK-NEXT: strb r6, [r2]401; CHECK-NEXT: vmov.u16 r2, q0[1]402; CHECK-NEXT: strb r2, [r3]403; CHECK-NEXT: vmov.u16 r2, q0[2]404; CHECK-NEXT: strb.w r2, [r12]405; CHECK-NEXT: vmov.u16 r2, q0[3]406; CHECK-NEXT: strb.w r2, [lr]407; CHECK-NEXT: vmov.u16 r2, q0[4]408; CHECK-NEXT: strb r2, [r0]409; CHECK-NEXT: vmov.u16 r0, q0[5]410; CHECK-NEXT: strb r0, [r1]411; CHECK-NEXT: vmov.u16 r0, q0[6]412; CHECK-NEXT: strb r0, [r4]413; CHECK-NEXT: vmov.u16 r0, q0[7]414; CHECK-NEXT: strb r0, [r5]415; CHECK-NEXT: pop {r4, r5, r6, pc}416entry:417 %offs = load <8 x i8>, ptr %offptr, align 1418 %offs.sext = sext <8 x i8> %offs to <8 x i32>419 %byte_ptrs = getelementptr inbounds i8, ptr %base, <8 x i32> %offs.sext420 %input.trunc = trunc <8 x i16> %input to <8 x i8>421 call void @llvm.masked.scatter.v8i8(<8 x i8> %input.trunc, <8 x ptr> %byte_ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)422 ret void423}424 425declare void @llvm.masked.scatter.v8i8(<8 x i8>, <8 x ptr>, i32, <8 x i1>)426declare void @llvm.masked.scatter.v8i16(<8 x i16>, <8 x ptr>, i32, <8 x i1>)427declare void @llvm.masked.scatter.v8f16(<8 x half>, <8 x ptr>, i32, <8 x i1>)428