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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4; VLDRB.u32 Qd, [base, offs]5define arm_aapcs_vfpcc void @ext_unscaled_i8_i32(ptr %base, ptr %offptr, <4 x i32> %input) {6; CHECK-LABEL: ext_unscaled_i8_i32:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vldrw.u32 q1, [r1]9; CHECK-NEXT: vstrb.32 q0, [r0, q1]10; CHECK-NEXT: bx lr11entry:12 %offs = load <4 x i32>, ptr %offptr, align 413 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs14 %t = trunc <4 x i32> %input to <4 x i8>15 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)16 ret void17}18 19; VLDRH.u32 Qd, [base, offs]20define arm_aapcs_vfpcc void @ext_unscaled_i16_i32(ptr %base, ptr %offptr, <4 x i32> %input) {21; CHECK-LABEL: ext_unscaled_i16_i32:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vldrw.u32 q1, [r1]24; CHECK-NEXT: vstrh.32 q0, [r0, q1]25; CHECK-NEXT: bx lr26entry:27 %offs = load <4 x i32>, ptr %offptr, align 428 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs29 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>30 %t = trunc <4 x i32> %input to <4 x i16>31 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)32 ret void33}34 35; VSTRW.32 Qd, [base, offs]36define arm_aapcs_vfpcc void @unscaled_i32_i32(ptr %base, ptr %offptr, <4 x i32> %input) {37; CHECK-LABEL: unscaled_i32_i32:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: vldrw.u32 q1, [r1]40; CHECK-NEXT: vstrw.32 q0, [r0, q1]41; CHECK-NEXT: bx lr42entry:43 %offs = load <4 x i32>, ptr %offptr, align 444 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs45 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>46 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)47 ret void48}49 50; VSTRW.32 Qd, [base, offs]51define arm_aapcs_vfpcc void @unscaled_f32_i32(ptr %base, ptr %offptr, <4 x float> %input) {52; CHECK-LABEL: unscaled_f32_i32:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: vldrw.u32 q1, [r1]55; CHECK-NEXT: vstrw.32 q0, [r0, q1]56; CHECK-NEXT: bx lr57entry:58 %offs = load <4 x i32>, ptr %offptr, align 459 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs60 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>61 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)62 ret void63}64 65; VSTRW.32 Qd, [base, offs.zext]66define arm_aapcs_vfpcc void @unsigned_unscaled_b_i32_i16(ptr %base, ptr %offptr, <4 x i32> %input) {67; CHECK-LABEL: unsigned_unscaled_b_i32_i16:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: vldrh.u32 q1, [r1]70; CHECK-NEXT: vstrw.32 q0, [r0, q1]71; CHECK-NEXT: bx lr72entry:73 %offs = load <4 x i16>, ptr %offptr, align 274 %offs.zext = zext <4 x i16> %offs to <4 x i32>75 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext76 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>77 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)78 ret void79}80 81; VSTRW.32 Qd, [base, offs.sext]82define arm_aapcs_vfpcc void @signed_unscaled_i32_i16(ptr %base, ptr %offptr, <4 x i32> %input) {83; CHECK-LABEL: signed_unscaled_i32_i16:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vldrh.s32 q1, [r1]86; CHECK-NEXT: vstrw.32 q0, [r0, q1]87; CHECK-NEXT: bx lr88entry:89 %offs = load <4 x i16>, ptr %offptr, align 290 %offs.sext = sext <4 x i16> %offs to <4 x i32>91 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext92 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>93 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)94 ret void95}96 97; VSTRW.32 Qd, [base, offs.zext]98define arm_aapcs_vfpcc void @a_unsigned_unscaled_f32_i16(ptr %base, ptr %offptr, <4 x float> %input) {99; CHECK-LABEL: a_unsigned_unscaled_f32_i16:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vldrh.u32 q1, [r1]102; CHECK-NEXT: vstrw.32 q0, [r0, q1]103; CHECK-NEXT: bx lr104entry:105 %offs = load <4 x i16>, ptr %offptr, align 2106 %offs.zext = zext <4 x i16> %offs to <4 x i32>107 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext108 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>109 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)110 ret void111}112 113; VSTRW.32 Qd, [base, offs.sext]114define arm_aapcs_vfpcc void @b_signed_unscaled_f32_i16(ptr %base, ptr %offptr, <4 x float> %input) {115; CHECK-LABEL: b_signed_unscaled_f32_i16:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vldrh.s32 q1, [r1]118; CHECK-NEXT: vstrw.32 q0, [r0, q1]119; CHECK-NEXT: bx lr120entry:121 %offs = load <4 x i16>, ptr %offptr, align 2122 %offs.sext = sext <4 x i16> %offs to <4 x i32>123 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext124 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>125 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)126 ret void127}128 129; VLDRH.u32 Qd, [base, offs.sext]130define arm_aapcs_vfpcc void @ext_signed_unscaled_i16_i16(ptr %base, ptr %offptr, <4 x i32> %input) {131; CHECK-LABEL: ext_signed_unscaled_i16_i16:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vldrh.s32 q1, [r1]134; CHECK-NEXT: vstrh.32 q0, [r0, q1]135; CHECK-NEXT: bx lr136entry:137 %offs = load <4 x i16>, ptr %offptr, align 2138 %offs.sext = sext <4 x i16> %offs to <4 x i32>139 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext140 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>141 %t = trunc <4 x i32> %input to <4 x i16>142 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)143 ret void144}145 146; VLDRH.u32 Qd, [base, offs.zext]147define arm_aapcs_vfpcc void @ext_unsigned_unscaled_i16_i16(ptr %base, ptr %offptr, <4 x i32> %input) {148; CHECK-LABEL: ext_unsigned_unscaled_i16_i16:149; CHECK: @ %bb.0: @ %entry150; CHECK-NEXT: vldrh.u32 q1, [r1]151; CHECK-NEXT: vstrh.32 q0, [r0, q1]152; CHECK-NEXT: bx lr153entry:154 %offs = load <4 x i16>, ptr %offptr, align 2155 %offs.zext = zext <4 x i16> %offs to <4 x i32>156 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext157 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>158 %t = trunc <4 x i32> %input to <4 x i16>159 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)160 ret void161}162 163; VLDRB.u32 Qd, [base, offs.sext]164define arm_aapcs_vfpcc void @ext_signed_unscaled_i8_i16(ptr %base, ptr %offptr, <4 x i32> %input) {165; CHECK-LABEL: ext_signed_unscaled_i8_i16:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vldrh.s32 q1, [r1]168; CHECK-NEXT: vstrb.32 q0, [r0, q1]169; CHECK-NEXT: bx lr170entry:171 %offs = load <4 x i16>, ptr %offptr, align 2172 %offs.sext = sext <4 x i16> %offs to <4 x i32>173 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext174 %t = trunc <4 x i32> %input to <4 x i8>175 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)176 ret void177}178 179; VLDRB.s32 Qd, [base, offs.zext]180define arm_aapcs_vfpcc void @ext_unsigned_unscaled_i8_i16(ptr %base, ptr %offptr, <4 x i32> %input) {181; CHECK-LABEL: ext_unsigned_unscaled_i8_i16:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vldrh.u32 q1, [r1]184; CHECK-NEXT: vstrb.32 q0, [r0, q1]185; CHECK-NEXT: bx lr186entry:187 %offs = load <4 x i16>, ptr %offptr, align 2188 %offs.zext = zext <4 x i16> %offs to <4 x i32>189 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext190 %t = trunc <4 x i32> %input to <4 x i8>191 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)192 ret void193}194 195; VSTRW.32 Qd, [base, offs.zext]196define arm_aapcs_vfpcc void @unsigned_unscaled_b_i32_i8(ptr %base, ptr %offptr, <4 x i32> %input) {197; CHECK-LABEL: unsigned_unscaled_b_i32_i8:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vldrb.u32 q1, [r1]200; CHECK-NEXT: vstrw.32 q0, [r0, q1]201; CHECK-NEXT: bx lr202entry:203 %offs = load <4 x i8>, ptr %offptr, align 1204 %offs.zext = zext <4 x i8> %offs to <4 x i32>205 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext206 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>207 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)208 ret void209}210 211; VSTRW.32 Qd, [base, offs.sext]212define arm_aapcs_vfpcc void @signed_unscaled_i32_i8(ptr %base, ptr %offptr, <4 x i32> %input) {213; CHECK-LABEL: signed_unscaled_i32_i8:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vldrb.s32 q1, [r1]216; CHECK-NEXT: vstrw.32 q0, [r0, q1]217; CHECK-NEXT: bx lr218entry:219 %offs = load <4 x i8>, ptr %offptr, align 1220 %offs.sext = sext <4 x i8> %offs to <4 x i32>221 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext222 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>223 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)224 ret void225}226 227; VSTRW.32 Qd, [base, offs.zext]228define arm_aapcs_vfpcc void @a_unsigned_unscaled_f32_i8(ptr %base, ptr %offptr, <4 x float> %input) {229; CHECK-LABEL: a_unsigned_unscaled_f32_i8:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vldrb.u32 q1, [r1]232; CHECK-NEXT: vstrw.32 q0, [r0, q1]233; CHECK-NEXT: bx lr234entry:235 %offs = load <4 x i8>, ptr %offptr, align 1236 %offs.zext = zext <4 x i8> %offs to <4 x i32>237 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext238 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>239 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)240 ret void241}242 243; VSTRW.32 Qd, [base, offs.sext]244define arm_aapcs_vfpcc void @b_signed_unscaled_f32_i8(ptr %base, ptr %offptr, <4 x float> %input) {245; CHECK-LABEL: b_signed_unscaled_f32_i8:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vldrb.s32 q1, [r1]248; CHECK-NEXT: vstrw.32 q0, [r0, q1]249; CHECK-NEXT: bx lr250entry:251 %offs = load <4 x i8>, ptr %offptr, align 1252 %offs.sext = sext <4 x i8> %offs to <4 x i32>253 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext254 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>255 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %input, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)256 ret void257}258 259; VLDRH.u32 Qd, [base, offs.sext]260define arm_aapcs_vfpcc void @ext_signed_unscaled_i8_i8(ptr %base, ptr %offptr, <4 x i32> %input) {261; CHECK-LABEL: ext_signed_unscaled_i8_i8:262; CHECK: @ %bb.0: @ %entry263; CHECK-NEXT: vldrb.s32 q1, [r1]264; CHECK-NEXT: vstrb.32 q0, [r0, q1]265; CHECK-NEXT: bx lr266entry:267 %offs = load <4 x i8>, ptr %offptr, align 1268 %offs.sext = sext <4 x i8> %offs to <4 x i32>269 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext270 %t = trunc <4 x i32> %input to <4 x i8>271 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)272 ret void273}274 275; VLDRH.u32 Qd, [base, offs.zext]276define arm_aapcs_vfpcc void @ext_unsigned_unscaled_i8_i8(ptr %base, ptr %offptr, <4 x i32> %input) {277; CHECK-LABEL: ext_unsigned_unscaled_i8_i8:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vldrb.u32 q1, [r1]280; CHECK-NEXT: vstrb.32 q0, [r0, q1]281; CHECK-NEXT: bx lr282entry:283 %offs = load <4 x i8>, ptr %offptr, align 1284 %offs.zext = zext <4 x i8> %offs to <4 x i32>285 %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext286 %t = trunc <4 x i32> %input to <4 x i8>287 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %t, <4 x ptr> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)288 ret void289}290 291define arm_aapcs_vfpcc void @trunc_signed_unscaled_i64_i8(ptr %base, ptr %offptr, <4 x i64> %input) {292; CHECK-LABEL: trunc_signed_unscaled_i64_i8:293; CHECK: @ %bb.0: @ %entry294; CHECK-NEXT: vldrb.s32 q2, [r1]295; CHECK-NEXT: vmov.f32 s1, s2296; CHECK-NEXT: vmov.f32 s2, s4297; CHECK-NEXT: vmov.f32 s3, s6298; CHECK-NEXT: vstrw.32 q0, [r0, q2]299; CHECK-NEXT: bx lr300entry:301 %offs = load <4 x i8>, ptr %offptr, align 1302 %offs.sext = sext <4 x i8> %offs to <4 x i32>303 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext304 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>305 %input.trunc = trunc <4 x i64> %input to <4 x i32>306 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input.trunc, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)307 ret void308}309 310define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i64_i8(ptr %base, ptr %offptr, <4 x i64> %input) {311; CHECK-LABEL: trunc_unsigned_unscaled_i64_i8:312; CHECK: @ %bb.0: @ %entry313; CHECK-NEXT: vldrb.u32 q2, [r1]314; CHECK-NEXT: vmov.f32 s1, s2315; CHECK-NEXT: vmov.f32 s2, s4316; CHECK-NEXT: vmov.f32 s3, s6317; CHECK-NEXT: vstrw.32 q0, [r0, q2]318; CHECK-NEXT: bx lr319entry:320 %offs = load <4 x i8>, ptr %offptr, align 1321 %offs.zext = zext <4 x i8> %offs to <4 x i32>322 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext323 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>324 %input.trunc = trunc <4 x i64> %input to <4 x i32>325 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %input.trunc, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)326 ret void327}328 329define arm_aapcs_vfpcc void @trunc_signed_unscaled_i32_i8(ptr %base, ptr %offptr, <4 x i32> %input) {330; CHECK-LABEL: trunc_signed_unscaled_i32_i8:331; CHECK: @ %bb.0: @ %entry332; CHECK-NEXT: vldrb.s32 q1, [r1]333; CHECK-NEXT: vstrh.32 q0, [r0, q1]334; CHECK-NEXT: bx lr335entry:336 %offs = load <4 x i8>, ptr %offptr, align 1337 %offs.sext = sext <4 x i8> %offs to <4 x i32>338 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext339 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>340 %input.trunc = trunc <4 x i32> %input to <4 x i16>341 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %input.trunc, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)342 ret void343}344 345define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i32_i8(ptr %base, ptr %offptr, <4 x i32> %input) {346; CHECK-LABEL: trunc_unsigned_unscaled_i32_i8:347; CHECK: @ %bb.0: @ %entry348; CHECK-NEXT: vldrb.u32 q1, [r1]349; CHECK-NEXT: vstrh.32 q0, [r0, q1]350; CHECK-NEXT: bx lr351entry:352 %offs = load <4 x i8>, ptr %offptr, align 1353 %offs.zext = zext <4 x i8> %offs to <4 x i32>354 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext355 %ptrs = bitcast <4 x ptr> %byte_ptrs to <4 x ptr>356 %input.trunc = trunc <4 x i32> %input to <4 x i16>357 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %input.trunc, <4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)358 ret void359}360 361define arm_aapcs_vfpcc void @trunc_signed_unscaled_i16_i8(ptr %base, ptr %offptr, <4 x i16> %input) {362; CHECK-LABEL: trunc_signed_unscaled_i16_i8:363; CHECK: @ %bb.0: @ %entry364; CHECK-NEXT: vmov.i32 q1, #0xff365; CHECK-NEXT: vldrb.s32 q2, [r1]366; CHECK-NEXT: vand q0, q0, q1367; CHECK-NEXT: vstrb.32 q0, [r0, q2]368; CHECK-NEXT: bx lr369entry:370 %offs = load <4 x i8>, ptr %offptr, align 1371 %offs.sext = sext <4 x i8> %offs to <4 x i32>372 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.sext373 %input.trunc = trunc <4 x i16> %input to <4 x i8>374 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %input.trunc, <4 x ptr> %byte_ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)375 ret void376}377 378define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i16_i8(ptr %base, ptr %offptr, <4 x i16> %input) {379; CHECK-LABEL: trunc_unsigned_unscaled_i16_i8:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: vmov.i32 q1, #0xff382; CHECK-NEXT: vldrb.u32 q2, [r1]383; CHECK-NEXT: vand q0, q0, q1384; CHECK-NEXT: vstrb.32 q0, [r0, q2]385; CHECK-NEXT: bx lr386entry:387 %offs = load <4 x i8>, ptr %offptr, align 1388 %offs.zext = zext <4 x i8> %offs to <4 x i32>389 %byte_ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> %offs.zext390 %input.trunc = trunc <4 x i16> %input to <4 x i8>391 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %input.trunc, <4 x ptr> %byte_ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)392 ret void393}394 395declare void @llvm.masked.scatter.v4i8.v4p0(<4 x i8>, <4 x ptr>, i32, <4 x i1>)396declare void @llvm.masked.scatter.v4i16.v4p0(<4 x i16>, <4 x ptr>, i32, <4 x i1>)397declare void @llvm.masked.scatter.v4f16.v4p0(<4 x half>, <4 x ptr>, i32, <4 x i1>)398declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32, <4 x i1>)399declare void @llvm.masked.scatter.v4f32.v4p0(<4 x float>, <4 x ptr>, i32, <4 x i1>)400