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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst %s -o - | FileCheck %s3 4; i325 6; Expand7define arm_aapcs_vfpcc void @ptr_v2i32(<2 x i32> %v, ptr %offptr) {8; CHECK-LABEL: ptr_v2i32:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: vmov r2, s011; CHECK-NEXT: ldrd r0, r1, [r0]12; CHECK-NEXT: str r2, [r0]13; CHECK-NEXT: vmov r0, s214; CHECK-NEXT: str r0, [r1]15; CHECK-NEXT: bx lr16entry:17 %offs = load <2 x ptr>, ptr %offptr, align 418 call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %v, <2 x ptr> %offs, i32 4, <2 x i1> <i1 true, i1 true>)19 ret void20}21 22; VSTRW.32 Qd, [offs, 0]23define arm_aapcs_vfpcc void @ptr_v4i32(<4 x i32> %v, ptr %offptr) {24; CHECK-LABEL: ptr_v4i32:25; CHECK: @ %bb.0: @ %entry26; CHECK-NEXT: vldrw.u32 q1, [r0]27; CHECK-NEXT: vstrw.32 q0, [q1]28; CHECK-NEXT: bx lr29entry:30 %offs = load <4 x ptr>, ptr %offptr, align 431 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %v, <4 x ptr> %offs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)32 ret void33}34 35; Expand36define arm_aapcs_vfpcc void @ptr_v8i32(<8 x i32> %v, ptr %offptr) {37; CHECK-LABEL: ptr_v8i32:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: .save {r4, r5, r6, r7, lr}40; CHECK-NEXT: push {r4, r5, r6, r7, lr}41; CHECK-NEXT: vldrw.u32 q2, [r0]42; CHECK-NEXT: vmov r3, r4, d043; CHECK-NEXT: vmov r1, r2, d444; CHECK-NEXT: vmov lr, r12, d545; CHECK-NEXT: vldrw.u32 q2, [r0, #16]46; CHECK-NEXT: vmov r0, r5, d147; CHECK-NEXT: str r3, [r1]48; CHECK-NEXT: vmov r1, r7, d449; CHECK-NEXT: str r4, [r2]50; CHECK-NEXT: vmov r2, r4, d551; CHECK-NEXT: str.w r0, [lr]52; CHECK-NEXT: vmov r0, r3, d253; CHECK-NEXT: str.w r5, [r12]54; CHECK-NEXT: vmov r5, r6, d355; CHECK-NEXT: str r0, [r1]56; CHECK-NEXT: str r3, [r7]57; CHECK-NEXT: str r5, [r2]58; CHECK-NEXT: str r6, [r4]59; CHECK-NEXT: pop {r4, r5, r6, r7, pc}60entry:61 %offs = load <8 x ptr>, ptr %offptr, align 462 call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %v, <8 x ptr> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)63 ret void64}65 66; Expand67define arm_aapcs_vfpcc void @ptr_v16i32(<16 x i32> %v, ptr %offptr) {68; CHECK-LABEL: ptr_v16i32:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: .save {r4, r5, r6, r7, lr}71; CHECK-NEXT: push {r4, r5, r6, r7, lr}72; CHECK-NEXT: .pad #473; CHECK-NEXT: sub sp, #474; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}75; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}76; CHECK-NEXT: vldrw.u32 q4, [r0]77; CHECK-NEXT: vmov r3, r4, d078; CHECK-NEXT: vldrw.u32 q5, [r0, #32]79; CHECK-NEXT: vldrw.u32 q6, [r0, #16]80; CHECK-NEXT: vmov r1, r2, d881; CHECK-NEXT: vmov lr, r12, d982; CHECK-NEXT: vldrw.u32 q4, [r0, #48]83; CHECK-NEXT: vmov r0, r5, d184; CHECK-NEXT: str r3, [r1]85; CHECK-NEXT: vmov r1, r3, d1286; CHECK-NEXT: str r4, [r2]87; CHECK-NEXT: vmov r2, r7, d1388; CHECK-NEXT: str.w r0, [lr]89; CHECK-NEXT: vmov r0, r4, d290; CHECK-NEXT: str.w r5, [r12]91; CHECK-NEXT: vmov r5, r6, d392; CHECK-NEXT: str r0, [r1]93; CHECK-NEXT: vmov r0, r1, d1094; CHECK-NEXT: str r4, [r3]95; CHECK-NEXT: vmov r3, r4, d1196; CHECK-NEXT: str r5, [r2]97; CHECK-NEXT: vmov r2, r5, d498; CHECK-NEXT: str r6, [r7]99; CHECK-NEXT: vmov r7, r6, d5100; CHECK-NEXT: str r2, [r0]101; CHECK-NEXT: vmov r0, r2, d8102; CHECK-NEXT: str r5, [r1]103; CHECK-NEXT: vmov r1, r5, d9104; CHECK-NEXT: str r7, [r3]105; CHECK-NEXT: vmov r3, r7, d6106; CHECK-NEXT: str r6, [r4]107; CHECK-NEXT: vmov r6, r4, d7108; CHECK-NEXT: str r3, [r0]109; CHECK-NEXT: str r7, [r2]110; CHECK-NEXT: str r6, [r1]111; CHECK-NEXT: str r4, [r5]112; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}113; CHECK-NEXT: add sp, #4114; CHECK-NEXT: pop {r4, r5, r6, r7, pc}115entry:116 %offs = load <16 x ptr>, ptr %offptr, align 4117 call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %v, <16 x ptr> %offs, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)118 ret void119}120 121; f32122 123; Expand124define arm_aapcs_vfpcc void @ptr_v2f32(<2 x float> %v, ptr %offptr) {125; CHECK-LABEL: ptr_v2f32:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: ldrd r0, r1, [r0]128; CHECK-NEXT: vstr s0, [r0]129; CHECK-NEXT: vstr s1, [r1]130; CHECK-NEXT: bx lr131entry:132 %offs = load <2 x ptr>, ptr %offptr, align 4133 call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> %v, <2 x ptr> %offs, i32 4, <2 x i1> <i1 true, i1 true>)134 ret void135}136 137; VSTRW.32 Qd, [offs, 0]138define arm_aapcs_vfpcc void @ptr_v4f32(<4 x float> %v, ptr %offptr) {139; CHECK-LABEL: ptr_v4f32:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vldrw.u32 q1, [r0]142; CHECK-NEXT: vstrw.32 q0, [q1]143; CHECK-NEXT: bx lr144entry:145 %offs = load <4 x ptr>, ptr %offptr, align 4146 call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %v, <4 x ptr> %offs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)147 ret void148}149 150; Expand151define arm_aapcs_vfpcc void @ptr_v8f32(<8 x float> %v, ptr %offptr) {152; CHECK-LABEL: ptr_v8f32:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: .save {r4, r5, r7, lr}155; CHECK-NEXT: push {r4, r5, r7, lr}156; CHECK-NEXT: vldrw.u32 q2, [r0]157; CHECK-NEXT: vmov r1, lr, d4158; CHECK-NEXT: vmov r3, r12, d5159; CHECK-NEXT: vldrw.u32 q2, [r0, #16]160; CHECK-NEXT: vmov r0, r2, d4161; CHECK-NEXT: vmov r4, r5, d5162; CHECK-NEXT: vstr s0, [r1]163; CHECK-NEXT: vstr s1, [lr]164; CHECK-NEXT: vstr s2, [r3]165; CHECK-NEXT: vstr s3, [r12]166; CHECK-NEXT: vstr s4, [r0]167; CHECK-NEXT: vstr s5, [r2]168; CHECK-NEXT: vstr s6, [r4]169; CHECK-NEXT: vstr s7, [r5]170; CHECK-NEXT: pop {r4, r5, r7, pc}171entry:172 %offs = load <8 x ptr>, ptr %offptr, align 4173 call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %v, <8 x ptr> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)174 ret void175}176 177; i16178 179; Expand.180define arm_aapcs_vfpcc void @ptr_i16(<8 x i16> %v, ptr %offptr) {181; CHECK-LABEL: ptr_i16:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: .save {r4, r5, r6, lr}184; CHECK-NEXT: push {r4, r5, r6, lr}185; CHECK-NEXT: vldrw.u32 q1, [r0]186; CHECK-NEXT: vmov.u16 r6, q0[0]187; CHECK-NEXT: vmov r1, r2, d2188; CHECK-NEXT: vmov r3, r12, d3189; CHECK-NEXT: vldrw.u32 q1, [r0, #16]190; CHECK-NEXT: vmov r0, lr, d2191; CHECK-NEXT: vmov r4, r5, d3192; CHECK-NEXT: strh r6, [r1]193; CHECK-NEXT: vmov.u16 r1, q0[1]194; CHECK-NEXT: strh r1, [r2]195; CHECK-NEXT: vmov.u16 r1, q0[2]196; CHECK-NEXT: strh r1, [r3]197; CHECK-NEXT: vmov.u16 r1, q0[3]198; CHECK-NEXT: strh.w r1, [r12]199; CHECK-NEXT: vmov.u16 r1, q0[4]200; CHECK-NEXT: strh r1, [r0]201; CHECK-NEXT: vmov.u16 r0, q0[5]202; CHECK-NEXT: strh.w r0, [lr]203; CHECK-NEXT: vmov.u16 r0, q0[6]204; CHECK-NEXT: strh r0, [r4]205; CHECK-NEXT: vmov.u16 r0, q0[7]206; CHECK-NEXT: strh r0, [r5]207; CHECK-NEXT: pop {r4, r5, r6, pc}208entry:209 %offs = load <8 x ptr>, ptr %offptr, align 4210 call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %v, <8 x ptr> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)211 ret void212}213 214; Expand215define arm_aapcs_vfpcc void @ptr_v2i16_trunc(<2 x i32> %v, ptr %offptr) {216; CHECK-LABEL: ptr_v2i16_trunc:217; CHECK: @ %bb.0: @ %entry218; CHECK-NEXT: vmov r2, s0219; CHECK-NEXT: ldrd r0, r1, [r0]220; CHECK-NEXT: strh r2, [r0]221; CHECK-NEXT: vmov r0, s2222; CHECK-NEXT: strh r0, [r1]223; CHECK-NEXT: bx lr224entry:225 %offs = load <2 x ptr>, ptr %offptr, align 4226 %ext = trunc <2 x i32> %v to <2 x i16>227 call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> %ext, <2 x ptr> %offs, i32 2, <2 x i1> <i1 true, i1 true>)228 ret void229}230 231define arm_aapcs_vfpcc void @ptr_v4i16_trunc(<4 x i32> %v, ptr %offptr) {232; CHECK-LABEL: ptr_v4i16_trunc:233; CHECK: @ %bb.0: @ %entry234; CHECK-NEXT: vldrw.u32 q1, [r0]235; CHECK-NEXT: movs r0, #0236; CHECK-NEXT: vstrh.32 q0, [r0, q1]237; CHECK-NEXT: bx lr238entry:239 %offs = load <4 x ptr>, ptr %offptr, align 4240 %ext = trunc <4 x i32> %v to <4 x i16>241 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %ext, <4 x ptr> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)242 ret void243}244 245define arm_aapcs_vfpcc void @ptr_v4i16_dup(i32 %v, <4 x ptr> %offs) {246; CHECK-LABEL: ptr_v4i16_dup:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vdup.32 q1, r0249; CHECK-NEXT: movs r1, #0250; CHECK-NEXT: vmovlb.u16 q1, q1251; CHECK-NEXT: vstrh.32 q1, [r1, q0]252; CHECK-NEXT: bx lr253entry:254 %ext = trunc i32 %v to i16255 %splatinsert = insertelement <4 x i16> poison, i16 %ext, i32 0256 %splat = shufflevector <4 x i16> %splatinsert, <4 x i16> poison, <4 x i32> zeroinitializer257 call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %splat, <4 x ptr> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)258 ret void259}260 261; Expand262define arm_aapcs_vfpcc void @ptr_v8i16_trunc(<8 x i32> %v, ptr %offptr) {263; CHECK-LABEL: ptr_v8i16_trunc:264; CHECK: @ %bb.0: @ %entry265; CHECK-NEXT: .save {r4, r5, r6, r7, lr}266; CHECK-NEXT: push {r4, r5, r6, r7, lr}267; CHECK-NEXT: vldrw.u32 q2, [r0]268; CHECK-NEXT: vmov r3, r4, d0269; CHECK-NEXT: vmov r1, r2, d4270; CHECK-NEXT: vmov lr, r12, d5271; CHECK-NEXT: vldrw.u32 q2, [r0, #16]272; CHECK-NEXT: vmov r0, r5, d1273; CHECK-NEXT: strh r3, [r1]274; CHECK-NEXT: vmov r1, r7, d4275; CHECK-NEXT: strh r4, [r2]276; CHECK-NEXT: vmov r2, r4, d5277; CHECK-NEXT: strh.w r0, [lr]278; CHECK-NEXT: vmov r0, r3, d2279; CHECK-NEXT: strh.w r5, [r12]280; CHECK-NEXT: vmov r5, r6, d3281; CHECK-NEXT: strh r0, [r1]282; CHECK-NEXT: strh r3, [r7]283; CHECK-NEXT: strh r5, [r2]284; CHECK-NEXT: strh r6, [r4]285; CHECK-NEXT: pop {r4, r5, r6, r7, pc}286entry:287 %offs = load <8 x ptr>, ptr %offptr, align 4288 %ext = trunc <8 x i32> %v to <8 x i16>289 call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %ext, <8 x ptr> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)290 ret void291}292 293; f16294 295; Expand.296define arm_aapcs_vfpcc void @ptr_f16(<8 x half> %v, ptr %offptr) {297; CHECK-LABEL: ptr_f16:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vldrw.u32 q2, [r0]300; CHECK-NEXT: vldrw.u32 q1, [r0, #16]301; CHECK-NEXT: vmov r0, r1, d4302; CHECK-NEXT: vstr.16 s0, [r0]303; CHECK-NEXT: vmovx.f16 s0, s0304; CHECK-NEXT: vstr.16 s0, [r1]305; CHECK-NEXT: vmov r0, r1, d5306; CHECK-NEXT: vmovx.f16 s0, s1307; CHECK-NEXT: vstr.16 s1, [r0]308; CHECK-NEXT: vstr.16 s0, [r1]309; CHECK-NEXT: vmov r0, r1, d2310; CHECK-NEXT: vmovx.f16 s0, s2311; CHECK-NEXT: vstr.16 s2, [r0]312; CHECK-NEXT: vstr.16 s0, [r1]313; CHECK-NEXT: vmov r0, r1, d3314; CHECK-NEXT: vmovx.f16 s0, s3315; CHECK-NEXT: vstr.16 s3, [r0]316; CHECK-NEXT: vstr.16 s0, [r1]317; CHECK-NEXT: bx lr318entry:319 %offs = load <8 x ptr>, ptr %offptr, align 4320 call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> %v, <8 x ptr> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)321 ret void322}323 324define arm_aapcs_vfpcc void @ptr_v4f16(<4 x half> %v, ptr %offptr) {325; CHECK-LABEL: ptr_v4f16:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vldrw.u32 q1, [r0]328; CHECK-NEXT: vmov r0, r1, d2329; CHECK-NEXT: vstr.16 s0, [r0]330; CHECK-NEXT: vmovx.f16 s0, s0331; CHECK-NEXT: vstr.16 s0, [r1]332; CHECK-NEXT: vmov r0, r1, d3333; CHECK-NEXT: vmovx.f16 s0, s1334; CHECK-NEXT: vstr.16 s1, [r0]335; CHECK-NEXT: vstr.16 s0, [r1]336; CHECK-NEXT: bx lr337entry:338 %offs = load <4 x ptr>, ptr %offptr, align 4339 call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %v, <4 x ptr> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)340 ret void341}342 343define arm_aapcs_vfpcc void @ptr_v4f16_dup(half %v, <4 x ptr> %offs) {344; CHECK-LABEL: ptr_v4f16_dup:345; CHECK: @ %bb.0: @ %entry346; CHECK-NEXT: vmov r0, r1, d2347; CHECK-NEXT: vmov r2, r3, d3348; CHECK-NEXT: vstr.16 s0, [r0]349; CHECK-NEXT: vstr.16 s0, [r1]350; CHECK-NEXT: vstr.16 s0, [r2]351; CHECK-NEXT: vstr.16 s0, [r3]352; CHECK-NEXT: bx lr353entry:354 %splatinsert = insertelement <4 x half> poison, half %v, i32 0355 %splat = shufflevector <4 x half> %splatinsert, <4 x half> poison, <4 x i32> zeroinitializer356 call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %splat, <4 x ptr> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)357 ret void358}359 360; i8361 362; Expand.363define arm_aapcs_vfpcc void @ptr_i8(<16 x i8> %v, ptr %offptr) {364; CHECK-LABEL: ptr_i8:365; CHECK: @ %bb.0: @ %entry366; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}367; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}368; CHECK-NEXT: vldrw.u32 q1, [r0]369; CHECK-NEXT: vldrw.u32 q2, [r0, #16]370; CHECK-NEXT: vldrw.u32 q3, [r0, #32]371; CHECK-NEXT: vmov.u8 r6, q0[0]372; CHECK-NEXT: vmov r1, r2, d2373; CHECK-NEXT: vmov.u8 r5, q0[4]374; CHECK-NEXT: vmov r3, r12, d3375; CHECK-NEXT: vldrw.u32 q1, [r0, #48]376; CHECK-NEXT: vmov lr, r4, d4377; CHECK-NEXT: vmov.u8 r7, q0[6]378; CHECK-NEXT: vmov r0, r8, d5379; CHECK-NEXT: strb r6, [r1]380; CHECK-NEXT: vmov.u8 r1, q0[1]381; CHECK-NEXT: strb r1, [r2]382; CHECK-NEXT: vmov.u8 r6, q0[2]383; CHECK-NEXT: vmov r1, r9, d6384; CHECK-NEXT: strb r6, [r3]385; CHECK-NEXT: vmov.u8 r3, q0[3]386; CHECK-NEXT: vmov.u8 r2, q0[8]387; CHECK-NEXT: strb.w r3, [r12]388; CHECK-NEXT: vmov r3, r6, d7389; CHECK-NEXT: strb.w r5, [lr]390; CHECK-NEXT: vmov.u8 r5, q0[5]391; CHECK-NEXT: strb r5, [r4]392; CHECK-NEXT: vmov r5, r4, d2393; CHECK-NEXT: strb r7, [r0]394; CHECK-NEXT: vmov.u8 r0, q0[7]395; CHECK-NEXT: strb.w r0, [r8]396; CHECK-NEXT: vmov r0, r7, d3397; CHECK-NEXT: strb r2, [r1]398; CHECK-NEXT: vmov.u8 r1, q0[9]399; CHECK-NEXT: strb.w r1, [r9]400; CHECK-NEXT: vmov.u8 r1, q0[10]401; CHECK-NEXT: strb r1, [r3]402; CHECK-NEXT: vmov.u8 r1, q0[11]403; CHECK-NEXT: strb r1, [r6]404; CHECK-NEXT: vmov.u8 r1, q0[12]405; CHECK-NEXT: strb r1, [r5]406; CHECK-NEXT: vmov.u8 r1, q0[13]407; CHECK-NEXT: strb r1, [r4]408; CHECK-NEXT: vmov.u8 r1, q0[14]409; CHECK-NEXT: strb r1, [r0]410; CHECK-NEXT: vmov.u8 r0, q0[15]411; CHECK-NEXT: strb r0, [r7]412; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}413entry:414 %offs = load <16 x ptr>, ptr %offptr, align 4415 call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> %v, <16 x ptr> %offs, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)416 ret void417}418 419; Expand420define arm_aapcs_vfpcc void @ptr_v8i8_trunc16(<8 x i16> %v, ptr %offptr) {421; CHECK-LABEL: ptr_v8i8_trunc16:422; CHECK: @ %bb.0: @ %entry423; CHECK-NEXT: .save {r4, r5, r6, lr}424; CHECK-NEXT: push {r4, r5, r6, lr}425; CHECK-NEXT: vldrw.u32 q1, [r0]426; CHECK-NEXT: vmov.u16 r6, q0[0]427; CHECK-NEXT: vmov r1, r2, d2428; CHECK-NEXT: vmov r3, r12, d3429; CHECK-NEXT: vldrw.u32 q1, [r0, #16]430; CHECK-NEXT: vmov r0, lr, d2431; CHECK-NEXT: vmov r4, r5, d3432; CHECK-NEXT: strb r6, [r1]433; CHECK-NEXT: vmov.u16 r1, q0[1]434; CHECK-NEXT: strb r1, [r2]435; CHECK-NEXT: vmov.u16 r1, q0[2]436; CHECK-NEXT: strb r1, [r3]437; CHECK-NEXT: vmov.u16 r1, q0[3]438; CHECK-NEXT: strb.w r1, [r12]439; CHECK-NEXT: vmov.u16 r1, q0[4]440; CHECK-NEXT: strb r1, [r0]441; CHECK-NEXT: vmov.u16 r0, q0[5]442; CHECK-NEXT: strb.w r0, [lr]443; CHECK-NEXT: vmov.u16 r0, q0[6]444; CHECK-NEXT: strb r0, [r4]445; CHECK-NEXT: vmov.u16 r0, q0[7]446; CHECK-NEXT: strb r0, [r5]447; CHECK-NEXT: pop {r4, r5, r6, pc}448entry:449 %offs = load <8 x ptr>, ptr %offptr, align 4450 %ext = trunc <8 x i16> %v to <8 x i8>451 call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %ext, <8 x ptr> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)452 ret void453}454 455define arm_aapcs_vfpcc void @ptr_v4i8_trunc32(<4 x i32> %v, ptr %offptr) {456; CHECK-LABEL: ptr_v4i8_trunc32:457; CHECK: @ %bb.0: @ %entry458; CHECK-NEXT: vldrw.u32 q1, [r0]459; CHECK-NEXT: movs r0, #0460; CHECK-NEXT: vstrb.32 q0, [r0, q1]461; CHECK-NEXT: bx lr462entry:463 %offs = load <4 x ptr>, ptr %offptr, align 4464 %ext = trunc <4 x i32> %v to <4 x i8>465 call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %ext, <4 x ptr> %offs, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)466 ret void467}468 469; Expand470define arm_aapcs_vfpcc void @ptr_v8i8_trunc32(<8 x i32> %v, ptr %offptr) {471; CHECK-LABEL: ptr_v8i8_trunc32:472; CHECK: @ %bb.0: @ %entry473; CHECK-NEXT: .save {r4, r5, r6, r7, lr}474; CHECK-NEXT: push {r4, r5, r6, r7, lr}475; CHECK-NEXT: vldrw.u32 q2, [r0]476; CHECK-NEXT: vmov r3, r4, d0477; CHECK-NEXT: vmov r1, r2, d4478; CHECK-NEXT: vmov lr, r12, d5479; CHECK-NEXT: vldrw.u32 q2, [r0, #16]480; CHECK-NEXT: vmov r0, r5, d1481; CHECK-NEXT: strb r3, [r1]482; CHECK-NEXT: vmov r1, r7, d4483; CHECK-NEXT: strb r4, [r2]484; CHECK-NEXT: vmov r2, r4, d5485; CHECK-NEXT: strb.w r0, [lr]486; CHECK-NEXT: vmov r0, r3, d2487; CHECK-NEXT: strb.w r5, [r12]488; CHECK-NEXT: vmov r5, r6, d3489; CHECK-NEXT: strb r0, [r1]490; CHECK-NEXT: strb r3, [r7]491; CHECK-NEXT: strb r5, [r2]492; CHECK-NEXT: strb r6, [r4]493; CHECK-NEXT: pop {r4, r5, r6, r7, pc}494entry:495 %offs = load <8 x ptr>, ptr %offptr, align 4496 %ext = trunc <8 x i32> %v to <8 x i8>497 call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %ext, <8 x ptr> %offs, i32 1, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)498 ret void499}500 501; loops502 503define void @foo_ptr_p_int32_t(ptr %dest, ptr %src, i32 %n) {504; CHECK-LABEL: foo_ptr_p_int32_t:505; CHECK: @ %bb.0: @ %entry506; CHECK-NEXT: bic r3, r2, #15507; CHECK-NEXT: cmp r3, #1508; CHECK-NEXT: it lt509; CHECK-NEXT: bxlt lr510; CHECK-NEXT: .LBB19_1: @ %vector.body511; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1512; CHECK-NEXT: vldrw.u32 q0, [r1], #16513; CHECK-NEXT: subs r2, #4514; CHECK-NEXT: vptt.i32 ne, q0, zr515; CHECK-NEXT: vldrwt.u32 q1, [r0], #16516; CHECK-NEXT: vstrwt.32 q1, [q0]517; CHECK-NEXT: bne .LBB19_1518; CHECK-NEXT: @ %bb.2: @ %for.end519; CHECK-NEXT: bx lr520entry:521 %and = and i32 %n, -16522 %cmp11 = icmp sgt i32 %and, 0523 br i1 %cmp11, label %vector.body, label %for.end524 525vector.body: ; preds = %entry, %vector.body526 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]527 %0 = getelementptr inbounds ptr, ptr %src, i32 %index528 %wide.load = load <4 x ptr>, ptr %0, align 4529 %1 = icmp ne <4 x ptr> %wide.load, zeroinitializer530 %2 = getelementptr inbounds i32, ptr %dest, i32 %index531 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.v4p0(ptr %2, i32 4, <4 x i1> %1, <4 x i32> undef)532 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %wide.masked.load, <4 x ptr> %wide.load, i32 4, <4 x i1> %1)533 %index.next = add i32 %index, 4534 %3 = icmp eq i32 %index.next, %n535 br i1 %3, label %for.end, label %vector.body536 537for.end: ; preds = %vector.body, %entry538 ret void539}540 541define void @foo_ptr_p_float(ptr %dest, ptr %src, i32 %n) {542; CHECK-LABEL: foo_ptr_p_float:543; CHECK: @ %bb.0: @ %entry544; CHECK-NEXT: bic r3, r2, #15545; CHECK-NEXT: cmp r3, #1546; CHECK-NEXT: it lt547; CHECK-NEXT: bxlt lr548; CHECK-NEXT: .LBB20_1: @ %vector.body549; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1550; CHECK-NEXT: vldrw.u32 q0, [r1], #16551; CHECK-NEXT: subs r2, #4552; CHECK-NEXT: vptt.i32 ne, q0, zr553; CHECK-NEXT: vldrwt.u32 q1, [r0], #16554; CHECK-NEXT: vstrwt.32 q1, [q0]555; CHECK-NEXT: bne .LBB20_1556; CHECK-NEXT: @ %bb.2: @ %for.end557; CHECK-NEXT: bx lr558entry:559 %and = and i32 %n, -16560 %cmp11 = icmp sgt i32 %and, 0561 br i1 %cmp11, label %vector.body, label %for.end562 563vector.body: ; preds = %entry, %vector.body564 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]565 %0 = getelementptr inbounds ptr, ptr %src, i32 %index566 %wide.load = load <4 x ptr>, ptr %0, align 4567 %1 = icmp ne <4 x ptr> %wide.load, zeroinitializer568 %2 = getelementptr inbounds float, ptr %dest, i32 %index569 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.v4p0(ptr %2, i32 4, <4 x i1> %1, <4 x i32> undef)570 %3 = bitcast <4 x ptr> %wide.load to <4 x ptr>571 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %wide.masked.load, <4 x ptr> %3, i32 4, <4 x i1> %1)572 %index.next = add i32 %index, 4573 %4 = icmp eq i32 %index.next, %n574 br i1 %4, label %for.end, label %vector.body575 576for.end: ; preds = %vector.body, %entry577 ret void578}579 580; VLSTW.u32 Qd, [P, 4]581define arm_aapcs_vfpcc void @qi4(<4 x i32> %v, <4 x ptr> %p) {582; CHECK-LABEL: qi4:583; CHECK: @ %bb.0: @ %entry584; CHECK-NEXT: movs r0, #16585; CHECK-NEXT: vadd.i32 q1, q1, r0586; CHECK-NEXT: vstrw.32 q0, [q1]587; CHECK-NEXT: bx lr588entry:589 %g = getelementptr inbounds i32, <4 x ptr> %p, i32 4590 call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %v, <4 x ptr> %g, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)591 ret void592}593 594declare void @llvm.masked.scatter.v2i16.v2p0(<2 x i16>, <2 x ptr>, i32, <2 x i1>)595declare void @llvm.masked.scatter.v2i32.v2p0(<2 x i32>, <2 x ptr>, i32, <2 x i1>)596declare void @llvm.masked.scatter.v2f32.v2p0(<2 x float>, <2 x ptr>, i32, <2 x i1>)597declare void @llvm.masked.scatter.v4i8.v4p0(<4 x i8>, <4 x ptr>, i32, <4 x i1>)598declare void @llvm.masked.scatter.v4i16.v4p0(<4 x i16>, <4 x ptr>, i32, <4 x i1>)599declare void @llvm.masked.scatter.v4f16.v4p0(<4 x half>, <4 x ptr>, i32, <4 x i1>)600declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32, <4 x i1>)601declare void @llvm.masked.scatter.v4f32.v4p0(<4 x float>, <4 x ptr>, i32, <4 x i1>)602declare void @llvm.masked.scatter.v8i8.v8p0(<8 x i8>, <8 x ptr>, i32, <8 x i1>)603declare void @llvm.masked.scatter.v8i16.v8p0(<8 x i16>, <8 x ptr>, i32, <8 x i1>)604declare void @llvm.masked.scatter.v8f16.v8p0(<8 x half>, <8 x ptr>, i32, <8 x i1>)605declare void @llvm.masked.scatter.v8i32.v8p0(<8 x i32>, <8 x ptr>, i32, <8 x i1>)606declare void @llvm.masked.scatter.v8f32.v8p0(<8 x float>, <8 x ptr>, i32, <8 x i1>)607declare void @llvm.masked.scatter.v16i8.v16p0(<16 x i8>, <16 x ptr>, i32, <16 x i1>)608declare void @llvm.masked.scatter.v16i32.v16p0(<16 x i32>, <16 x ptr>, i32, <16 x i1>)609declare <4 x i32> @llvm.masked.load.v4i32.v4p0(ptr, i32, <4 x i1>, <4 x i32>)610