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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat=false -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc <4 x i32> @test_v4i32(i32 %x, <4 x i32> %s0, <4 x i32> %s1) {5; CHECK-LABEL: test_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: cmp r0, #08; CHECK-NEXT: it eq9; CHECK-NEXT: bxeq lr10; CHECK-NEXT: .LBB0_1: @ %select.false11; CHECK-NEXT: vmov q0, q112; CHECK-NEXT: bx lr13entry:14 %c = icmp eq i32 %x, 015 %s = select i1 %c, <4 x i32> %s0, <4 x i32> %s116 ret <4 x i32> %s17}18 19define arm_aapcs_vfpcc <8 x i16> @test_v8i16(i32 %x, <8 x i16> %s0, <8 x i16> %s1) {20; CHECK-LABEL: test_v8i16:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: cmp r0, #023; CHECK-NEXT: it eq24; CHECK-NEXT: bxeq lr25; CHECK-NEXT: .LBB1_1: @ %select.false26; CHECK-NEXT: vmov q0, q127; CHECK-NEXT: bx lr28entry:29 %c = icmp eq i32 %x, 030 %s = select i1 %c, <8 x i16> %s0, <8 x i16> %s131 ret <8 x i16> %s32}33 34define arm_aapcs_vfpcc <16 x i8> @test_v16i8(i32 %x, <16 x i8> %s0, <16 x i8> %s1) {35; CHECK-LABEL: test_v16i8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: cmp r0, #038; CHECK-NEXT: it eq39; CHECK-NEXT: bxeq lr40; CHECK-NEXT: .LBB2_1: @ %select.false41; CHECK-NEXT: vmov q0, q142; CHECK-NEXT: bx lr43entry:44 %c = icmp eq i32 %x, 045 %s = select i1 %c, <16 x i8> %s0, <16 x i8> %s146 ret <16 x i8> %s47}48 49define arm_aapcs_vfpcc <2 x i64> @test_v2i64(i32 %x, <2 x i64> %s0, <2 x i64> %s1) {50; CHECK-LABEL: test_v2i64:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: cmp r0, #053; CHECK-NEXT: it eq54; CHECK-NEXT: bxeq lr55; CHECK-NEXT: .LBB3_1: @ %select.false56; CHECK-NEXT: vmov q0, q157; CHECK-NEXT: bx lr58entry:59 %c = icmp eq i32 %x, 060 %s = select i1 %c, <2 x i64> %s0, <2 x i64> %s161 ret <2 x i64> %s62}63 64define arm_aapcs_vfpcc <4 x float> @test_v4float(i32 %x, <4 x float> %s0, <4 x float> %s1) {65; CHECK-LABEL: test_v4float:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: cmp r0, #068; CHECK-NEXT: it eq69; CHECK-NEXT: bxeq lr70; CHECK-NEXT: .LBB4_1: @ %select.false71; CHECK-NEXT: vmov q0, q172; CHECK-NEXT: bx lr73entry:74 %c = icmp eq i32 %x, 075 %s = select i1 %c, <4 x float> %s0, <4 x float> %s176 ret <4 x float> %s77}78 79define arm_aapcs_vfpcc <8 x half> @test_v8half(i32 %x, <8 x half> %s0, <8 x half> %s1) {80; CHECK-LABEL: test_v8half:81; CHECK: @ %bb.0: @ %entry82; CHECK-NEXT: cmp r0, #083; CHECK-NEXT: it eq84; CHECK-NEXT: bxeq lr85; CHECK-NEXT: .LBB5_1: @ %select.false86; CHECK-NEXT: vmov q0, q187; CHECK-NEXT: bx lr88entry:89 %c = icmp eq i32 %x, 090 %s = select i1 %c, <8 x half> %s0, <8 x half> %s191 ret <8 x half> %s92}93 94define arm_aapcs_vfpcc <2 x double> @test_v2double(i32 %x, <2 x double> %s0, <2 x double> %s1) {95; CHECK-LABEL: test_v2double:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: cmp r0, #098; CHECK-NEXT: it eq99; CHECK-NEXT: bxeq lr100; CHECK-NEXT: .LBB6_1: @ %select.false101; CHECK-NEXT: vmov q0, q1102; CHECK-NEXT: bx lr103entry:104 %c = icmp eq i32 %x, 0105 %s = select i1 %c, <2 x double> %s0, <2 x double> %s1106 ret <2 x double> %s107}108 109define arm_aapcs_vfpcc <4 x i32> @minsize_v4i32(i32 %x, <4 x i32> %s0, <4 x i32> %s1) minsize {110; CHECK-LABEL: minsize_v4i32:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: cbz r0, .LBB7_2113; CHECK-NEXT: @ %bb.1: @ %select.false114; CHECK-NEXT: vmov q0, q1115; CHECK-NEXT: .LBB7_2: @ %select.end116; CHECK-NEXT: bx lr117entry:118 %c = icmp eq i32 %x, 0119 %s = select i1 %c, <4 x i32> %s0, <4 x i32> %s1120 ret <4 x i32> %s121}122 123define arm_aapcs_vfpcc <8 x i16> @minsize_v8i16(i32 %x, <8 x i16> %s0, <8 x i16> %s1) minsize {124; CHECK-LABEL: minsize_v8i16:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: cbz r0, .LBB8_2127; CHECK-NEXT: @ %bb.1: @ %select.false128; CHECK-NEXT: vmov q0, q1129; CHECK-NEXT: .LBB8_2: @ %select.end130; CHECK-NEXT: bx lr131entry:132 %c = icmp eq i32 %x, 0133 %s = select i1 %c, <8 x i16> %s0, <8 x i16> %s1134 ret <8 x i16> %s135}136 137define arm_aapcs_vfpcc <16 x i8> @minsize_v16i8(i32 %x, <16 x i8> %s0, <16 x i8> %s1) minsize {138; CHECK-LABEL: minsize_v16i8:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: cbz r0, .LBB9_2141; CHECK-NEXT: @ %bb.1: @ %select.false142; CHECK-NEXT: vmov q0, q1143; CHECK-NEXT: .LBB9_2: @ %select.end144; CHECK-NEXT: bx lr145entry:146 %c = icmp eq i32 %x, 0147 %s = select i1 %c, <16 x i8> %s0, <16 x i8> %s1148 ret <16 x i8> %s149}150 151define arm_aapcs_vfpcc <2 x i64> @minsize_v2i64(i32 %x, <2 x i64> %s0, <2 x i64> %s1) minsize {152; CHECK-LABEL: minsize_v2i64:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: cbz r0, .LBB10_2155; CHECK-NEXT: @ %bb.1: @ %select.false156; CHECK-NEXT: vmov q0, q1157; CHECK-NEXT: .LBB10_2: @ %select.end158; CHECK-NEXT: bx lr159entry:160 %c = icmp eq i32 %x, 0161 %s = select i1 %c, <2 x i64> %s0, <2 x i64> %s1162 ret <2 x i64> %s163}164 165define arm_aapcs_vfpcc <4 x float> @minsize_v4float(i32 %x, <4 x float> %s0, <4 x float> %s1) minsize {166; CHECK-LABEL: minsize_v4float:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: cbz r0, .LBB11_2169; CHECK-NEXT: @ %bb.1: @ %select.false170; CHECK-NEXT: vmov q0, q1171; CHECK-NEXT: .LBB11_2: @ %select.end172; CHECK-NEXT: bx lr173entry:174 %c = icmp eq i32 %x, 0175 %s = select i1 %c, <4 x float> %s0, <4 x float> %s1176 ret <4 x float> %s177}178 179define arm_aapcs_vfpcc <8 x half> @minsize_v8half(i32 %x, <8 x half> %s0, <8 x half> %s1) minsize {180; CHECK-LABEL: minsize_v8half:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: cbz r0, .LBB12_2183; CHECK-NEXT: @ %bb.1: @ %select.false184; CHECK-NEXT: vmov q0, q1185; CHECK-NEXT: .LBB12_2: @ %select.end186; CHECK-NEXT: bx lr187entry:188 %c = icmp eq i32 %x, 0189 %s = select i1 %c, <8 x half> %s0, <8 x half> %s1190 ret <8 x half> %s191}192 193define arm_aapcs_vfpcc <2 x double> @minsize_v2double(i32 %x, <2 x double> %s0, <2 x double> %s1) minsize {194; CHECK-LABEL: minsize_v2double:195; CHECK: @ %bb.0: @ %entry196; CHECK-NEXT: cbz r0, .LBB13_2197; CHECK-NEXT: @ %bb.1: @ %select.false198; CHECK-NEXT: vmov q0, q1199; CHECK-NEXT: .LBB13_2: @ %select.end200; CHECK-NEXT: bx lr201entry:202 %c = icmp eq i32 %x, 0203 %s = select i1 %c, <2 x double> %s0, <2 x double> %s1204 ret <2 x double> %s205}206 207define i32 @e() {208; CHECK-LABEL: e:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: adr r0, .LCPI14_0211; CHECK-NEXT: movs r1, #0212; CHECK-NEXT: vldrw.u32 q0, [r0]213; CHECK-NEXT: movs r0, #4214; CHECK-NEXT: vmov q1, q0215; CHECK-NEXT: .LBB14_1: @ %vector.body216; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1217; CHECK-NEXT: adds r1, #4218; CHECK-NEXT: vadd.i32 q1, q1, r0219; CHECK-NEXT: cmp r1, #8220; CHECK-NEXT: csetm r2, eq221; CHECK-NEXT: subs.w r3, r1, #8222; CHECK-NEXT: vdup.32 q2, r2223; CHECK-NEXT: csel r1, r1, r3, ne224; CHECK-NEXT: vbic q1, q1, q2225; CHECK-NEXT: vand q2, q2, q0226; CHECK-NEXT: vorr q1, q2, q1227; CHECK-NEXT: b .LBB14_1228; CHECK-NEXT: .p2align 4229; CHECK-NEXT: @ %bb.2:230; CHECK-NEXT: .LCPI14_0:231; CHECK-NEXT: .long 0 @ 0x0232; CHECK-NEXT: .long 1 @ 0x1233; CHECK-NEXT: .long 2 @ 0x2234; CHECK-NEXT: .long 3 @ 0x3235entry:236 br label %vector.body237 238vector.body: ; preds = %pred.store.continue73, %entry239 %index = phi i32 [ 0, %entry ], [ %spec.select, %pred.store.continue73 ]240 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %spec.select74, %pred.store.continue73 ]241 %l3 = icmp ult <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5>242 %l4 = extractelement <4 x i1> %l3, i32 0243 br label %pred.store.continue73244 245pred.store.continue73: ; preds = %pred.store.if72, %pred.store.continue71246 %index.next = add i32 %index, 4247 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>248 %l60 = icmp eq i32 %index.next, 8249 %spec.select = select i1 %l60, i32 0, i32 %index.next250 %spec.select74 = select i1 %l60, <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> %vec.ind.next251 br label %vector.body252}253 254