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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -o - %s | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -early-live-intervals -o - %s | FileCheck %s4 5define arm_aapcs_vfpcc <4 x float> @foo_v4i16(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i16> %a) {6; CHECK-LABEL: foo_v4i16:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmovlb.s16 q0, q09; CHECK-NEXT: vpt.s32 lt, q0, zr10; CHECK-NEXT: vldrht.s32 q0, [r0]11; CHECK-NEXT: vcvt.f32.s32 q0, q012; CHECK-NEXT: bx lr13entry:14 %active.lane.mask = icmp slt <4 x i16> %a, zeroinitializer15 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %pSrc, i32 2, <4 x i1> %active.lane.mask, <4 x i16> undef)16 %0 = sitofp <4 x i16> %wide.masked.load to <4 x float>17 ret <4 x float> %018}19 20define arm_aapcs_vfpcc <8 x half> @foo_v8i8(ptr nocapture readonly %pSrc, i32 %blockSize, <8 x i8> %a) {21; CHECK-LABEL: foo_v8i8:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vmovlb.s8 q0, q024; CHECK-NEXT: vpt.s16 lt, q0, zr25; CHECK-NEXT: vldrbt.s16 q0, [r0]26; CHECK-NEXT: vcvt.f16.s16 q0, q027; CHECK-NEXT: bx lr28entry:29 %active.lane.mask = icmp slt <8 x i8> %a, zeroinitializer30 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %pSrc, i32 1, <8 x i1> %active.lane.mask, <8 x i8> undef)31 %0 = sitofp <8 x i8> %wide.masked.load to <8 x half>32 ret <8 x half> %033}34 35define arm_aapcs_vfpcc <4 x float> @foo_v4i8(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i8> %a) {36; CHECK-LABEL: foo_v4i8:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: vmovlb.s8 q0, q039; CHECK-NEXT: vmovlb.s16 q0, q040; CHECK-NEXT: vpt.s32 lt, q0, zr41; CHECK-NEXT: vldrbt.s32 q0, [r0]42; CHECK-NEXT: vcvt.f32.s32 q0, q043; CHECK-NEXT: bx lr44entry:45 %active.lane.mask = icmp slt <4 x i8> %a, zeroinitializer46 %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %pSrc, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)47 %0 = sitofp <4 x i8> %wide.masked.load to <4 x float>48 ret <4 x float> %049}50 51define arm_aapcs_vfpcc <4 x double> @foo_v4i32(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) {52; CHECK-LABEL: foo_v4i32:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: .save {r7, lr}55; CHECK-NEXT: push {r7, lr}56; CHECK-NEXT: .vsave {d8, d9, d10, d11}57; CHECK-NEXT: vpush {d8, d9, d10, d11}58; CHECK-NEXT: vpt.s32 lt, q0, zr59; CHECK-NEXT: vldrwt.u32 q5, [r0]60; CHECK-NEXT: vmov.f32 s2, s2361; CHECK-NEXT: vmov.f32 s16, s2262; CHECK-NEXT: vmov r0, s263; CHECK-NEXT: asrs r1, r0, #3164; CHECK-NEXT: bl __aeabi_l2d65; CHECK-NEXT: vmov r2, s1666; CHECK-NEXT: vmov d9, r0, r167; CHECK-NEXT: asrs r3, r2, #3168; CHECK-NEXT: mov r0, r269; CHECK-NEXT: mov r1, r370; CHECK-NEXT: bl __aeabi_l2d71; CHECK-NEXT: vmov.f32 s2, s2172; CHECK-NEXT: vmov d8, r0, r173; CHECK-NEXT: vmov r2, s274; CHECK-NEXT: asrs r3, r2, #3175; CHECK-NEXT: mov r0, r276; CHECK-NEXT: mov r1, r377; CHECK-NEXT: bl __aeabi_l2d78; CHECK-NEXT: vmov r2, s2079; CHECK-NEXT: vmov d11, r0, r180; CHECK-NEXT: asrs r3, r2, #3181; CHECK-NEXT: mov r0, r282; CHECK-NEXT: mov r1, r383; CHECK-NEXT: bl __aeabi_l2d84; CHECK-NEXT: vmov d10, r0, r185; CHECK-NEXT: vmov q1, q486; CHECK-NEXT: vmov q0, q587; CHECK-NEXT: vpop {d8, d9, d10, d11}88; CHECK-NEXT: pop {r7, pc}89entry:90 %active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer91 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)92 %0 = sitofp <4 x i32> %wide.masked.load to <4 x double>93 ret <4 x double> %094}95 96declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)97 98declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>)99 100declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>)101 102declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)103