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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i1(<4 x i32> %m) {5; CHECK-LABEL: sext_v4i32_v4i32_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vshl.i32 q0, q0, #318; CHECK-NEXT: vshr.s32 q0, q0, #319; CHECK-NEXT: bx lr10entry:11 %shl = shl <4 x i32> %m, <i32 31, i32 31, i32 31, i32 31>12 %shr = ashr exact <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>13 ret <4 x i32> %shr14}15 16define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i8(<4 x i32> %m) {17; CHECK-LABEL: sext_v4i32_v4i32_v4i8:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmovlb.s8 q0, q020; CHECK-NEXT: vmovlb.s16 q0, q021; CHECK-NEXT: bx lr22entry:23 %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>24 %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>25 ret <4 x i32> %shr26}27 28define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i16(<4 x i32> %m) {29; CHECK-LABEL: sext_v4i32_v4i32_v4i16:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vmovlb.s16 q0, q032; CHECK-NEXT: bx lr33entry:34 %shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>35 %shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>36 ret <4 x i32> %shr37}38 39define arm_aapcs_vfpcc <8 x i16> @sext_v8i16_v8i16_v8i8(<8 x i16> %m) {40; CHECK-LABEL: sext_v8i16_v8i16_v8i8:41; CHECK: @ %bb.0: @ %entry42; CHECK-NEXT: vmovlb.s8 q0, q043; CHECK-NEXT: bx lr44entry:45 %shl = shl <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>46 %shr = ashr exact <8 x i16> %shl, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>47 ret <8 x i16> %shr48}49 50define arm_aapcs_vfpcc <8 x i16> @sext_v8i16_v8i16_v8i1(<8 x i16> %m) {51; CHECK-LABEL: sext_v8i16_v8i16_v8i1:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: vshl.i16 q0, q0, #1554; CHECK-NEXT: vshr.s16 q0, q0, #1555; CHECK-NEXT: bx lr56entry:57 %shl = shl <8 x i16> %m, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>58 %shr = ashr exact <8 x i16> %shl, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>59 ret <8 x i16> %shr60}61 62define arm_aapcs_vfpcc <2 x i64> @sext_v2i64_v2i64_v2i32(<2 x i64> %m) {63; CHECK-LABEL: sext_v2i64_v2i64_v2i32:64; CHECK: @ %bb.0: @ %entry65; CHECK-NEXT: vmov r0, s266; CHECK-NEXT: vmov r1, s067; CHECK-NEXT: vmov q0[2], q0[0], r1, r068; CHECK-NEXT: asrs r0, r0, #3169; CHECK-NEXT: asrs r1, r1, #3170; CHECK-NEXT: vmov q0[3], q0[1], r1, r071; CHECK-NEXT: bx lr72entry:73 %shl = shl <2 x i64> %m, <i64 32, i64 32>74 %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>75 ret <2 x i64> %shr76}77 78define arm_aapcs_vfpcc <2 x i64> @sext_v2i64_v2i64_v2i35(<2 x i64> %m) {79; CHECK-LABEL: sext_v2i64_v2i64_v2i35:80; CHECK: @ %bb.0: @ %entry81; CHECK-NEXT: vmov r0, r1, d182; CHECK-NEXT: vmov r2, r3, d083; CHECK-NEXT: vmov q0[2], q0[0], r2, r084; CHECK-NEXT: sbfx r0, r1, #0, #385; CHECK-NEXT: sbfx r1, r3, #0, #386; CHECK-NEXT: vmov q0[3], q0[1], r1, r087; CHECK-NEXT: bx lr88entry:89 %shl = shl <2 x i64> %m, <i64 29, i64 29>90 %shr = ashr exact <2 x i64> %shl, <i64 29, i64 29>91 ret <2 x i64> %shr92}93 94define arm_aapcs_vfpcc <8 x i16> @sext_v8i8_v8i16(<8 x i8> %src) {95; CHECK-LABEL: sext_v8i8_v8i16:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vmovlb.s8 q0, q098; CHECK-NEXT: bx lr99entry:100 %0 = sext <8 x i8> %src to <8 x i16>101 ret <8 x i16> %0102}103 104define arm_aapcs_vfpcc <4 x i32> @sext_v4i16_v4i32(<4 x i16> %src) {105; CHECK-LABEL: sext_v4i16_v4i32:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vmovlb.s16 q0, q0108; CHECK-NEXT: bx lr109entry:110 %0 = sext <4 x i16> %src to <4 x i32>111 ret <4 x i32> %0112}113 114define arm_aapcs_vfpcc <4 x i32> @sext_v4i8_v4i32(<4 x i8> %src) {115; CHECK-LABEL: sext_v4i8_v4i32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vmovlb.s8 q0, q0118; CHECK-NEXT: vmovlb.s16 q0, q0119; CHECK-NEXT: bx lr120entry:121 %0 = sext <4 x i8> %src to <4 x i32>122 ret <4 x i32> %0123}124 125define arm_aapcs_vfpcc <16 x i16> @sext_v16i8_v16i16(<16 x i8> %src) {126; CHECK-LABEL: sext_v16i8_v16i16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: .pad #16129; CHECK-NEXT: sub sp, #16130; CHECK-NEXT: mov r0, sp131; CHECK-NEXT: vstrw.32 q0, [r0]132; CHECK-NEXT: vldrb.s16 q0, [r0]133; CHECK-NEXT: vldrb.s16 q1, [r0, #8]134; CHECK-NEXT: add sp, #16135; CHECK-NEXT: bx lr136entry:137 %0 = sext <16 x i8> %src to <16 x i16>138 ret <16 x i16> %0139}140 141define arm_aapcs_vfpcc <8 x i32> @sext_v8i16_v8i32(<8 x i16> %src) {142; CHECK-LABEL: sext_v8i16_v8i32:143; CHECK: @ %bb.0: @ %entry144; CHECK-NEXT: .pad #16145; CHECK-NEXT: sub sp, #16146; CHECK-NEXT: mov r0, sp147; CHECK-NEXT: vstrw.32 q0, [r0]148; CHECK-NEXT: vldrh.s32 q0, [r0]149; CHECK-NEXT: vldrh.s32 q1, [r0, #8]150; CHECK-NEXT: add sp, #16151; CHECK-NEXT: bx lr152entry:153 %0 = sext <8 x i16> %src to <8 x i32>154 ret <8 x i32> %0155}156 157define arm_aapcs_vfpcc <16 x i32> @sext_v16i8_v16i32(<16 x i8> %src) {158; CHECK-LABEL: sext_v16i8_v16i32:159; CHECK: @ %bb.0: @ %entry160; CHECK-NEXT: .pad #48161; CHECK-NEXT: sub sp, #48162; CHECK-NEXT: mov r0, sp163; CHECK-NEXT: add r1, sp, #32164; CHECK-NEXT: vstrw.32 q0, [r0]165; CHECK-NEXT: vldrb.s16 q0, [r0]166; CHECK-NEXT: vstrw.32 q0, [r1]167; CHECK-NEXT: vldrb.s16 q0, [r0, #8]168; CHECK-NEXT: add r0, sp, #16169; CHECK-NEXT: vstrw.32 q0, [r0]170; CHECK-NEXT: vldrh.s32 q0, [r1]171; CHECK-NEXT: vldrh.s32 q1, [r1, #8]172; CHECK-NEXT: vldrh.s32 q2, [r0]173; CHECK-NEXT: vldrh.s32 q3, [r0, #8]174; CHECK-NEXT: add sp, #48175; CHECK-NEXT: bx lr176entry:177 %0 = sext <16 x i8> %src to <16 x i32>178 ret <16 x i32> %0179}180 181define arm_aapcs_vfpcc <2 x i64> @sext_v2i32_v2i64(<2 x i32> %src) {182; CHECK-LABEL: sext_v2i32_v2i64:183; CHECK: @ %bb.0: @ %entry184; CHECK-NEXT: vmov r0, s2185; CHECK-NEXT: vmov r1, s0186; CHECK-NEXT: vmov q0[2], q0[0], r1, r0187; CHECK-NEXT: asrs r0, r0, #31188; CHECK-NEXT: asrs r1, r1, #31189; CHECK-NEXT: vmov q0[3], q0[1], r1, r0190; CHECK-NEXT: bx lr191entry:192 %0 = sext <2 x i32> %src to <2 x i64>193 ret <2 x i64> %0194}195 196 197define arm_aapcs_vfpcc <8 x i16> @zext_v8i8_v8i16(<8 x i8> %src) {198; CHECK-LABEL: zext_v8i8_v8i16:199; CHECK: @ %bb.0: @ %entry200; CHECK-NEXT: vmovlb.u8 q0, q0201; CHECK-NEXT: bx lr202entry:203 %0 = zext <8 x i8> %src to <8 x i16>204 ret <8 x i16> %0205}206 207define arm_aapcs_vfpcc <4 x i32> @zext_v4i16_v4i32(<4 x i16> %src) {208; CHECK-LABEL: zext_v4i16_v4i32:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: vmovlb.u16 q0, q0211; CHECK-NEXT: bx lr212entry:213 %0 = zext <4 x i16> %src to <4 x i32>214 ret <4 x i32> %0215}216 217define arm_aapcs_vfpcc <4 x i32> @zext_v4i8_v4i32(<4 x i8> %src) {218; CHECK-LABEL: zext_v4i8_v4i32:219; CHECK: @ %bb.0: @ %entry220; CHECK-NEXT: vmov.i32 q1, #0xff221; CHECK-NEXT: vand q0, q0, q1222; CHECK-NEXT: bx lr223entry:224 %0 = zext <4 x i8> %src to <4 x i32>225 ret <4 x i32> %0226}227 228define arm_aapcs_vfpcc <16 x i16> @zext_v16i8_v16i16(<16 x i8> %src) {229; CHECK-LABEL: zext_v16i8_v16i16:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: .pad #16232; CHECK-NEXT: sub sp, #16233; CHECK-NEXT: mov r0, sp234; CHECK-NEXT: vstrw.32 q0, [r0]235; CHECK-NEXT: vldrb.u16 q0, [r0]236; CHECK-NEXT: vldrb.u16 q1, [r0, #8]237; CHECK-NEXT: add sp, #16238; CHECK-NEXT: bx lr239entry:240 %0 = zext <16 x i8> %src to <16 x i16>241 ret <16 x i16> %0242}243 244define arm_aapcs_vfpcc <8 x i32> @zext_v8i16_v8i32(<8 x i16> %src) {245; CHECK-LABEL: zext_v8i16_v8i32:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: .pad #16248; CHECK-NEXT: sub sp, #16249; CHECK-NEXT: mov r0, sp250; CHECK-NEXT: vstrw.32 q0, [r0]251; CHECK-NEXT: vldrh.u32 q0, [r0]252; CHECK-NEXT: vldrh.u32 q1, [r0, #8]253; CHECK-NEXT: add sp, #16254; CHECK-NEXT: bx lr255entry:256 %0 = zext <8 x i16> %src to <8 x i32>257 ret <8 x i32> %0258}259 260define arm_aapcs_vfpcc <16 x i32> @zext_v16i8_v16i32(<16 x i8> %src) {261; CHECK-LABEL: zext_v16i8_v16i32:262; CHECK: @ %bb.0: @ %entry263; CHECK-NEXT: .pad #48264; CHECK-NEXT: sub sp, #48265; CHECK-NEXT: mov r0, sp266; CHECK-NEXT: add r1, sp, #32267; CHECK-NEXT: vstrw.32 q0, [r0]268; CHECK-NEXT: vldrb.u16 q0, [r0]269; CHECK-NEXT: vstrw.32 q0, [r1]270; CHECK-NEXT: vldrb.u16 q0, [r0, #8]271; CHECK-NEXT: add r0, sp, #16272; CHECK-NEXT: vstrw.32 q0, [r0]273; CHECK-NEXT: vldrh.u32 q0, [r1]274; CHECK-NEXT: vldrh.u32 q1, [r1, #8]275; CHECK-NEXT: vldrh.u32 q2, [r0]276; CHECK-NEXT: vldrh.u32 q3, [r0, #8]277; CHECK-NEXT: add sp, #48278; CHECK-NEXT: bx lr279entry:280 %0 = zext <16 x i8> %src to <16 x i32>281 ret <16 x i32> %0282}283 284define arm_aapcs_vfpcc <2 x i64> @zext_v2i32_v2i64(<2 x i32> %src) {285; CHECK-LABEL: zext_v2i32_v2i64:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vmov.i64 q1, #0xffffffff288; CHECK-NEXT: vand q0, q0, q1289; CHECK-NEXT: bx lr290entry:291 %0 = zext <2 x i32> %src to <2 x i64>292 ret <2 x i64> %0293}294 295 296define arm_aapcs_vfpcc <8 x i8> @trunc_v8i16_v8i8(<8 x i16> %src) {297; CHECK-LABEL: trunc_v8i16_v8i8:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: bx lr300entry:301 %0 = trunc <8 x i16> %src to <8 x i8>302 ret <8 x i8> %0303}304 305define arm_aapcs_vfpcc <4 x i16> @trunc_v4i32_v4i16(<4 x i32> %src) {306; CHECK-LABEL: trunc_v4i32_v4i16:307; CHECK: @ %bb.0: @ %entry308; CHECK-NEXT: bx lr309entry:310 %0 = trunc <4 x i32> %src to <4 x i16>311 ret <4 x i16> %0312}313 314define arm_aapcs_vfpcc <4 x i8> @trunc_v4i32_v4i8(<4 x i32> %src) {315; CHECK-LABEL: trunc_v4i32_v4i8:316; CHECK: @ %bb.0: @ %entry317; CHECK-NEXT: bx lr318entry:319 %0 = trunc <4 x i32> %src to <4 x i8>320 ret <4 x i8> %0321}322 323define arm_aapcs_vfpcc <16 x i8> @trunc_v16i16_v16i8(<16 x i16> %src) {324; CHECK-LABEL: trunc_v16i16_v16i8:325; CHECK: @ %bb.0: @ %entry326; CHECK-NEXT: .pad #16327; CHECK-NEXT: sub sp, #16328; CHECK-NEXT: mov r0, sp329; CHECK-NEXT: vstrb.16 q1, [r0, #8]330; CHECK-NEXT: vstrb.16 q0, [r0]331; CHECK-NEXT: vldrw.u32 q0, [r0]332; CHECK-NEXT: add sp, #16333; CHECK-NEXT: bx lr334entry:335 %0 = trunc <16 x i16> %src to <16 x i8>336 ret <16 x i8> %0337}338 339define arm_aapcs_vfpcc <8 x i16> @trunc_v8i32_v8i16(<8 x i32> %src) {340; CHECK-LABEL: trunc_v8i32_v8i16:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: .pad #16343; CHECK-NEXT: sub sp, #16344; CHECK-NEXT: mov r0, sp345; CHECK-NEXT: vstrh.32 q1, [r0, #8]346; CHECK-NEXT: vstrh.32 q0, [r0]347; CHECK-NEXT: vldrw.u32 q0, [r0]348; CHECK-NEXT: add sp, #16349; CHECK-NEXT: bx lr350entry:351 %0 = trunc <8 x i32> %src to <8 x i16>352 ret <8 x i16> %0353}354 355define arm_aapcs_vfpcc <16 x i8> @trunc_v16i32_v16i8(<16 x i32> %src) {356; CHECK-LABEL: trunc_v16i32_v16i8:357; CHECK: @ %bb.0: @ %entry358; CHECK-NEXT: .pad #16359; CHECK-NEXT: sub sp, #16360; CHECK-NEXT: mov r0, sp361; CHECK-NEXT: vstrb.32 q3, [r0, #12]362; CHECK-NEXT: vstrb.32 q2, [r0, #8]363; CHECK-NEXT: vstrb.32 q1, [r0, #4]364; CHECK-NEXT: vstrb.32 q0, [r0]365; CHECK-NEXT: vldrw.u32 q0, [r0]366; CHECK-NEXT: add sp, #16367; CHECK-NEXT: bx lr368entry:369 %0 = trunc <16 x i32> %src to <16 x i8>370 ret <16 x i8> %0371}372 373define arm_aapcs_vfpcc <2 x i32> @trunc_v2i64_v2i32(<2 x i64> %src) {374; CHECK-LABEL: trunc_v2i64_v2i32:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: bx lr377entry:378 %0 = trunc <2 x i64> %src to <2 x i32>379 ret <2 x i32> %0380}381 382