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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @shl_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: shl_qq_int8_t:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vshl.u8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = shl <16 x i8> %src1, %src211 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @shl_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) {15; CHECK-LABEL: shl_qq_int16_t:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vshl.u16 q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = shl <8 x i16> %src1, %src221 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @shl_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) {25; CHECK-LABEL: shl_qq_int32_t:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vshl.u32 q0, q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = shl <4 x i32> %src1, %src231 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <2 x i64> @shl_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) {35; CHECK-LABEL: shl_qq_int64_t:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: .save {r5, lr}38; CHECK-NEXT: push {r5, lr}39; CHECK-NEXT: vmov r0, s640; CHECK-NEXT: vmov r2, r1, d141; CHECK-NEXT: lsll r2, r1, r042; CHECK-NEXT: vmov r3, s443; CHECK-NEXT: vmov r0, r5, d044; CHECK-NEXT: lsll r0, r5, r345; CHECK-NEXT: vmov q0[2], q0[0], r0, r246; CHECK-NEXT: vmov q0[3], q0[1], r5, r147; CHECK-NEXT: pop {r5, pc}48entry:49 %0 = shl <2 x i64> %src1, %src250 ret <2 x i64> %051}52 53 54define arm_aapcs_vfpcc <16 x i8> @shru_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) {55; CHECK-LABEL: shru_qq_int8_t:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vneg.s8 q1, q158; CHECK-NEXT: vshl.u8 q0, q0, q159; CHECK-NEXT: bx lr60entry:61 %0 = lshr <16 x i8> %src1, %src262 ret <16 x i8> %063}64 65define arm_aapcs_vfpcc <8 x i16> @shru_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) {66; CHECK-LABEL: shru_qq_int16_t:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vneg.s16 q1, q169; CHECK-NEXT: vshl.u16 q0, q0, q170; CHECK-NEXT: bx lr71entry:72 %0 = lshr <8 x i16> %src1, %src273 ret <8 x i16> %074}75 76define arm_aapcs_vfpcc <4 x i32> @shru_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) {77; CHECK-LABEL: shru_qq_int32_t:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vneg.s32 q1, q180; CHECK-NEXT: vshl.u32 q0, q0, q181; CHECK-NEXT: bx lr82entry:83 %0 = lshr <4 x i32> %src1, %src284 ret <4 x i32> %085}86 87define arm_aapcs_vfpcc <2 x i64> @shru_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) {88; CHECK-LABEL: shru_qq_int64_t:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: .save {r5, lr}91; CHECK-NEXT: push {r5, lr}92; CHECK-NEXT: vmov r2, s693; CHECK-NEXT: vmov r1, s494; CHECK-NEXT: vmov r0, r5, d195; CHECK-NEXT: rsbs r2, r2, #096; CHECK-NEXT: lsll r0, r5, r297; CHECK-NEXT: vmov r2, r3, d098; CHECK-NEXT: rsbs r1, r1, #099; CHECK-NEXT: lsll r2, r3, r1100; CHECK-NEXT: vmov q0[2], q0[0], r2, r0101; CHECK-NEXT: vmov q0[3], q0[1], r3, r5102; CHECK-NEXT: pop {r5, pc}103entry:104 %0 = lshr <2 x i64> %src1, %src2105 ret <2 x i64> %0106}107 108 109define arm_aapcs_vfpcc <16 x i8> @shrs_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) {110; CHECK-LABEL: shrs_qq_int8_t:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: vneg.s8 q1, q1113; CHECK-NEXT: vshl.s8 q0, q0, q1114; CHECK-NEXT: bx lr115entry:116 %0 = ashr <16 x i8> %src1, %src2117 ret <16 x i8> %0118}119 120define arm_aapcs_vfpcc <8 x i16> @shrs_qq_int16_t(<8 x i16> %src1, <8 x i16> %src2) {121; CHECK-LABEL: shrs_qq_int16_t:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vneg.s16 q1, q1124; CHECK-NEXT: vshl.s16 q0, q0, q1125; CHECK-NEXT: bx lr126entry:127 %0 = ashr <8 x i16> %src1, %src2128 ret <8 x i16> %0129}130 131define arm_aapcs_vfpcc <4 x i32> @shrs_qq_int32_t(<4 x i32> %src1, <4 x i32> %src2) {132; CHECK-LABEL: shrs_qq_int32_t:133; CHECK: @ %bb.0: @ %entry134; CHECK-NEXT: vneg.s32 q1, q1135; CHECK-NEXT: vshl.s32 q0, q0, q1136; CHECK-NEXT: bx lr137entry:138 %0 = ashr <4 x i32> %src1, %src2139 ret <4 x i32> %0140}141 142define arm_aapcs_vfpcc <2 x i64> @shrs_qq_int64_t(<2 x i64> %src1, <2 x i64> %src2) {143; CHECK-LABEL: shrs_qq_int64_t:144; CHECK: @ %bb.0: @ %entry145; CHECK-NEXT: .save {r5, lr}146; CHECK-NEXT: push {r5, lr}147; CHECK-NEXT: vmov r0, s6148; CHECK-NEXT: vmov r2, r1, d1149; CHECK-NEXT: asrl r2, r1, r0150; CHECK-NEXT: vmov r3, s4151; CHECK-NEXT: vmov r0, r5, d0152; CHECK-NEXT: asrl r0, r5, r3153; CHECK-NEXT: vmov q0[2], q0[0], r0, r2154; CHECK-NEXT: vmov q0[3], q0[1], r5, r1155; CHECK-NEXT: pop {r5, pc}156entry:157 %0 = ashr <2 x i64> %src1, %src2158 ret <2 x i64> %0159}160 161 162define arm_aapcs_vfpcc <16 x i8> @shl_qi_int8_t(<16 x i8> %src1) {163; CHECK-LABEL: shl_qi_int8_t:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vshl.i8 q0, q0, #4166; CHECK-NEXT: bx lr167entry:168 %0 = shl <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>169 ret <16 x i8> %0170}171 172define arm_aapcs_vfpcc <8 x i16> @shl_qi_int16_t(<8 x i16> %src1) {173; CHECK-LABEL: shl_qi_int16_t:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vshl.i16 q0, q0, #4176; CHECK-NEXT: bx lr177entry:178 %0 = shl <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>179 ret <8 x i16> %0180}181 182define arm_aapcs_vfpcc <4 x i32> @shl_qi_int32_t(<4 x i32> %src1) {183; CHECK-LABEL: shl_qi_int32_t:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: vshl.i32 q0, q0, #4186; CHECK-NEXT: bx lr187entry:188 %0 = shl <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4>189 ret <4 x i32> %0190}191 192define arm_aapcs_vfpcc <2 x i64> @shl_qi_int64_t(<2 x i64> %src1) {193; CHECK-LABEL: shl_qi_int64_t:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vmov r0, r1, d1196; CHECK-NEXT: vmov r2, r3, d0197; CHECK-NEXT: lsll r0, r1, #4198; CHECK-NEXT: lsll r2, r3, #4199; CHECK-NEXT: vmov q0[2], q0[0], r2, r0200; CHECK-NEXT: vmov q0[3], q0[1], r3, r1201; CHECK-NEXT: bx lr202entry:203 %0 = shl <2 x i64> %src1, <i64 4, i64 4>204 ret <2 x i64> %0205}206 207 208define arm_aapcs_vfpcc <16 x i8> @shru_qi_int8_t(<16 x i8> %src1) {209; CHECK-LABEL: shru_qi_int8_t:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vshr.u8 q0, q0, #4212; CHECK-NEXT: bx lr213entry:214 %0 = lshr <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>215 ret <16 x i8> %0216}217 218define arm_aapcs_vfpcc <8 x i16> @shru_qi_int16_t(<8 x i16> %src1) {219; CHECK-LABEL: shru_qi_int16_t:220; CHECK: @ %bb.0: @ %entry221; CHECK-NEXT: vshr.u16 q0, q0, #4222; CHECK-NEXT: bx lr223entry:224 %0 = lshr <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>225 ret <8 x i16> %0226}227 228define arm_aapcs_vfpcc <4 x i32> @shru_qi_int32_t(<4 x i32> %src1) {229; CHECK-LABEL: shru_qi_int32_t:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vshr.u32 q0, q0, #4232; CHECK-NEXT: bx lr233entry:234 %0 = lshr <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4>235 ret <4 x i32> %0236}237 238define arm_aapcs_vfpcc <2 x i64> @shru_qi_int64_t(<2 x i64> %src1) {239; CHECK-LABEL: shru_qi_int64_t:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vmov r0, r1, d1242; CHECK-NEXT: vmov r2, r3, d0243; CHECK-NEXT: lsrl r0, r1, #4244; CHECK-NEXT: lsrl r2, r3, #4245; CHECK-NEXT: vmov q0[2], q0[0], r2, r0246; CHECK-NEXT: vmov q0[3], q0[1], r3, r1247; CHECK-NEXT: bx lr248entry:249 %0 = lshr <2 x i64> %src1, <i64 4, i64 4>250 ret <2 x i64> %0251}252 253 254define arm_aapcs_vfpcc <16 x i8> @shrs_qi_int8_t(<16 x i8> %src1) {255; CHECK-LABEL: shrs_qi_int8_t:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: vshr.s8 q0, q0, #4258; CHECK-NEXT: bx lr259entry:260 %0 = ashr <16 x i8> %src1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>261 ret <16 x i8> %0262}263 264define arm_aapcs_vfpcc <8 x i16> @shrs_qi_int16_t(<8 x i16> %src1) {265; CHECK-LABEL: shrs_qi_int16_t:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: vshr.s16 q0, q0, #4268; CHECK-NEXT: bx lr269entry:270 %0 = ashr <8 x i16> %src1, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>271 ret <8 x i16> %0272}273 274define arm_aapcs_vfpcc <4 x i32> @shrs_qi_int32_t(<4 x i32> %src1) {275; CHECK-LABEL: shrs_qi_int32_t:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vshr.s32 q0, q0, #4278; CHECK-NEXT: bx lr279entry:280 %0 = ashr <4 x i32> %src1, <i32 4, i32 4, i32 4, i32 4>281 ret <4 x i32> %0282}283 284define arm_aapcs_vfpcc <2 x i64> @shrs_qi_int64_t(<2 x i64> %src1) {285; CHECK-LABEL: shrs_qi_int64_t:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vmov r0, r1, d1288; CHECK-NEXT: vmov r2, r3, d0289; CHECK-NEXT: asrl r0, r1, #4290; CHECK-NEXT: asrl r2, r3, #4291; CHECK-NEXT: vmov q0[2], q0[0], r2, r0292; CHECK-NEXT: vmov q0[3], q0[1], r3, r1293; CHECK-NEXT: bx lr294entry:295 %0 = ashr <2 x i64> %src1, <i64 4, i64 4>296 ret <2 x i64> %0297}298 299 300define arm_aapcs_vfpcc <16 x i8> @shl_qr_int8_t(<16 x i8> %src1, i8 %src2) {301; CHECK-LABEL: shl_qr_int8_t:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: vshl.u8 q0, r0304; CHECK-NEXT: bx lr305entry:306 %i = insertelement <16 x i8> undef, i8 %src2, i32 0307 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer308 %0 = shl <16 x i8> %src1, %s309 ret <16 x i8> %0310}311 312define arm_aapcs_vfpcc <8 x i16> @shl_qr_int16_t(<8 x i16> %src1, i16 %src2) {313; CHECK-LABEL: shl_qr_int16_t:314; CHECK: @ %bb.0: @ %entry315; CHECK-NEXT: vshl.u16 q0, r0316; CHECK-NEXT: bx lr317entry:318 %i = insertelement <8 x i16> undef, i16 %src2, i32 0319 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer320 %0 = shl <8 x i16> %src1, %s321 ret <8 x i16> %0322}323 324define arm_aapcs_vfpcc <4 x i32> @shl_qr_int32_t(<4 x i32> %src1, i32 %src2) {325; CHECK-LABEL: shl_qr_int32_t:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vshl.u32 q0, r0328; CHECK-NEXT: bx lr329entry:330 %i = insertelement <4 x i32> undef, i32 %src2, i32 0331 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer332 %0 = shl <4 x i32> %src1, %s333 ret <4 x i32> %0334}335 336define arm_aapcs_vfpcc <2 x i64> @shl_qr_int64_t(<2 x i64> %src1, i64 %src2) {337; CHECK-LABEL: shl_qr_int64_t:338; CHECK: @ %bb.0: @ %entry339; CHECK-NEXT: vmov r12, r1, d1340; CHECK-NEXT: vmov r2, r3, d0341; CHECK-NEXT: lsll r12, r1, r0342; CHECK-NEXT: lsll r2, r3, r0343; CHECK-NEXT: vmov q0[2], q0[0], r2, r12344; CHECK-NEXT: vmov q0[3], q0[1], r3, r1345; CHECK-NEXT: bx lr346entry:347 %i = insertelement <2 x i64> undef, i64 %src2, i32 0348 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer349 %0 = shl <2 x i64> %src1, %s350 ret <2 x i64> %0351}352 353 354define arm_aapcs_vfpcc <16 x i8> @shru_qr_int8_t(<16 x i8> %src1, i8 %src2) {355; CHECK-LABEL: shru_qr_int8_t:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: rsbs r0, r0, #0358; CHECK-NEXT: vshl.u8 q0, r0359; CHECK-NEXT: bx lr360entry:361 %i = insertelement <16 x i8> undef, i8 %src2, i32 0362 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer363 %0 = lshr <16 x i8> %src1, %s364 ret <16 x i8> %0365}366 367define arm_aapcs_vfpcc <8 x i16> @shru_qr_int16_t(<8 x i16> %src1, i16 %src2) {368; CHECK-LABEL: shru_qr_int16_t:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: rsbs r0, r0, #0371; CHECK-NEXT: vshl.u16 q0, r0372; CHECK-NEXT: bx lr373entry:374 %i = insertelement <8 x i16> undef, i16 %src2, i32 0375 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer376 %0 = lshr <8 x i16> %src1, %s377 ret <8 x i16> %0378}379 380define arm_aapcs_vfpcc <4 x i32> @shru_qr_int32_t(<4 x i32> %src1, i32 %src2) {381; CHECK-LABEL: shru_qr_int32_t:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: rsbs r0, r0, #0384; CHECK-NEXT: vshl.u32 q0, r0385; CHECK-NEXT: bx lr386entry:387 %i = insertelement <4 x i32> undef, i32 %src2, i32 0388 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer389 %0 = lshr <4 x i32> %src1, %s390 ret <4 x i32> %0391}392 393define arm_aapcs_vfpcc <2 x i64> @shru_qr_int64_t(<2 x i64> %src1, i64 %src2) {394; CHECK-LABEL: shru_qr_int64_t:395; CHECK: @ %bb.0: @ %entry396; CHECK-NEXT: .save {r5, lr}397; CHECK-NEXT: push {r5, lr}398; CHECK-NEXT: rsbs r3, r0, #0399; CHECK-NEXT: vmov r2, r1, d1400; CHECK-NEXT: vmov r0, r5, d0401; CHECK-NEXT: lsll r2, r1, r3402; CHECK-NEXT: lsll r0, r5, r3403; CHECK-NEXT: vmov q0[2], q0[0], r0, r2404; CHECK-NEXT: vmov q0[3], q0[1], r5, r1405; CHECK-NEXT: pop {r5, pc}406entry:407 %i = insertelement <2 x i64> undef, i64 %src2, i32 0408 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer409 %0 = lshr <2 x i64> %src1, %s410 ret <2 x i64> %0411}412 413 414define arm_aapcs_vfpcc <16 x i8> @shrs_qr_int8_t(<16 x i8> %src1, i8 %src2) {415; CHECK-LABEL: shrs_qr_int8_t:416; CHECK: @ %bb.0: @ %entry417; CHECK-NEXT: rsbs r0, r0, #0418; CHECK-NEXT: vshl.s8 q0, r0419; CHECK-NEXT: bx lr420entry:421 %i = insertelement <16 x i8> undef, i8 %src2, i32 0422 %s = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer423 %0 = ashr <16 x i8> %src1, %s424 ret <16 x i8> %0425}426 427define arm_aapcs_vfpcc <8 x i16> @shrs_qr_int16_t(<8 x i16> %src1, i16 %src2) {428; CHECK-LABEL: shrs_qr_int16_t:429; CHECK: @ %bb.0: @ %entry430; CHECK-NEXT: rsbs r0, r0, #0431; CHECK-NEXT: vshl.s16 q0, r0432; CHECK-NEXT: bx lr433entry:434 %i = insertelement <8 x i16> undef, i16 %src2, i32 0435 %s = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer436 %0 = ashr <8 x i16> %src1, %s437 ret <8 x i16> %0438}439 440define arm_aapcs_vfpcc <4 x i32> @shrs_qr_int32_t(<4 x i32> %src1, i32 %src2) {441; CHECK-LABEL: shrs_qr_int32_t:442; CHECK: @ %bb.0: @ %entry443; CHECK-NEXT: rsbs r0, r0, #0444; CHECK-NEXT: vshl.s32 q0, r0445; CHECK-NEXT: bx lr446entry:447 %i = insertelement <4 x i32> undef, i32 %src2, i32 0448 %s = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer449 %0 = ashr <4 x i32> %src1, %s450 ret <4 x i32> %0451}452 453define arm_aapcs_vfpcc <2 x i64> @shrs_qr_int64_t(<2 x i64> %src1, i64 %src2) {454; CHECK-LABEL: shrs_qr_int64_t:455; CHECK: @ %bb.0: @ %entry456; CHECK-NEXT: vmov r12, r1, d1457; CHECK-NEXT: vmov r2, r3, d0458; CHECK-NEXT: asrl r12, r1, r0459; CHECK-NEXT: asrl r2, r3, r0460; CHECK-NEXT: vmov q0[2], q0[0], r2, r12461; CHECK-NEXT: vmov q0[3], q0[1], r3, r1462; CHECK-NEXT: bx lr463entry:464 %i = insertelement <2 x i64> undef, i64 %src2, i32 0465 %s = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer466 %0 = ashr <2 x i64> %src1, %s467 ret <2 x i64> %0468}469 470define arm_aapcs_vfpcc <16 x i8> @shl_qiv_int8_t(<16 x i8> %src1) {471; CHECK-LABEL: shl_qiv_int8_t:472; CHECK: @ %bb.0: @ %entry473; CHECK-NEXT: movw r0, #513474; CHECK-NEXT: movt r0, #1027475; CHECK-NEXT: vdup.32 q1, r0476; CHECK-NEXT: vshl.u8 q0, q0, q1477; CHECK-NEXT: bx lr478entry:479 %0 = shl <16 x i8> %src1, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>480 ret <16 x i8> %0481}482 483define arm_aapcs_vfpcc <8 x i16> @shl_qiv_int16_t(<8 x i16> %src1) {484; CHECK-LABEL: shl_qiv_int16_t:485; CHECK: @ %bb.0: @ %entry486; CHECK-NEXT: adr r0, .LCPI37_0487; CHECK-NEXT: vldrw.u32 q1, [r0]488; CHECK-NEXT: vshl.u16 q0, q0, q1489; CHECK-NEXT: bx lr490; CHECK-NEXT: .p2align 4491; CHECK-NEXT: @ %bb.1:492; CHECK-NEXT: .LCPI37_0:493; CHECK-NEXT: .short 1 @ 0x1494; CHECK-NEXT: .short 2 @ 0x2495; CHECK-NEXT: .short 3 @ 0x3496; CHECK-NEXT: .short 4 @ 0x4497; CHECK-NEXT: .short 1 @ 0x1498; CHECK-NEXT: .short 2 @ 0x2499; CHECK-NEXT: .short 3 @ 0x3500; CHECK-NEXT: .short 4 @ 0x4501entry:502 %0 = shl <8 x i16> %src1, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>503 ret <8 x i16> %0504}505 506define arm_aapcs_vfpcc <4 x i32> @shl_qiv_int32_t(<4 x i32> %src1) {507; CHECK-LABEL: shl_qiv_int32_t:508; CHECK: @ %bb.0: @ %entry509; CHECK-NEXT: adr r0, .LCPI38_0510; CHECK-NEXT: vldrw.u32 q1, [r0]511; CHECK-NEXT: vshl.u32 q0, q0, q1512; CHECK-NEXT: bx lr513; CHECK-NEXT: .p2align 4514; CHECK-NEXT: @ %bb.1:515; CHECK-NEXT: .LCPI38_0:516; CHECK-NEXT: .long 1 @ 0x1517; CHECK-NEXT: .long 2 @ 0x2518; CHECK-NEXT: .long 3 @ 0x3519; CHECK-NEXT: .long 4 @ 0x4520entry:521 %0 = shl <4 x i32> %src1, <i32 1, i32 2, i32 3, i32 4>522 ret <4 x i32> %0523}524