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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LV3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LV,CHECKFP4; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LIS5; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LIS,CHECKFP6 7define arm_aapcs_vfpcc <4 x i32> @shuffle1_i32(<4 x i32> %src) {8; CHECK-LABEL: shuffle1_i32:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: vmov.f32 s4, s311; CHECK-NEXT: vmov.f32 s5, s212; CHECK-NEXT: vmov.f32 s6, s113; CHECK-NEXT: vmov.f32 s7, s014; CHECK-NEXT: vmov q0, q115; CHECK-NEXT: bx lr16entry:17 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>18 ret <4 x i32> %out19}20 21define arm_aapcs_vfpcc <4 x i32> @shuffle2_i32(<4 x i32> %src) {22; CHECK-LABEL: shuffle2_i32:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: bx lr25entry:26 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>27 ret <4 x i32> %out28}29 30define arm_aapcs_vfpcc <4 x i32> @shuffle3_i32(<4 x i32> %src) {31; CHECK-LABEL: shuffle3_i32:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vmov.f32 s4, s334; CHECK-NEXT: vmov.f32 s5, s135; CHECK-NEXT: vmov.f32 s6, s236; CHECK-NEXT: vmov.f32 s7, s037; CHECK-NEXT: vmov q0, q138; CHECK-NEXT: bx lr39entry:40 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0>41 ret <4 x i32> %out42}43 44define arm_aapcs_vfpcc <4 x i32> @shuffle5_i32(<4 x i32> %src) {45; CHECK-LABEL: shuffle5_i32:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vrev64.32 q1, q048; CHECK-NEXT: vmov q0, q149; CHECK-NEXT: bx lr50entry:51 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>52 ret <4 x i32> %out53}54 55define arm_aapcs_vfpcc <4 x i32> @shuffle6_i32(<4 x i32> %src) {56; CHECK-LABEL: shuffle6_i32:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: bx lr59entry:60 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 3>61 ret <4 x i32> %out62}63 64define arm_aapcs_vfpcc <4 x i32> @oneoff11_i32(<4 x i32> %src1, <4 x i32> %src2) {65; CHECK-LABEL: oneoff11_i32:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vmov.f32 s2, s168; CHECK-NEXT: bx lr69entry:70 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>71 ret <4 x i32> %out72}73 74define arm_aapcs_vfpcc <4 x i32> @oneoff12_i32(<4 x i32> %src1, <4 x i32> %src2) {75; CHECK-LABEL: oneoff12_i32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vmov.f32 s0, s478; CHECK-NEXT: bx lr79entry:80 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>81 ret <4 x i32> %out82}83 84define arm_aapcs_vfpcc <4 x i32> @oneoff21_i32(<4 x i32> %src1, <4 x i32> %src2) {85; CHECK-LABEL: oneoff21_i32:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vmov.f32 s7, s088; CHECK-NEXT: vmov q0, q189; CHECK-NEXT: bx lr90entry:91 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 6, i32 0>92 ret <4 x i32> %out93}94 95define arm_aapcs_vfpcc <4 x i32> @oneoff22_i32(<4 x i32> %src1, <4 x i32> %src2) {96; CHECK-LABEL: oneoff22_i32:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vmov q0, q199; CHECK-NEXT: vmov.f32 s2, s0100; CHECK-NEXT: bx lr101entry:102 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7>103 ret <4 x i32> %out104}105 106define arm_aapcs_vfpcc <4 x i32> @oneoffundef_i32(<4 x i32> %src1, <4 x i32> %src2) {107; CHECK-LABEL: oneoffundef_i32:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmov.f32 s1, s4110; CHECK-NEXT: bx lr111entry:112 %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 undef, i32 3>113 ret <4 x i32> %out114}115 116define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) {117; CHECK-LABEL: shuffle2step_i32:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vmov.f32 s8, s1120; CHECK-NEXT: vmov.f32 s9, s3121; CHECK-NEXT: vmov.f32 s1, s2122; CHECK-NEXT: vmov.f32 s10, s5123; CHECK-NEXT: vmov.f32 s11, s7124; CHECK-NEXT: vmov.f32 s2, s4125; CHECK-NEXT: vmov.f32 s3, s6126; CHECK-NEXT: vadd.i32 q0, q0, q2127; CHECK-NEXT: bx lr128entry:129 %s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>130 %s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>131 %r = add <4 x i32> %s1, %s2132 ret <4 x i32> %r133}134 135define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {136; CHECK-LABEL: shuffle3step_i32:137; CHECK: @ %bb.0: @ %entry138; CHECK-NEXT: .vsave {d8, d9}139; CHECK-NEXT: vpush {d8, d9}140; CHECK-NEXT: vmov.f32 s13, s4141; CHECK-NEXT: vmov.f32 s14, s7142; CHECK-NEXT: vmov.f32 s18, s6143; CHECK-NEXT: vmov.f32 s12, s1144; CHECK-NEXT: vmov.f32 s15, s10145; CHECK-NEXT: vmov.f32 s16, s0146; CHECK-NEXT: vmov.f32 s17, s3147; CHECK-NEXT: vmov.f32 s19, s9148; CHECK-NEXT: vadd.i32 q3, q4, q3149; CHECK-NEXT: vmov.f32 s4, s2150; CHECK-NEXT: vmov.f32 s6, s8151; CHECK-NEXT: vmov.f32 s7, s11152; CHECK-NEXT: vadd.i32 q0, q3, q1153; CHECK-NEXT: vpop {d8, d9}154; CHECK-NEXT: bx lr155entry:156 %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>157 %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>158 %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>159 %a = add <4 x i32> %s1, %s2160 %r = add <4 x i32> %a, %s3161 ret <4 x i32> %r162}163 164define arm_aapcs_vfpcc <4 x i32> @shuffle4step_i32(<16 x i32> %src) {165; CHECK-LABEL: shuffle4step_i32:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: .vsave {d8, d9, d10, d11}168; CHECK-NEXT: vpush {d8, d9, d10, d11}169; CHECK-NEXT: vmov.f32 s16, s3170; CHECK-NEXT: vmov.f32 s20, s2171; CHECK-NEXT: vmov.f32 s17, s7172; CHECK-NEXT: vmov.f32 s18, s11173; CHECK-NEXT: vmov.f32 s19, s15174; CHECK-NEXT: vmov.f32 s21, s6175; CHECK-NEXT: vmov.f32 s22, s10176; CHECK-NEXT: vmov.f32 s23, s14177; CHECK-NEXT: vadd.i32 q4, q5, q4178; CHECK-NEXT: vmov.f32 s20, s1179; CHECK-NEXT: vmov.f32 s21, s5180; CHECK-NEXT: vmov.f32 s22, s9181; CHECK-NEXT: vmov.f32 s23, s13182; CHECK-NEXT: vmov.f32 s1, s4183; CHECK-NEXT: vmov.f32 s2, s8184; CHECK-NEXT: vmov.f32 s3, s12185; CHECK-NEXT: vadd.i32 q0, q0, q5186; CHECK-NEXT: vadd.i32 q0, q0, q4187; CHECK-NEXT: vpop {d8, d9, d10, d11}188; CHECK-NEXT: bx lr189entry:190 %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>191 %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>192 %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>193 %s4 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>194 %a1 = add <4 x i32> %s1, %s2195 %a2 = add <4 x i32> %s3, %s4196 %r = add <4 x i32> %a1, %a2197 ret <4 x i32> %r198}199 200; i16201 202define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) {203; CHECK-LABEL: shuffle1_i16:204; CHECK: @ %bb.0: @ %entry205; CHECK-NEXT: vrev64.16 q1, q0206; CHECK-NEXT: vmov.f32 s0, s6207; CHECK-NEXT: vmov.f32 s1, s7208; CHECK-NEXT: vmov.f32 s2, s4209; CHECK-NEXT: vmov.f32 s3, s5210; CHECK-NEXT: bx lr211entry:212 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>213 ret <8 x i16> %out214}215 216define arm_aapcs_vfpcc <8 x i16> @shuffle2_i16(<8 x i16> %src) {217; CHECK-LABEL: shuffle2_i16:218; CHECK: @ %bb.0: @ %entry219; CHECK-NEXT: bx lr220entry:221 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>222 ret <8 x i16> %out223}224 225define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) {226; CHECK-LV-LABEL: shuffle3_i16:227; CHECK-LV: @ %bb.0: @ %entry228; CHECK-LV-NEXT: vmovx.f16 s5, s3229; CHECK-LV-NEXT: vmovx.f16 s6, s1230; CHECK-LV-NEXT: vmovx.f16 s4, s0231; CHECK-LV-NEXT: vins.f16 s1, s0232; CHECK-LV-NEXT: vins.f16 s6, s4233; CHECK-LV-NEXT: vins.f16 s5, s3234; CHECK-LV-NEXT: vmov.f32 s4, s2235; CHECK-LV-NEXT: vmov.f32 s7, s1236; CHECK-LV-NEXT: vmov q0, q1237; CHECK-LV-NEXT: bx lr238;239; CHECK-LIS-LABEL: shuffle3_i16:240; CHECK-LIS: @ %bb.0: @ %entry241; CHECK-LIS-NEXT: vmov q1, q0242; CHECK-LIS-NEXT: vmovx.f16 s2, s5243; CHECK-LIS-NEXT: vmovx.f16 s0, s4244; CHECK-LIS-NEXT: vins.f16 s5, s4245; CHECK-LIS-NEXT: vins.f16 s2, s0246; CHECK-LIS-NEXT: vmov.f32 s0, s6247; CHECK-LIS-NEXT: vmovx.f16 s1, s7248; CHECK-LIS-NEXT: vmov.f32 s3, s5249; CHECK-LIS-NEXT: vins.f16 s1, s7250; CHECK-LIS-NEXT: bx lr251 252entry:253 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>254 ret <8 x i16> %out255}256 257define arm_aapcs_vfpcc <8 x i16> @shuffle5_i16(<8 x i16> %src) {258; CHECK-LABEL: shuffle5_i16:259; CHECK: @ %bb.0: @ %entry260; CHECK-NEXT: vrev64.16 q1, q0261; CHECK-NEXT: vmov q0, q1262; CHECK-NEXT: bx lr263entry:264 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>265 ret <8 x i16> %out266}267 268define arm_aapcs_vfpcc <8 x i16> @shuffle6_i16(<8 x i16> %src) {269; CHECK-LABEL: shuffle6_i16:270; CHECK: @ %bb.0: @ %entry271; CHECK-NEXT: vrev32.16 q0, q0272; CHECK-NEXT: bx lr273entry:274 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>275 ret <8 x i16> %out276}277 278define arm_aapcs_vfpcc <8 x i16> @oneoff11_i16(<8 x i16> %src1, <8 x i16> %src2) {279; CHECK-LABEL: oneoff11_i16:280; CHECK: @ %bb.0: @ %entry281; CHECK-NEXT: vmov.u16 r0, q0[1]282; CHECK-NEXT: vmov.16 q0[2], r0283; CHECK-NEXT: bx lr284entry:285 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>286 ret <8 x i16> %out287}288 289define arm_aapcs_vfpcc <8 x i16> @oneoff12_i16(<8 x i16> %src1, <8 x i16> %src2) {290; CHECK-LABEL: oneoff12_i16:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vmov.u16 r0, q1[0]293; CHECK-NEXT: vmov.16 q0[0], r0294; CHECK-NEXT: bx lr295entry:296 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>297 ret <8 x i16> %out298}299 300define arm_aapcs_vfpcc <8 x i16> @oneoff21_i16(<8 x i16> %src1, <8 x i16> %src2) {301; CHECK-LABEL: oneoff21_i16:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: vins.f16 s5, s0304; CHECK-NEXT: vmov q0, q1305; CHECK-NEXT: bx lr306entry:307 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>308 ret <8 x i16> %out309}310 311define arm_aapcs_vfpcc <8 x i16> @oneoff22_i16(<8 x i16> %src1, <8 x i16> %src2) {312; CHECK-LABEL: oneoff22_i16:313; CHECK: @ %bb.0: @ %entry314; CHECK-NEXT: vmov q0, q1315; CHECK-NEXT: vmov.u16 r0, q1[6]316; CHECK-NEXT: vmov.16 q0[0], r0317; CHECK-NEXT: bx lr318entry:319 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>320 ret <8 x i16> %out321}322 323define arm_aapcs_vfpcc <8 x i16> @oneoffundef_i16(<8 x i16> %src1, <8 x i16> %src2) {324; CHECK-LABEL: oneoffundef_i16:325; CHECK: @ %bb.0: @ %entry326; CHECK-NEXT: vmov.u16 r0, q0[3]327; CHECK-NEXT: vmov.16 q1[5], r0328; CHECK-NEXT: vmov q0, q1329; CHECK-NEXT: bx lr330entry:331 %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 undef, i32 undef, i32 12, i32 3, i32 14, i32 15>332 ret <8 x i16> %out333}334 335define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) {336; CHECK-LABEL: shuffle2step_i16:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: .pad #32339; CHECK-NEXT: sub sp, #32340; CHECK-NEXT: mov r0, sp341; CHECK-NEXT: vshr.u32 q2, q1, #16342; CHECK-NEXT: vstrh.32 q2, [r0, #8]343; CHECK-NEXT: vshr.u32 q2, q0, #16344; CHECK-NEXT: add r1, sp, #16345; CHECK-NEXT: vstrh.32 q2, [r0]346; CHECK-NEXT: vstrh.32 q1, [r1, #8]347; CHECK-NEXT: vstrh.32 q0, [r1]348; CHECK-NEXT: vldrw.u32 q0, [r0]349; CHECK-NEXT: vldrw.u32 q1, [r1]350; CHECK-NEXT: vadd.i16 q0, q1, q0351; CHECK-NEXT: add sp, #32352; CHECK-NEXT: bx lr353entry:354 %s1 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>355 %s2 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>356 %r = add <8 x i16> %s1, %s2357 ret <8 x i16> %r358}359 360define arm_aapcs_vfpcc <8 x i16> @shuffle3step_i16(<32 x i16> %src) {361; CHECK-LABEL: shuffle3step_i16:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: .vsave {d8, d9}364; CHECK-NEXT: vpush {d8, d9}365; CHECK-NEXT: vmovx.f16 s12, s0366; CHECK-NEXT: vmov.f32 s16, s1367; CHECK-NEXT: vins.f16 s12, s2368; CHECK-NEXT: vmovx.f16 s2, s2369; CHECK-NEXT: vins.f16 s16, s2370; CHECK-NEXT: vmovx.f16 s2, s5371; CHECK-NEXT: vmov.f32 s17, s4372; CHECK-NEXT: vmovx.f16 s14, s6373; CHECK-NEXT: vins.f16 s17, s2374; CHECK-NEXT: vmovx.f16 s2, s8375; CHECK-NEXT: vmov.f32 s18, s7376; CHECK-NEXT: vins.f16 s14, s8377; CHECK-NEXT: vins.f16 s18, s2378; CHECK-NEXT: vmovx.f16 s2, s11379; CHECK-NEXT: vmovx.f16 s8, s10380; CHECK-NEXT: vins.f16 s10, s2381; CHECK-NEXT: vmovx.f16 s2, s1382; CHECK-NEXT: vmovx.f16 s13, s3383; CHECK-NEXT: vins.f16 s0, s2384; CHECK-NEXT: vmovx.f16 s2, s4385; CHECK-NEXT: vins.f16 s3, s2386; CHECK-NEXT: vmovx.f16 s2, s7387; CHECK-NEXT: vmovx.f16 s15, s9388; CHECK-NEXT: vins.f16 s6, s2389; CHECK-NEXT: vins.f16 s9, s8390; CHECK-NEXT: vmov.f32 s1, s3391; CHECK-NEXT: vins.f16 s15, s11392; CHECK-NEXT: vins.f16 s13, s5393; CHECK-NEXT: vmov.f32 s2, s6394; CHECK-NEXT: vmov.f32 s3, s9395; CHECK-NEXT: vmov.f32 s19, s10396; CHECK-NEXT: vadd.i16 q0, q0, q3397; CHECK-NEXT: vadd.i16 q0, q0, q4398; CHECK-NEXT: vpop {d8, d9}399; CHECK-NEXT: bx lr400entry:401 %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>402 %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>403 %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>404 %a = add <8 x i16> %s1, %s2405 %r = add <8 x i16> %a, %s3406 ret <8 x i16> %r407}408 409define arm_aapcs_vfpcc <8 x i16> @shuffle4step_i16(<32 x i16> %src) {410; CHECK-LABEL: shuffle4step_i16:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: .vsave {d8, d9, d10, d11}413; CHECK-NEXT: vpush {d8, d9, d10, d11}414; CHECK-NEXT: vmovx.f16 s18, s9415; CHECK-NEXT: vmovx.f16 s16, s11416; CHECK-NEXT: vins.f16 s18, s16417; CHECK-NEXT: vmovx.f16 s19, s13418; CHECK-NEXT: vmovx.f16 s16, s15419; CHECK-NEXT: vmovx.f16 s20, s3420; CHECK-NEXT: vins.f16 s19, s16421; CHECK-NEXT: vmovx.f16 s16, s1422; CHECK-NEXT: vins.f16 s16, s20423; CHECK-NEXT: vmovx.f16 s17, s5424; CHECK-NEXT: vmovx.f16 s20, s7425; CHECK-NEXT: vins.f16 s9, s11426; CHECK-NEXT: vins.f16 s13, s15427; CHECK-NEXT: vins.f16 s5, s7428; CHECK-NEXT: vins.f16 s1, s3429; CHECK-NEXT: vins.f16 s17, s20430; CHECK-NEXT: vmov.f32 s20, s1431; CHECK-NEXT: vmovx.f16 s1, s10432; CHECK-NEXT: vmov.f32 s22, s9433; CHECK-NEXT: vmov.f32 s21, s5434; CHECK-NEXT: vmov.f32 s23, s13435; CHECK-NEXT: vadd.i16 q4, q5, q4436; CHECK-NEXT: vmovx.f16 s22, s8437; CHECK-NEXT: vins.f16 s22, s1438; CHECK-NEXT: vmovx.f16 s23, s12439; CHECK-NEXT: vmovx.f16 s1, s14440; CHECK-NEXT: vmovx.f16 s20, s0441; CHECK-NEXT: vins.f16 s23, s1442; CHECK-NEXT: vmov.f32 s1, s2443; CHECK-NEXT: vmovx.f16 s2, s2444; CHECK-NEXT: vmovx.f16 s21, s4445; CHECK-NEXT: vins.f16 s20, s2446; CHECK-NEXT: vmovx.f16 s2, s6447; CHECK-NEXT: vins.f16 s12, s14448; CHECK-NEXT: vins.f16 s8, s10449; CHECK-NEXT: vins.f16 s4, s6450; CHECK-NEXT: vins.f16 s21, s2451; CHECK-NEXT: vins.f16 s0, s1452; CHECK-NEXT: vmov.f32 s2, s8453; CHECK-NEXT: vmov.f32 s1, s4454; CHECK-NEXT: vmov.f32 s3, s12455; CHECK-NEXT: vadd.i16 q0, q0, q5456; CHECK-NEXT: vadd.i16 q0, q0, q4457; CHECK-NEXT: vpop {d8, d9, d10, d11}458; CHECK-NEXT: bx lr459entry:460 %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>461 %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>462 %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>463 %s4 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>464 %a1 = add <8 x i16> %s1, %s2465 %a2 = add <8 x i16> %s3, %s4466 %r = add <8 x i16> %a1, %a2467 ret <8 x i16> %r468}469 470; i8471 472define arm_aapcs_vfpcc <16 x i8> @shuffle1_i8(<16 x i8> %src) {473; CHECK-LABEL: shuffle1_i8:474; CHECK: @ %bb.0: @ %entry475; CHECK-NEXT: vrev64.8 q1, q0476; CHECK-NEXT: vmov.f32 s0, s6477; CHECK-NEXT: vmov.f32 s1, s7478; CHECK-NEXT: vmov.f32 s2, s4479; CHECK-NEXT: vmov.f32 s3, s5480; CHECK-NEXT: bx lr481entry:482 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>483 ret <16 x i8> %out484}485 486define arm_aapcs_vfpcc <16 x i8> @shuffle2_i8(<16 x i8> %src) {487; CHECK-LABEL: shuffle2_i8:488; CHECK: @ %bb.0: @ %entry489; CHECK-NEXT: bx lr490entry:491 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>492 ret <16 x i8> %out493}494 495define arm_aapcs_vfpcc <16 x i8> @shuffle3_i8(<16 x i8> %src) {496; CHECK-LABEL: shuffle3_i8:497; CHECK: @ %bb.0: @ %entry498; CHECK-NEXT: vmov q1, q0499; CHECK-NEXT: vmov.u8 r0, q0[4]500; CHECK-NEXT: vmov.8 q0[0], r0501; CHECK-NEXT: vmov.u8 r0, q1[5]502; CHECK-NEXT: vmov.8 q0[1], r0503; CHECK-NEXT: vmov.u8 r0, q1[15]504; CHECK-NEXT: vmov.8 q0[2], r0505; CHECK-NEXT: vmov.u8 r0, q1[7]506; CHECK-NEXT: vmov.8 q0[3], r0507; CHECK-NEXT: vmov.u8 r0, q1[14]508; CHECK-NEXT: vmov.8 q0[4], r0509; CHECK-NEXT: vmov.u8 r0, q1[9]510; CHECK-NEXT: vmov.8 q0[5], r0511; CHECK-NEXT: vmov.u8 r0, q1[6]512; CHECK-NEXT: vmov.8 q0[6], r0513; CHECK-NEXT: vmov.u8 r0, q1[3]514; CHECK-NEXT: vmov.8 q0[7], r0515; CHECK-NEXT: vmov.u8 r0, q1[10]516; CHECK-NEXT: vmov.8 q0[8], r0517; CHECK-NEXT: vmov.u8 r0, q1[12]518; CHECK-NEXT: vmov.8 q0[9], r0519; CHECK-NEXT: vmov.u8 r0, q1[1]520; CHECK-NEXT: vmov.8 q0[10], r0521; CHECK-NEXT: vmov.u8 r0, q1[13]522; CHECK-NEXT: vmov.8 q0[11], r0523; CHECK-NEXT: vmov.u8 r0, q1[2]524; CHECK-NEXT: vmov.8 q0[12], r0525; CHECK-NEXT: vmov.u8 r0, q1[8]526; CHECK-NEXT: vmov.8 q0[13], r0527; CHECK-NEXT: vmov.u8 r0, q1[0]528; CHECK-NEXT: vmov.8 q0[14], r0529; CHECK-NEXT: vmov.u8 r0, q1[11]530; CHECK-NEXT: vmov.8 q0[15], r0531; CHECK-NEXT: bx lr532entry:533 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 15, i32 7, i32 14, i32 9, i32 6, i32 3, i32 10, i32 12, i32 1, i32 13, i32 2, i32 8, i32 0, i32 11>534 ret <16 x i8> %out535}536 537define arm_aapcs_vfpcc <16 x i8> @shuffle5_i8(<16 x i8> %src) {538; CHECK-LABEL: shuffle5_i8:539; CHECK: @ %bb.0: @ %entry540; CHECK-NEXT: vrev64.8 q1, q0541; CHECK-NEXT: vmov q0, q1542; CHECK-NEXT: bx lr543entry:544 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>545 ret <16 x i8> %out546}547 548define arm_aapcs_vfpcc <16 x i8> @shuffle6_i8(<16 x i8> %src) {549; CHECK-LABEL: shuffle6_i8:550; CHECK: @ %bb.0: @ %entry551; CHECK-NEXT: vrev32.8 q0, q0552; CHECK-NEXT: bx lr553entry:554 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>555 ret <16 x i8> %out556}557 558define arm_aapcs_vfpcc <16 x i8> @shuffle7_i8(<16 x i8> %src) {559; CHECK-LABEL: shuffle7_i8:560; CHECK: @ %bb.0: @ %entry561; CHECK-NEXT: vrev16.8 q0, q0562; CHECK-NEXT: bx lr563entry:564 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>565 ret <16 x i8> %out566}567 568define arm_aapcs_vfpcc <16 x i8> @oneoff11_i8(<16 x i8> %src1, <16 x i8> %src2) {569; CHECK-LABEL: oneoff11_i8:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: vmov.u8 r0, q0[1]572; CHECK-NEXT: vmov.8 q0[2], r0573; CHECK-NEXT: bx lr574entry:575 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>576 ret <16 x i8> %out577}578 579define arm_aapcs_vfpcc <16 x i8> @oneoff12_i8(<16 x i8> %src1, <16 x i8> %src2) {580; CHECK-LABEL: oneoff12_i8:581; CHECK: @ %bb.0: @ %entry582; CHECK-NEXT: vmov.u8 r0, q1[4]583; CHECK-NEXT: vmov.8 q0[0], r0584; CHECK-NEXT: bx lr585entry:586 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 20, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>587 ret <16 x i8> %out588}589 590define arm_aapcs_vfpcc <16 x i8> @oneoff21_i8(<16 x i8> %src1, <16 x i8> %src2) {591; CHECK-LABEL: oneoff21_i8:592; CHECK: @ %bb.0: @ %entry593; CHECK-NEXT: vmov.u8 r0, q0[0]594; CHECK-NEXT: vmov.8 q1[3], r0595; CHECK-NEXT: vmov q0, q1596; CHECK-NEXT: bx lr597entry:598 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 0, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>599 ret <16 x i8> %out600}601 602define arm_aapcs_vfpcc <16 x i8> @oneoff22_i8(<16 x i8> %src1, <16 x i8> %src2) {603; CHECK-LABEL: oneoff22_i8:604; CHECK: @ %bb.0: @ %entry605; CHECK-NEXT: vmov q0, q1606; CHECK-NEXT: vmov.u8 r0, q1[15]607; CHECK-NEXT: vmov.8 q0[9], r0608; CHECK-NEXT: bx lr609entry:610 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 31, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>611 ret <16 x i8> %out612}613 614define arm_aapcs_vfpcc <16 x i8> @oneoffundef_i8(<16 x i8> %src1, <16 x i8> %src2) {615; CHECK-LABEL: oneoffundef_i8:616; CHECK: @ %bb.0: @ %entry617; CHECK-NEXT: vmov.u8 r0, q0[2]618; CHECK-NEXT: vmov.8 q0[1], r0619; CHECK-NEXT: bx lr620entry:621 %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 undef, i32 2, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 undef, i32 13, i32 14, i32 15>622 ret <16 x i8> %out623}624 625define arm_aapcs_vfpcc <16 x i8> @shuffle2step_i8(<32 x i8> %src) {626; CHECK-LABEL: shuffle2step_i8:627; CHECK: @ %bb.0: @ %entry628; CHECK-NEXT: .pad #32629; CHECK-NEXT: sub sp, #32630; CHECK-NEXT: mov r0, sp631; CHECK-NEXT: vshr.u16 q2, q1, #8632; CHECK-NEXT: vstrb.16 q2, [r0, #8]633; CHECK-NEXT: vshr.u16 q2, q0, #8634; CHECK-NEXT: add r1, sp, #16635; CHECK-NEXT: vstrb.16 q2, [r0]636; CHECK-NEXT: vstrb.16 q1, [r1, #8]637; CHECK-NEXT: vstrb.16 q0, [r1]638; CHECK-NEXT: vldrw.u32 q0, [r0]639; CHECK-NEXT: vldrw.u32 q1, [r1]640; CHECK-NEXT: vadd.i8 q0, q1, q0641; CHECK-NEXT: add sp, #32642; CHECK-NEXT: bx lr643entry:644 %s1 = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>645 %s2 = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>646 %r = add <16 x i8> %s1, %s2647 ret <16 x i8> %r648}649 650define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) {651; CHECK-LABEL: shuffle3step_i8:652; CHECK: @ %bb.0: @ %entry653; CHECK-NEXT: .vsave {d8, d9, d10, d11}654; CHECK-NEXT: vpush {d8, d9, d10, d11}655; CHECK-NEXT: vmov.u8 r0, q0[1]656; CHECK-NEXT: vmov.8 q3[0], r0657; CHECK-NEXT: vmov.u8 r0, q0[4]658; CHECK-NEXT: vmov.8 q3[1], r0659; CHECK-NEXT: vmov.u8 r0, q0[7]660; CHECK-NEXT: vmov.8 q3[2], r0661; CHECK-NEXT: vmov.u8 r0, q0[10]662; CHECK-NEXT: vmov.8 q3[3], r0663; CHECK-NEXT: vmov.u8 r0, q0[13]664; CHECK-NEXT: vmov.8 q3[4], r0665; CHECK-NEXT: vmov.u8 r0, q1[0]666; CHECK-NEXT: vmov.8 q3[5], r0667; CHECK-NEXT: vmov.u8 r0, q1[3]668; CHECK-NEXT: vmov.8 q3[6], r0669; CHECK-NEXT: vmov.u8 r0, q1[9]670; CHECK-NEXT: vmov.8 q4[8], r0671; CHECK-NEXT: vmov.u8 r0, q1[12]672; CHECK-NEXT: vmov.8 q4[9], r0673; CHECK-NEXT: vmov.u8 r0, q1[15]674; CHECK-NEXT: vmov.8 q4[10], r0675; CHECK-NEXT: vmov.u8 r0, q2[2]676; CHECK-NEXT: vmov.8 q4[11], r0677; CHECK-NEXT: vmov.u8 r0, q2[5]678; CHECK-NEXT: vmov.8 q4[12], r0679; CHECK-NEXT: vmov.u8 r0, q2[8]680; CHECK-NEXT: vmov.8 q4[13], r0681; CHECK-NEXT: vmov.u8 r0, q2[11]682; CHECK-NEXT: vmov.8 q4[14], r0683; CHECK-NEXT: vmov.u8 r0, q2[14]684; CHECK-NEXT: vmov.8 q4[15], r0685; CHECK-NEXT: vmov.u8 r0, q1[6]686; CHECK-NEXT: vmov.8 q3[7], r0687; CHECK-NEXT: vmov.u8 r0, q0[0]688; CHECK-NEXT: vmov.f32 s14, s18689; CHECK-NEXT: vmov.f32 s15, s19690; CHECK-NEXT: vmov.8 q4[0], r0691; CHECK-NEXT: vmov.u8 r0, q0[3]692; CHECK-NEXT: vmov.8 q4[1], r0693; CHECK-NEXT: vmov.u8 r0, q0[6]694; CHECK-NEXT: vmov.8 q4[2], r0695; CHECK-NEXT: vmov.u8 r0, q0[9]696; CHECK-NEXT: vmov.8 q4[3], r0697; CHECK-NEXT: vmov.u8 r0, q0[12]698; CHECK-NEXT: vmov.8 q4[4], r0699; CHECK-NEXT: vmov.u8 r0, q0[15]700; CHECK-NEXT: vmov.8 q4[5], r0701; CHECK-NEXT: vmov.u8 r0, q1[2]702; CHECK-NEXT: vmov.8 q4[6], r0703; CHECK-NEXT: vmov.u8 r0, q1[8]704; CHECK-NEXT: vmov.8 q5[8], r0705; CHECK-NEXT: vmov.u8 r0, q1[11]706; CHECK-NEXT: vmov.8 q5[9], r0707; CHECK-NEXT: vmov.u8 r0, q1[14]708; CHECK-NEXT: vmov.8 q5[10], r0709; CHECK-NEXT: vmov.u8 r0, q2[1]710; CHECK-NEXT: vmov.8 q5[11], r0711; CHECK-NEXT: vmov.u8 r0, q2[4]712; CHECK-NEXT: vmov.8 q5[12], r0713; CHECK-NEXT: vmov.u8 r0, q2[7]714; CHECK-NEXT: vmov.8 q5[13], r0715; CHECK-NEXT: vmov.u8 r0, q2[10]716; CHECK-NEXT: vmov.8 q5[14], r0717; CHECK-NEXT: vmov.u8 r0, q2[13]718; CHECK-NEXT: vmov.8 q5[15], r0719; CHECK-NEXT: vmov.u8 r0, q1[5]720; CHECK-NEXT: vmov.8 q4[7], r0721; CHECK-NEXT: vmov.u8 r0, q0[2]722; CHECK-NEXT: vmov.f32 s18, s22723; CHECK-NEXT: vmov.f32 s19, s23724; CHECK-NEXT: vadd.i8 q3, q4, q3725; CHECK-NEXT: vmov.8 q4[0], r0726; CHECK-NEXT: vmov.u8 r0, q0[5]727; CHECK-NEXT: vmov.8 q4[1], r0728; CHECK-NEXT: vmov.u8 r0, q0[8]729; CHECK-NEXT: vmov.8 q4[2], r0730; CHECK-NEXT: vmov.u8 r0, q0[11]731; CHECK-NEXT: vmov.8 q4[3], r0732; CHECK-NEXT: vmov.u8 r0, q0[14]733; CHECK-NEXT: vmov.8 q4[4], r0734; CHECK-NEXT: vmov.u8 r0, q1[1]735; CHECK-NEXT: vmov.8 q4[5], r0736; CHECK-NEXT: vmov.u8 r0, q1[4]737; CHECK-NEXT: vmov.8 q4[6], r0738; CHECK-NEXT: vmov.u8 r0, q1[10]739; CHECK-NEXT: vmov.8 q0[8], r0740; CHECK-NEXT: vmov.u8 r0, q1[13]741; CHECK-NEXT: vmov.8 q0[9], r0742; CHECK-NEXT: vmov.u8 r0, q2[0]743; CHECK-NEXT: vmov.8 q0[10], r0744; CHECK-NEXT: vmov.u8 r0, q2[3]745; CHECK-NEXT: vmov.8 q0[11], r0746; CHECK-NEXT: vmov.u8 r0, q2[6]747; CHECK-NEXT: vmov.8 q0[12], r0748; CHECK-NEXT: vmov.u8 r0, q2[9]749; CHECK-NEXT: vmov.8 q0[13], r0750; CHECK-NEXT: vmov.u8 r0, q2[12]751; CHECK-NEXT: vmov.8 q0[14], r0752; CHECK-NEXT: vmov.u8 r0, q2[15]753; CHECK-NEXT: vmov.8 q0[15], r0754; CHECK-NEXT: vmov.u8 r0, q1[7]755; CHECK-NEXT: vmov.8 q4[7], r0756; CHECK-NEXT: vmov.f32 s18, s2757; CHECK-NEXT: vmov.f32 s19, s3758; CHECK-NEXT: vadd.i8 q0, q3, q4759; CHECK-NEXT: vpop {d8, d9, d10, d11}760; CHECK-NEXT: bx lr761entry:762 %s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>763 %s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>764 %s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>765 %a = add <16 x i8> %s1, %s2766 %r = add <16 x i8> %a, %s3767 ret <16 x i8> %r768}769 770define arm_aapcs_vfpcc <16 x i8> @shuffle4step_i8(<64 x i8> %src) {771; CHECK-LABEL: shuffle4step_i8:772; CHECK: @ %bb.0: @ %entry773; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}774; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}775; CHECK-NEXT: vmov.u8 r0, q0[3]776; CHECK-NEXT: vmov.8 q4[0], r0777; CHECK-NEXT: vmov.u8 r0, q0[7]778; CHECK-NEXT: vmov.8 q4[1], r0779; CHECK-NEXT: vmov.u8 r0, q0[11]780; CHECK-NEXT: vmov.8 q4[2], r0781; CHECK-NEXT: vmov.u8 r0, q0[15]782; CHECK-NEXT: vmov.8 q4[3], r0783; CHECK-NEXT: vmov.u8 r0, q1[3]784; CHECK-NEXT: vmov.8 q4[4], r0785; CHECK-NEXT: vmov.u8 r0, q1[7]786; CHECK-NEXT: vmov.8 q4[5], r0787; CHECK-NEXT: vmov.u8 r0, q1[11]788; CHECK-NEXT: vmov.8 q4[6], r0789; CHECK-NEXT: vmov.u8 r0, q2[3]790; CHECK-NEXT: vmov.8 q5[8], r0791; CHECK-NEXT: vmov.u8 r0, q2[7]792; CHECK-NEXT: vmov.8 q5[9], r0793; CHECK-NEXT: vmov.u8 r0, q2[11]794; CHECK-NEXT: vmov.8 q5[10], r0795; CHECK-NEXT: vmov.u8 r0, q2[15]796; CHECK-NEXT: vmov.8 q5[11], r0797; CHECK-NEXT: vmov.u8 r0, q3[3]798; CHECK-NEXT: vmov.8 q5[12], r0799; CHECK-NEXT: vmov.u8 r0, q3[7]800; CHECK-NEXT: vmov.8 q5[13], r0801; CHECK-NEXT: vmov.u8 r0, q3[11]802; CHECK-NEXT: vmov.8 q5[14], r0803; CHECK-NEXT: vmov.u8 r0, q3[15]804; CHECK-NEXT: vmov.8 q5[15], r0805; CHECK-NEXT: vmov.u8 r0, q1[15]806; CHECK-NEXT: vmov.8 q4[7], r0807; CHECK-NEXT: vmov.u8 r0, q0[2]808; CHECK-NEXT: vmov.f32 s18, s22809; CHECK-NEXT: vmov.f32 s19, s23810; CHECK-NEXT: vmov.8 q5[0], r0811; CHECK-NEXT: vmov.u8 r0, q0[6]812; CHECK-NEXT: vmov.8 q5[1], r0813; CHECK-NEXT: vmov.u8 r0, q0[10]814; CHECK-NEXT: vmov.8 q5[2], r0815; CHECK-NEXT: vmov.u8 r0, q0[14]816; CHECK-NEXT: vmov.8 q5[3], r0817; CHECK-NEXT: vmov.u8 r0, q1[2]818; CHECK-NEXT: vmov.8 q5[4], r0819; CHECK-NEXT: vmov.u8 r0, q1[6]820; CHECK-NEXT: vmov.8 q5[5], r0821; CHECK-NEXT: vmov.u8 r0, q1[10]822; CHECK-NEXT: vmov.8 q5[6], r0823; CHECK-NEXT: vmov.u8 r0, q2[2]824; CHECK-NEXT: vmov.8 q6[8], r0825; CHECK-NEXT: vmov.u8 r0, q2[6]826; CHECK-NEXT: vmov.8 q6[9], r0827; CHECK-NEXT: vmov.u8 r0, q2[10]828; CHECK-NEXT: vmov.8 q6[10], r0829; CHECK-NEXT: vmov.u8 r0, q2[14]830; CHECK-NEXT: vmov.8 q6[11], r0831; CHECK-NEXT: vmov.u8 r0, q3[2]832; CHECK-NEXT: vmov.8 q6[12], r0833; CHECK-NEXT: vmov.u8 r0, q3[6]834; CHECK-NEXT: vmov.8 q6[13], r0835; CHECK-NEXT: vmov.u8 r0, q3[10]836; CHECK-NEXT: vmov.8 q6[14], r0837; CHECK-NEXT: vmov.u8 r0, q3[14]838; CHECK-NEXT: vmov.8 q6[15], r0839; CHECK-NEXT: vmov.u8 r0, q1[14]840; CHECK-NEXT: vmov.8 q5[7], r0841; CHECK-NEXT: vmov.u8 r0, q0[1]842; CHECK-NEXT: vmov.f32 s22, s26843; CHECK-NEXT: vmov.f32 s23, s27844; CHECK-NEXT: vadd.i8 q4, q5, q4845; CHECK-NEXT: vmov.8 q5[0], r0846; CHECK-NEXT: vmov.u8 r0, q0[5]847; CHECK-NEXT: vmov.8 q5[1], r0848; CHECK-NEXT: vmov.u8 r0, q0[9]849; CHECK-NEXT: vmov.8 q5[2], r0850; CHECK-NEXT: vmov.u8 r0, q0[13]851; CHECK-NEXT: vmov.8 q5[3], r0852; CHECK-NEXT: vmov.u8 r0, q1[1]853; CHECK-NEXT: vmov.8 q5[4], r0854; CHECK-NEXT: vmov.u8 r0, q1[5]855; CHECK-NEXT: vmov.8 q5[5], r0856; CHECK-NEXT: vmov.u8 r0, q1[9]857; CHECK-NEXT: vmov.8 q5[6], r0858; CHECK-NEXT: vmov.u8 r0, q2[1]859; CHECK-NEXT: vmov.8 q6[8], r0860; CHECK-NEXT: vmov.u8 r0, q2[5]861; CHECK-NEXT: vmov.8 q6[9], r0862; CHECK-NEXT: vmov.u8 r0, q2[9]863; CHECK-NEXT: vmov.8 q6[10], r0864; CHECK-NEXT: vmov.u8 r0, q2[13]865; CHECK-NEXT: vmov.8 q6[11], r0866; CHECK-NEXT: vmov.u8 r0, q3[1]867; CHECK-NEXT: vmov.8 q6[12], r0868; CHECK-NEXT: vmov.u8 r0, q3[5]869; CHECK-NEXT: vmov.8 q6[13], r0870; CHECK-NEXT: vmov.u8 r0, q3[9]871; CHECK-NEXT: vmov.8 q6[14], r0872; CHECK-NEXT: vmov.u8 r0, q3[13]873; CHECK-NEXT: vmov.8 q6[15], r0874; CHECK-NEXT: vmov.u8 r0, q1[13]875; CHECK-NEXT: vmov.8 q5[7], r0876; CHECK-NEXT: vmov.u8 r0, q0[0]877; CHECK-NEXT: vmov.f32 s22, s26878; CHECK-NEXT: vmov.f32 s23, s27879; CHECK-NEXT: vmov.8 q6[0], r0880; CHECK-NEXT: vmov.u8 r0, q0[4]881; CHECK-NEXT: vmov.8 q6[1], r0882; CHECK-NEXT: vmov.u8 r0, q0[8]883; CHECK-NEXT: vmov.8 q6[2], r0884; CHECK-NEXT: vmov.u8 r0, q0[12]885; CHECK-NEXT: vmov.8 q6[3], r0886; CHECK-NEXT: vmov.u8 r0, q1[0]887; CHECK-NEXT: vmov.8 q6[4], r0888; CHECK-NEXT: vmov.u8 r0, q1[4]889; CHECK-NEXT: vmov.8 q6[5], r0890; CHECK-NEXT: vmov.u8 r0, q1[8]891; CHECK-NEXT: vmov.8 q6[6], r0892; CHECK-NEXT: vmov.u8 r0, q2[0]893; CHECK-NEXT: vmov.8 q0[8], r0894; CHECK-NEXT: vmov.u8 r0, q2[4]895; CHECK-NEXT: vmov.8 q0[9], r0896; CHECK-NEXT: vmov.u8 r0, q2[8]897; CHECK-NEXT: vmov.8 q0[10], r0898; CHECK-NEXT: vmov.u8 r0, q2[12]899; CHECK-NEXT: vmov.8 q0[11], r0900; CHECK-NEXT: vmov.u8 r0, q3[0]901; CHECK-NEXT: vmov.8 q0[12], r0902; CHECK-NEXT: vmov.u8 r0, q3[4]903; CHECK-NEXT: vmov.8 q0[13], r0904; CHECK-NEXT: vmov.u8 r0, q3[8]905; CHECK-NEXT: vmov.8 q0[14], r0906; CHECK-NEXT: vmov.u8 r0, q3[12]907; CHECK-NEXT: vmov.8 q0[15], r0908; CHECK-NEXT: vmov.u8 r0, q1[12]909; CHECK-NEXT: vmov.8 q6[7], r0910; CHECK-NEXT: vmov.f32 s26, s2911; CHECK-NEXT: vmov.f32 s27, s3912; CHECK-NEXT: vadd.i8 q0, q6, q5913; CHECK-NEXT: vadd.i8 q0, q0, q4914; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}915; CHECK-NEXT: bx lr916entry:917 %s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>918 %s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>919 %s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>920 %s4 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>921 %a1 = add <16 x i8> %s1, %s2922 %a2 = add <16 x i8> %s3, %s4923 %r = add <16 x i8> %a1, %a2924 ret <16 x i8> %r925}926 927; i64928 929define arm_aapcs_vfpcc <2 x i64> @shuffle1_i64(<2 x i64> %src) {930; CHECK-LABEL: shuffle1_i64:931; CHECK: @ %bb.0: @ %entry932; CHECK-NEXT: bx lr933entry:934 %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 0, i32 1>935 ret <2 x i64> %out936}937 938define arm_aapcs_vfpcc <2 x i64> @shuffle2_i64(<2 x i64> %src) {939; CHECK-LABEL: shuffle2_i64:940; CHECK: @ %bb.0: @ %entry941; CHECK-NEXT: vmov.f32 s4, s2942; CHECK-NEXT: vmov.f32 s6, s0943; CHECK-NEXT: vmov.f32 s5, s3944; CHECK-NEXT: vmov.f32 s7, s1945; CHECK-NEXT: vmov q0, q1946; CHECK-NEXT: bx lr947entry:948 %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 0>949 ret <2 x i64> %out950}951 952define arm_aapcs_vfpcc <2 x i64> @shuffle3_i64(<2 x i64> %src) {953; CHECK-LABEL: shuffle3_i64:954; CHECK: @ %bb.0: @ %entry955; CHECK-NEXT: bx lr956entry:957 %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 undef, i32 1>958 ret <2 x i64> %out959}960 961; f32962 963define arm_aapcs_vfpcc <4 x float> @shuffle1_f32(<4 x float> %src) {964; CHECK-LABEL: shuffle1_f32:965; CHECK: @ %bb.0: @ %entry966; CHECK-NEXT: vmov.f32 s4, s3967; CHECK-NEXT: vmov.f32 s5, s2968; CHECK-NEXT: vmov.f32 s6, s1969; CHECK-NEXT: vmov.f32 s7, s0970; CHECK-NEXT: vmov q0, q1971; CHECK-NEXT: bx lr972entry:973 %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>974 ret <4 x float> %out975}976 977define arm_aapcs_vfpcc <4 x float> @shuffle2_f32(<4 x float> %src) {978; CHECK-LABEL: shuffle2_f32:979; CHECK: @ %bb.0: @ %entry980; CHECK-NEXT: bx lr981entry:982 %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>983 ret <4 x float> %out984}985 986define arm_aapcs_vfpcc <4 x float> @shuffle3_f32(<4 x float> %src) {987; CHECK-LABEL: shuffle3_f32:988; CHECK: @ %bb.0: @ %entry989; CHECK-NEXT: vmov.f32 s4, s3990; CHECK-NEXT: vmov.f32 s5, s1991; CHECK-NEXT: vmov.f32 s6, s2992; CHECK-NEXT: vmov.f32 s7, s0993; CHECK-NEXT: vmov q0, q1994; CHECK-NEXT: bx lr995entry:996 %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0>997 ret <4 x float> %out998}999 1000define arm_aapcs_vfpcc <4 x float> @shuffle5_f32(<4 x float> %src) {1001; CHECK-LABEL: shuffle5_f32:1002; CHECK: @ %bb.0: @ %entry1003; CHECK-NEXT: vrev64.32 q1, q01004; CHECK-NEXT: vmov q0, q11005; CHECK-NEXT: bx lr1006entry:1007 %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>1008 ret <4 x float> %out1009}1010 1011define arm_aapcs_vfpcc <4 x float> @oneoff11_f32(<4 x float> %src1, <4 x float> %src2) {1012; CHECK-LABEL: oneoff11_f32:1013; CHECK: @ %bb.0: @ %entry1014; CHECK-NEXT: vmov.f32 s2, s11015; CHECK-NEXT: bx lr1016entry:1017 %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>1018 ret <4 x float> %out1019}1020 1021define arm_aapcs_vfpcc <4 x float> @oneoff12_f32(<4 x float> %src1, <4 x float> %src2) {1022; CHECK-LABEL: oneoff12_f32:1023; CHECK: @ %bb.0: @ %entry1024; CHECK-NEXT: vmov.f32 s0, s41025; CHECK-NEXT: bx lr1026entry:1027 %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>1028 ret <4 x float> %out1029}1030 1031define arm_aapcs_vfpcc <4 x float> @oneoff21_f32(<4 x float> %src1, <4 x float> %src2) {1032; CHECK-LABEL: oneoff21_f32:1033; CHECK: @ %bb.0: @ %entry1034; CHECK-NEXT: vmov.f32 s7, s01035; CHECK-NEXT: vmov q0, q11036; CHECK-NEXT: bx lr1037entry:1038 %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 5, i32 6, i32 0>1039 ret <4 x float> %out1040}1041 1042define arm_aapcs_vfpcc <4 x float> @oneoff22_f32(<4 x float> %src1, <4 x float> %src2) {1043; CHECK-LABEL: oneoff22_f32:1044; CHECK: @ %bb.0: @ %entry1045; CHECK-NEXT: vmov q0, q11046; CHECK-NEXT: vmov.f32 s2, s01047; CHECK-NEXT: bx lr1048entry:1049 %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7>1050 ret <4 x float> %out1051}1052 1053define arm_aapcs_vfpcc <4 x float> @shuffle2step_f32(<8 x float> %src) {1054; CHECKFP-LABEL: shuffle2step_f32:1055; CHECKFP: @ %bb.0: @ %entry1056; CHECKFP-NEXT: vmov.f32 s8, s11057; CHECKFP-NEXT: vmov.f32 s9, s31058; CHECKFP-NEXT: vmov.f32 s1, s21059; CHECKFP-NEXT: vmov.f32 s10, s51060; CHECKFP-NEXT: vmov.f32 s11, s71061; CHECKFP-NEXT: vmov.f32 s2, s41062; CHECKFP-NEXT: vmov.f32 s3, s61063; CHECKFP-NEXT: vadd.f32 q0, q0, q21064; CHECKFP-NEXT: bx lr1065entry:1066 %s1 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1067 %s2 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1068 %r = fadd <4 x float> %s1, %s21069 ret <4 x float> %r1070}1071 1072define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {1073; CHECKFP-LABEL: shuffle3step_f32:1074; CHECKFP: @ %bb.0: @ %entry1075; CHECKFP-NEXT: .vsave {d8, d9}1076; CHECKFP-NEXT: vpush {d8, d9}1077; CHECKFP-NEXT: vmov.f32 s13, s41078; CHECKFP-NEXT: vmov.f32 s14, s71079; CHECKFP-NEXT: vmov.f32 s18, s61080; CHECKFP-NEXT: vmov.f32 s12, s11081; CHECKFP-NEXT: vmov.f32 s15, s101082; CHECKFP-NEXT: vmov.f32 s16, s01083; CHECKFP-NEXT: vmov.f32 s17, s31084; CHECKFP-NEXT: vmov.f32 s19, s91085; CHECKFP-NEXT: vadd.f32 q3, q4, q31086; CHECKFP-NEXT: vmov.f32 s4, s21087; CHECKFP-NEXT: vmov.f32 s6, s81088; CHECKFP-NEXT: vmov.f32 s7, s111089; CHECKFP-NEXT: vadd.f32 q0, q3, q11090; CHECKFP-NEXT: vpop {d8, d9}1091; CHECKFP-NEXT: bx lr1092entry:1093 %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1094 %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>1095 %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>1096 %a = fadd <4 x float> %s1, %s21097 %r = fadd <4 x float> %a, %s31098 ret <4 x float> %r1099}1100 1101define arm_aapcs_vfpcc <4 x float> @shuffle4step_f32(<16 x float> %src) {1102; CHECKFP-LABEL: shuffle4step_f32:1103; CHECKFP: @ %bb.0: @ %entry1104; CHECKFP-NEXT: .vsave {d8, d9, d10, d11}1105; CHECKFP-NEXT: vpush {d8, d9, d10, d11}1106; CHECKFP-NEXT: vmov.f32 s16, s31107; CHECKFP-NEXT: vmov.f32 s20, s21108; CHECKFP-NEXT: vmov.f32 s17, s71109; CHECKFP-NEXT: vmov.f32 s18, s111110; CHECKFP-NEXT: vmov.f32 s19, s151111; CHECKFP-NEXT: vmov.f32 s21, s61112; CHECKFP-NEXT: vmov.f32 s22, s101113; CHECKFP-NEXT: vmov.f32 s23, s141114; CHECKFP-NEXT: vadd.f32 q4, q5, q41115; CHECKFP-NEXT: vmov.f32 s20, s11116; CHECKFP-NEXT: vmov.f32 s21, s51117; CHECKFP-NEXT: vmov.f32 s22, s91118; CHECKFP-NEXT: vmov.f32 s23, s131119; CHECKFP-NEXT: vmov.f32 s1, s41120; CHECKFP-NEXT: vmov.f32 s2, s81121; CHECKFP-NEXT: vmov.f32 s3, s121122; CHECKFP-NEXT: vadd.f32 q0, q0, q51123; CHECKFP-NEXT: vadd.f32 q0, q0, q41124; CHECKFP-NEXT: vpop {d8, d9, d10, d11}1125; CHECKFP-NEXT: bx lr1126entry:1127 %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>1128 %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>1129 %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>1130 %s4 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>1131 %a1 = fadd <4 x float> %s1, %s21132 %a2 = fadd <4 x float> %s3, %s41133 %r = fadd <4 x float> %a1, %a21134 ret <4 x float> %r1135}1136 1137; f161138 1139define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {1140; CHECK-LABEL: shuffle1_f16:1141; CHECK: @ %bb.0: @ %entry1142; CHECK-NEXT: vrev64.16 q1, q01143; CHECK-NEXT: vmov.f32 s0, s61144; CHECK-NEXT: vmov.f32 s1, s71145; CHECK-NEXT: vmov.f32 s2, s41146; CHECK-NEXT: vmov.f32 s3, s51147; CHECK-NEXT: bx lr1148entry:1149 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>1150 ret <8 x half> %out1151}1152 1153define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) {1154; CHECK-LABEL: shuffle2_f16:1155; CHECK: @ %bb.0: @ %entry1156; CHECK-NEXT: bx lr1157entry:1158 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1159 ret <8 x half> %out1160}1161 1162define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {1163; CHECK-LV-LABEL: shuffle3_f16:1164; CHECK-LV: @ %bb.0: @ %entry1165; CHECK-LV-NEXT: vmovx.f16 s5, s31166; CHECK-LV-NEXT: vmovx.f16 s6, s11167; CHECK-LV-NEXT: vmovx.f16 s4, s01168; CHECK-LV-NEXT: vins.f16 s1, s01169; CHECK-LV-NEXT: vins.f16 s6, s41170; CHECK-LV-NEXT: vins.f16 s5, s31171; CHECK-LV-NEXT: vmov.f32 s4, s21172; CHECK-LV-NEXT: vmov.f32 s7, s11173; CHECK-LV-NEXT: vmov q0, q11174; CHECK-LV-NEXT: bx lr1175;1176; CHECK-LIS-LABEL: shuffle3_f16:1177; CHECK-LIS: @ %bb.0: @ %entry1178; CHECK-LIS-NEXT: vmov q1, q01179; CHECK-LIS-NEXT: vmovx.f16 s2, s51180; CHECK-LIS-NEXT: vmovx.f16 s0, s41181; CHECK-LIS-NEXT: vins.f16 s5, s41182; CHECK-LIS-NEXT: vins.f16 s2, s01183; CHECK-LIS-NEXT: vmov.f32 s0, s61184; CHECK-LIS-NEXT: vmovx.f16 s1, s71185; CHECK-LIS-NEXT: vmov.f32 s3, s51186; CHECK-LIS-NEXT: vins.f16 s1, s71187; CHECK-LIS-NEXT: bx lr1188 1189entry:1190 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>1191 ret <8 x half> %out1192}1193 1194define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) {1195; CHECK-LABEL: shuffle5_f16:1196; CHECK: @ %bb.0: @ %entry1197; CHECK-NEXT: vrev64.16 q1, q01198; CHECK-NEXT: vmov q0, q11199; CHECK-NEXT: bx lr1200entry:1201 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>1202 ret <8 x half> %out1203}1204 1205define arm_aapcs_vfpcc <8 x half> @shuffle6_f16(<8 x half> %src) {1206; CHECK-LABEL: shuffle6_f16:1207; CHECK: @ %bb.0: @ %entry1208; CHECK-NEXT: vrev32.16 q0, q01209; CHECK-NEXT: bx lr1210entry:1211 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>1212 ret <8 x half> %out1213}1214 1215define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) {1216; CHECK-LABEL: oneoff11_f16:1217; CHECK: @ %bb.0: @ %entry1218; CHECK-NEXT: vmovx.f16 s4, s01219; CHECK-NEXT: vmov r0, s41220; CHECK-NEXT: vmov.16 q0[2], r01221; CHECK-NEXT: bx lr1222entry:1223 %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>1224 ret <8 x half> %out1225}1226 1227define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) {1228; CHECK-LABEL: oneoff12_f16:1229; CHECK: @ %bb.0: @ %entry1230; CHECK-NEXT: vmov r0, s41231; CHECK-NEXT: vmov.16 q0[0], r01232; CHECK-NEXT: bx lr1233entry:1234 %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1235 ret <8 x half> %out1236}1237 1238define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {1239; CHECK-LABEL: oneoff21_f16:1240; CHECK: @ %bb.0: @ %entry1241; CHECK-NEXT: vins.f16 s5, s01242; CHECK-NEXT: vmov q0, q11243; CHECK-NEXT: bx lr1244entry:1245 %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>1246 ret <8 x half> %out1247}1248 1249define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) {1250; CHECK-LABEL: oneoff22_f16:1251; CHECK: @ %bb.0: @ %entry1252; CHECK-NEXT: vmov q0, q11253; CHECK-NEXT: vmov r0, s31254; CHECK-NEXT: vmov.16 q0[0], r01255; CHECK-NEXT: bx lr1256entry:1257 %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1258 ret <8 x half> %out1259}1260 1261define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) {1262; CHECKFP-LABEL: shuffle2step_f16:1263; CHECKFP: @ %bb.0: @ %entry1264; CHECKFP-NEXT: vmovx.f16 s8, s01265; CHECKFP-NEXT: vmovx.f16 s10, s11266; CHECKFP-NEXT: vins.f16 s8, s101267; CHECKFP-NEXT: vmovx.f16 s9, s21268; CHECKFP-NEXT: vmovx.f16 s10, s31269; CHECKFP-NEXT: vmovx.f16 s12, s51270; CHECKFP-NEXT: vins.f16 s9, s101271; CHECKFP-NEXT: vmovx.f16 s10, s41272; CHECKFP-NEXT: vins.f16 s10, s121273; CHECKFP-NEXT: vmovx.f16 s11, s61274; CHECKFP-NEXT: vmovx.f16 s12, s71275; CHECKFP-NEXT: vins.f16 s2, s31276; CHECKFP-NEXT: vins.f16 s6, s71277; CHECKFP-NEXT: vins.f16 s4, s51278; CHECKFP-NEXT: vins.f16 s0, s11279; CHECKFP-NEXT: vmov.f32 s1, s21280; CHECKFP-NEXT: vins.f16 s11, s121281; CHECKFP-NEXT: vmov.f32 s2, s41282; CHECKFP-NEXT: vmov.f32 s3, s61283; CHECKFP-NEXT: vadd.f16 q0, q0, q21284; CHECKFP-NEXT: bx lr1285entry:1286 %s1 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1287 %s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1288 %r = fadd <8 x half> %s1, %s21289 ret <8 x half> %r1290}1291 1292define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {1293; CHECKFP-LABEL: shuffle3step_f16:1294; CHECKFP: @ %bb.0: @ %entry1295; CHECKFP-NEXT: .vsave {d8, d9}1296; CHECKFP-NEXT: vpush {d8, d9}1297; CHECKFP-NEXT: vmov.f32 s13, s41298; CHECKFP-NEXT: vmovx.f16 s4, s41299; CHECKFP-NEXT: vmovx.f16 s17, s31300; CHECKFP-NEXT: vins.f16 s3, s41301; CHECKFP-NEXT: vmovx.f16 s4, s71302; CHECKFP-NEXT: vmovx.f16 s18, s61303; CHECKFP-NEXT: vmovx.f16 s16, s01304; CHECKFP-NEXT: vins.f16 s6, s41305; CHECKFP-NEXT: vmovx.f16 s14, s21306; CHECKFP-NEXT: vmov.f32 s12, s11307; CHECKFP-NEXT: vmovx.f16 s4, s101308; CHECKFP-NEXT: vmovx.f16 s19, s91309; CHECKFP-NEXT: vins.f16 s12, s141310; CHECKFP-NEXT: vmovx.f16 s14, s51311; CHECKFP-NEXT: vins.f16 s16, s21312; CHECKFP-NEXT: vmovx.f16 s2, s111313; CHECKFP-NEXT: vmovx.f16 s15, s81314; CHECKFP-NEXT: vins.f16 s18, s81315; CHECKFP-NEXT: vmovx.f16 s8, s11316; CHECKFP-NEXT: vins.f16 s9, s41317; CHECKFP-NEXT: vins.f16 s13, s141318; CHECKFP-NEXT: vmov.f32 s14, s71319; CHECKFP-NEXT: vins.f16 s10, s21320; CHECKFP-NEXT: vmov.f32 s1, s31321; CHECKFP-NEXT: vins.f16 s19, s111322; CHECKFP-NEXT: vins.f16 s17, s51323; CHECKFP-NEXT: vins.f16 s0, s81324; CHECKFP-NEXT: vmov.f32 s2, s61325; CHECKFP-NEXT: vmov.f32 s3, s91326; CHECKFP-NEXT: vins.f16 s14, s151327; CHECKFP-NEXT: vmov.f32 s15, s101328; CHECKFP-NEXT: vadd.f16 q0, q0, q41329; CHECKFP-NEXT: vadd.f16 q0, q0, q31330; CHECKFP-NEXT: vpop {d8, d9}1331; CHECKFP-NEXT: bx lr1332entry:1333 %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>1334 %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>1335 %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>1336 %a = fadd <8 x half> %s1, %s21337 %r = fadd <8 x half> %a, %s31338 ret <8 x half> %r1339}1340 1341define arm_aapcs_vfpcc <8 x half> @shuffle4step_f16(<32 x half> %src) {1342; CHECKFP-LABEL: shuffle4step_f16:1343; CHECKFP: @ %bb.0: @ %entry1344; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1345; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}1346; CHECKFP-NEXT: vmovx.f16 s18, s91347; CHECKFP-NEXT: vmovx.f16 s16, s111348; CHECKFP-NEXT: vins.f16 s18, s161349; CHECKFP-NEXT: vmovx.f16 s19, s131350; CHECKFP-NEXT: vmovx.f16 s16, s151351; CHECKFP-NEXT: vmovx.f16 s22, s81352; CHECKFP-NEXT: vins.f16 s19, s161353; CHECKFP-NEXT: vmovx.f16 s16, s11354; CHECKFP-NEXT: vmovx.f16 s20, s31355; CHECKFP-NEXT: vins.f16 s1, s31356; CHECKFP-NEXT: vmovx.f16 s3, s101357; CHECKFP-NEXT: vins.f16 s16, s201358; CHECKFP-NEXT: vmovx.f16 s17, s51359; CHECKFP-NEXT: vmovx.f16 s20, s71360; CHECKFP-NEXT: vins.f16 s22, s31361; CHECKFP-NEXT: vmovx.f16 s23, s121362; CHECKFP-NEXT: vmovx.f16 s3, s141363; CHECKFP-NEXT: vins.f16 s17, s201364; CHECKFP-NEXT: vins.f16 s23, s31365; CHECKFP-NEXT: vmovx.f16 s20, s01366; CHECKFP-NEXT: vmovx.f16 s3, s21367; CHECKFP-NEXT: vins.f16 s9, s111368; CHECKFP-NEXT: vins.f16 s13, s151369; CHECKFP-NEXT: vins.f16 s5, s71370; CHECKFP-NEXT: vins.f16 s20, s31371; CHECKFP-NEXT: vmovx.f16 s21, s41372; CHECKFP-NEXT: vmovx.f16 s3, s61373; CHECKFP-NEXT: vins.f16 s8, s101374; CHECKFP-NEXT: vins.f16 s12, s141375; CHECKFP-NEXT: vins.f16 s4, s61376; CHECKFP-NEXT: vins.f16 s21, s31377; CHECKFP-NEXT: vins.f16 s0, s21378; CHECKFP-NEXT: vmov.f32 s24, s11379; CHECKFP-NEXT: vmov.f32 s26, s91380; CHECKFP-NEXT: vmov.f32 s25, s51381; CHECKFP-NEXT: vmov.f32 s27, s131382; CHECKFP-NEXT: vmov.f32 s2, s81383; CHECKFP-NEXT: vadd.f16 q4, q6, q41384; CHECKFP-NEXT: vmov.f32 s1, s41385; CHECKFP-NEXT: vmov.f32 s3, s121386; CHECKFP-NEXT: vadd.f16 q0, q0, q51387; CHECKFP-NEXT: vadd.f16 q0, q0, q41388; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}1389; CHECKFP-NEXT: bx lr1390entry:1391 %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>1392 %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>1393 %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>1394 %s4 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>1395 %a1 = fadd <8 x half> %s1, %s21396 %a2 = fadd <8 x half> %s3, %s41397 %r = fadd <8 x half> %a1, %a21398 ret <8 x half> %r1399}1400 1401; f641402 1403define arm_aapcs_vfpcc <2 x double> @shuffle1_f64(<2 x double> %src) {1404; CHECK-LABEL: shuffle1_f64:1405; CHECK: @ %bb.0: @ %entry1406; CHECK-NEXT: bx lr1407entry:1408 %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 0, i32 1>1409 ret <2 x double> %out1410}1411 1412define arm_aapcs_vfpcc <2 x double> @shuffle2_f64(<2 x double> %src) {1413; CHECK-LABEL: shuffle2_f64:1414; CHECK: @ %bb.0: @ %entry1415; CHECK-NEXT: vmov.f32 s4, s21416; CHECK-NEXT: vmov.f32 s6, s01417; CHECK-NEXT: vmov.f32 s5, s31418; CHECK-NEXT: vmov.f32 s7, s11419; CHECK-NEXT: vmov q0, q11420; CHECK-NEXT: bx lr1421entry:1422 %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 1, i32 0>1423 ret <2 x double> %out1424}1425 1426define arm_aapcs_vfpcc <2 x double> @shuffle3_f64(<2 x double> %src) {1427; CHECK-LABEL: shuffle3_f64:1428; CHECK: @ %bb.0: @ %entry1429; CHECK-NEXT: bx lr1430entry:1431 %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 undef, i32 1>1432 ret <2 x double> %out1433}1434 1435define arm_aapcs_vfpcc <4 x double> @shuffle4_f64(<2 x double> %src1, <2 x double> %src2) {1436; CHECK-LABEL: shuffle4_f64:1437; CHECK: @ %bb.0: @ %entry1438; CHECK-NEXT: vmov.f32 s8, s61439; CHECK-NEXT: vmov.f32 s6, s01440; CHECK-NEXT: vmov.f32 s9, s71441; CHECK-NEXT: vmov.f32 s7, s11442; CHECK-NEXT: vmov.f32 s10, s21443; CHECK-NEXT: vmov.f32 s11, s31444; CHECK-NEXT: vmov q0, q21445; CHECK-NEXT: bx lr1446entry:1447 %out = shufflevector <2 x double> %src1, <2 x double> %src2, <4 x i32> <i32 3, i32 1, i32 2, i32 0>1448 ret <4 x double> %out1449}1450define arm_aapcs_vfpcc <4 x double> @shuffle5_f64(<2 x double> %src1, <2 x double> %src2) {1451; CHECK-LABEL: shuffle5_f64:1452; CHECK: @ %bb.0: @ %entry1453; CHECK-NEXT: vmov.f32 s8, s61454; CHECK-NEXT: vmov.f32 s10, s41455; CHECK-NEXT: vmov.f32 s4, s21456; CHECK-NEXT: vmov.f32 s6, s01457; CHECK-NEXT: vmov.f32 s9, s71458; CHECK-NEXT: vmov.f32 s11, s51459; CHECK-NEXT: vmov.f32 s5, s31460; CHECK-NEXT: vmov.f32 s7, s11461; CHECK-NEXT: vmov q0, q21462; CHECK-NEXT: bx lr1463entry:1464 %out = shufflevector <2 x double> %src1, <2 x double> %src2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1465 ret <4 x double> %out1466}1467define arm_aapcs_vfpcc <2 x double> @shuffle6_f64(<2 x double> %src1, <2 x double> %src2) {1468; CHECK-LABEL: shuffle6_f64:1469; CHECK: @ %bb.0: @ %entry1470; CHECK-NEXT: vmov.f32 s2, s61471; CHECK-NEXT: vmov.f32 s3, s71472; CHECK-NEXT: bx lr1473entry:1474 %out = shufflevector <2 x double> %src1, <2 x double> %src2, <2 x i32> <i32 0, i32 3>1475 ret <2 x double> %out1476}1477define arm_aapcs_vfpcc <2 x double> @shuffle7_f64(<2 x double> %src1, <2 x double> %src2) {1478; CHECK-LABEL: shuffle7_f64:1479; CHECK: @ %bb.0: @ %entry1480; CHECK-NEXT: vmov.f32 s0, s61481; CHECK-NEXT: vmov.f32 s1, s71482; CHECK-NEXT: bx lr1483entry:1484 %out = shufflevector <2 x double> %src1, <2 x double> %src2, <2 x i32> <i32 3, i32 1>1485 ret <2 x double> %out1486}1487define arm_aapcs_vfpcc <2 x double> @shuffle8_f64(<2 x double> %src1, <2 x double> %src2) {1488; CHECK-LABEL: shuffle8_f64:1489; CHECK: @ %bb.0: @ %entry1490; CHECK-NEXT: vmov.f32 s6, s21491; CHECK-NEXT: vmov.f32 s7, s31492; CHECK-NEXT: vmov q0, q11493; CHECK-NEXT: bx lr1494entry:1495 %out = shufflevector <2 x double> %src1, <2 x double> %src2, <2 x i32> <i32 2, i32 1>1496 ret <2 x double> %out1497}1498define arm_aapcs_vfpcc <8 x double> @shuffle9_f64(<4 x double> %src1, <4 x double> %src2) {1499; CHECK-LV-LABEL: shuffle9_f64:1500; CHECK-LV: @ %bb.0: @ %entry1501; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11}1502; CHECK-LV-NEXT: vpush {d8, d9, d10, d11}1503; CHECK-LV-NEXT: vmov q5, q21504; CHECK-LV-NEXT: vmov.f32 s16, s01505; CHECK-LV-NEXT: vmov.f32 s18, s201506; CHECK-LV-NEXT: vmov.f32 s20, s21507; CHECK-LV-NEXT: vmov.f32 s10, s121508; CHECK-LV-NEXT: vmov.f32 s19, s211509; CHECK-LV-NEXT: vmov.f32 s8, s41510; CHECK-LV-NEXT: vmov.f32 s17, s11511; CHECK-LV-NEXT: vmov.f32 s21, s31512; CHECK-LV-NEXT: vmov q0, q41513; CHECK-LV-NEXT: vmov.f32 s12, s61514; CHECK-LV-NEXT: vmov.f32 s11, s131515; CHECK-LV-NEXT: vmov.f32 s9, s51516; CHECK-LV-NEXT: vmov.f32 s13, s71517; CHECK-LV-NEXT: vmov q1, q51518; CHECK-LV-NEXT: vpop {d8, d9, d10, d11}1519; CHECK-LV-NEXT: bx lr1520;1521; CHECK-LIS-LABEL: shuffle9_f64:1522; CHECK-LIS: @ %bb.0: @ %entry1523; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11}1524; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11}1525; CHECK-LIS-NEXT: vmov q5, q21526; CHECK-LIS-NEXT: vmov q4, q01527; CHECK-LIS-NEXT: vmov.f32 s2, s201528; CHECK-LIS-NEXT: vmov.f32 s20, s181529; CHECK-LIS-NEXT: vmov.f32 s10, s121530; CHECK-LIS-NEXT: vmov.f32 s3, s211531; CHECK-LIS-NEXT: vmov.f32 s8, s41532; CHECK-LIS-NEXT: vmov.f32 s21, s191533; CHECK-LIS-NEXT: vmov.f32 s12, s61534; CHECK-LIS-NEXT: vmov.f32 s11, s131535; CHECK-LIS-NEXT: vmov.f32 s9, s51536; CHECK-LIS-NEXT: vmov.f32 s13, s71537; CHECK-LIS-NEXT: vmov q1, q51538; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11}1539; CHECK-LIS-NEXT: bx lr1540 1541entry:1542 %out = shufflevector <4 x double> %src1, <4 x double> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>1543 ret <8 x double> %out1544}1545 1546 1547 1548 1549define arm_aapcs_vfpcc <4 x i64> @shuffle4_i64(<2 x i64> %src1, <2 x i64> %src2) {1550; CHECK-LABEL: shuffle4_i64:1551; CHECK: @ %bb.0: @ %entry1552; CHECK-NEXT: vmov.f32 s8, s61553; CHECK-NEXT: vmov.f32 s6, s01554; CHECK-NEXT: vmov.f32 s9, s71555; CHECK-NEXT: vmov.f32 s7, s11556; CHECK-NEXT: vmov.f32 s10, s21557; CHECK-NEXT: vmov.f32 s11, s31558; CHECK-NEXT: vmov q0, q21559; CHECK-NEXT: bx lr1560entry:1561 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <4 x i32> <i32 3, i32 1, i32 2, i32 0>1562 ret <4 x i64> %out1563}1564define arm_aapcs_vfpcc <4 x i64> @shuffle5_i64(<2 x i64> %src1, <2 x i64> %src2) {1565; CHECK-LABEL: shuffle5_i64:1566; CHECK: @ %bb.0: @ %entry1567; CHECK-NEXT: vmov.f32 s8, s61568; CHECK-NEXT: vmov.f32 s10, s41569; CHECK-NEXT: vmov.f32 s4, s21570; CHECK-NEXT: vmov.f32 s6, s01571; CHECK-NEXT: vmov.f32 s9, s71572; CHECK-NEXT: vmov.f32 s11, s51573; CHECK-NEXT: vmov.f32 s5, s31574; CHECK-NEXT: vmov.f32 s7, s11575; CHECK-NEXT: vmov q0, q21576; CHECK-NEXT: bx lr1577entry:1578 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1579 ret <4 x i64> %out1580}1581define arm_aapcs_vfpcc <2 x i64> @shuffle6_i64(<2 x i64> %src1, <2 x i64> %src2) {1582; CHECK-LABEL: shuffle6_i64:1583; CHECK: @ %bb.0: @ %entry1584; CHECK-NEXT: vmov.f32 s2, s61585; CHECK-NEXT: vmov.f32 s3, s71586; CHECK-NEXT: bx lr1587entry:1588 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>1589 ret <2 x i64> %out1590}1591define arm_aapcs_vfpcc <2 x i64> @shuffle7_i64(<2 x i64> %src1, <2 x i64> %src2) {1592; CHECK-LABEL: shuffle7_i64:1593; CHECK: @ %bb.0: @ %entry1594; CHECK-NEXT: vmov.f32 s0, s61595; CHECK-NEXT: vmov.f32 s1, s71596; CHECK-NEXT: bx lr1597entry:1598 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 1>1599 ret <2 x i64> %out1600}1601define arm_aapcs_vfpcc <2 x i64> @shuffle8_i64(<2 x i64> %src1, <2 x i64> %src2) {1602; CHECK-LABEL: shuffle8_i64:1603; CHECK: @ %bb.0: @ %entry1604; CHECK-NEXT: vmov.f32 s6, s21605; CHECK-NEXT: vmov.f32 s7, s31606; CHECK-NEXT: vmov q0, q11607; CHECK-NEXT: bx lr1608entry:1609 %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 2, i32 1>1610 ret <2 x i64> %out1611}1612define arm_aapcs_vfpcc <8 x i64> @shuffle9_i64(<4 x i64> %src1, <4 x i64> %src2) {1613; CHECK-LV-LABEL: shuffle9_i64:1614; CHECK-LV: @ %bb.0: @ %entry1615; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11}1616; CHECK-LV-NEXT: vpush {d8, d9, d10, d11}1617; CHECK-LV-NEXT: vmov q5, q21618; CHECK-LV-NEXT: vmov.f32 s16, s01619; CHECK-LV-NEXT: vmov.f32 s18, s201620; CHECK-LV-NEXT: vmov.f32 s20, s21621; CHECK-LV-NEXT: vmov.f32 s10, s121622; CHECK-LV-NEXT: vmov.f32 s19, s211623; CHECK-LV-NEXT: vmov.f32 s8, s41624; CHECK-LV-NEXT: vmov.f32 s17, s11625; CHECK-LV-NEXT: vmov.f32 s21, s31626; CHECK-LV-NEXT: vmov q0, q41627; CHECK-LV-NEXT: vmov.f32 s12, s61628; CHECK-LV-NEXT: vmov.f32 s11, s131629; CHECK-LV-NEXT: vmov.f32 s9, s51630; CHECK-LV-NEXT: vmov.f32 s13, s71631; CHECK-LV-NEXT: vmov q1, q51632; CHECK-LV-NEXT: vpop {d8, d9, d10, d11}1633; CHECK-LV-NEXT: bx lr1634;1635; CHECK-LIS-LABEL: shuffle9_i64:1636; CHECK-LIS: @ %bb.0: @ %entry1637; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11}1638; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11}1639; CHECK-LIS-NEXT: vmov q5, q21640; CHECK-LIS-NEXT: vmov q4, q01641; CHECK-LIS-NEXT: vmov.f32 s2, s201642; CHECK-LIS-NEXT: vmov.f32 s20, s181643; CHECK-LIS-NEXT: vmov.f32 s10, s121644; CHECK-LIS-NEXT: vmov.f32 s3, s211645; CHECK-LIS-NEXT: vmov.f32 s8, s41646; CHECK-LIS-NEXT: vmov.f32 s21, s191647; CHECK-LIS-NEXT: vmov.f32 s12, s61648; CHECK-LIS-NEXT: vmov.f32 s11, s131649; CHECK-LIS-NEXT: vmov.f32 s9, s51650; CHECK-LIS-NEXT: vmov.f32 s13, s71651; CHECK-LIS-NEXT: vmov q1, q51652; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11}1653; CHECK-LIS-NEXT: bx lr1654 1655entry:1656 %out = shufflevector <4 x i64> %src1, <4 x i64> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>1657 ret <8 x i64> %out1658}1659 1660 1661define arm_aapcs_vfpcc <4 x i32> @insert_i32(i32 %a) {1662; CHECK-LABEL: insert_i32:1663; CHECK: @ %bb.0: @ %entry1664; CHECK-NEXT: vmov.32 q0[0], r01665; CHECK-NEXT: bx lr1666entry:1667 %res = insertelement <4 x i32> undef, i32 %a, i32 01668 ret <4 x i32> %res1669}1670 1671define arm_aapcs_vfpcc <8 x i16> @insert_i16(i16 %a) {1672; CHECK-LABEL: insert_i16:1673; CHECK: @ %bb.0: @ %entry1674; CHECK-NEXT: vmov.16 q0[0], r01675; CHECK-NEXT: bx lr1676entry:1677 %res = insertelement <8 x i16> undef, i16 %a, i32 01678 ret <8 x i16> %res1679}1680 1681define arm_aapcs_vfpcc <16 x i8> @insert_i8(i8 %a) {1682; CHECK-LABEL: insert_i8:1683; CHECK: @ %bb.0: @ %entry1684; CHECK-NEXT: vmov.8 q0[0], r01685; CHECK-NEXT: bx lr1686entry:1687 %res = insertelement <16 x i8> undef, i8 %a, i32 01688 ret <16 x i8> %res1689}1690 1691define arm_aapcs_vfpcc <2 x i64> @insert_i64(i64 %a) {1692; CHECK-LABEL: insert_i64:1693; CHECK: @ %bb.0: @ %entry1694; CHECK-NEXT: vmov.32 q0[0], r01695; CHECK-NEXT: vmov.32 q0[1], r11696; CHECK-NEXT: bx lr1697entry:1698 %res = insertelement <2 x i64> undef, i64 %a, i32 01699 ret <2 x i64> %res1700}1701 1702define arm_aapcs_vfpcc <4 x float> @insert_f32(float %a) {1703; CHECK-LABEL: insert_f32:1704; CHECK: @ %bb.0: @ %entry1705; CHECK-NEXT: bx lr1706entry:1707 %res = insertelement <4 x float> undef, float %a, i32 01708 ret <4 x float> %res1709}1710 1711define arm_aapcs_vfpcc <8 x half> @insert_f16(half %a) {1712; CHECK-LABEL: insert_f16:1713; CHECK: @ %bb.0: @ %entry1714; CHECK-NEXT: bx lr1715entry:1716 %res = insertelement <8 x half> undef, half %a, i32 01717 ret <8 x half> %res1718}1719 1720define arm_aapcs_vfpcc <2 x double> @insert_f64(double %a) {1721; CHECK-LABEL: insert_f64:1722; CHECK: @ %bb.0: @ %entry1723; CHECK-NEXT: bx lr1724entry:1725 %res = insertelement <2 x double> undef, double %a, i32 01726 ret <2 x double> %res1727}1728 1729define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {1730; CHECK-LABEL: scalar_to_vector_i32:1731; CHECK: @ %bb.0: @ %entry1732; CHECK-NEXT: .pad #81733; CHECK-NEXT: sub sp, #81734; CHECK-NEXT: adr r2, .LCPI88_01735; CHECK-NEXT: vmov.u16 r0, q0[0]1736; CHECK-NEXT: vldrw.u32 q0, [r2]1737; CHECK-NEXT: mov r1, sp1738; CHECK-NEXT: vmov.32 q0[0], r01739; CHECK-NEXT: vstrh.32 q0, [r1]1740; CHECK-NEXT: ldrd r0, r1, [sp], #81741; CHECK-NEXT: bx lr1742; CHECK-NEXT: .p2align 41743; CHECK-NEXT: @ %bb.1:1744; CHECK-NEXT: .LCPI88_0:1745; CHECK-NEXT: .zero 41746; CHECK-NEXT: .long 7 @ 0x71747; CHECK-NEXT: .long 1 @ 0x11748; CHECK-NEXT: .long 9 @ 0x91749entry:1750 %f = shufflevector <8 x i16> %v, <8 x i16> <i16 undef, i16 7, i16 1, i16 9, i16 undef, i16 undef, i16 undef, i16 undef>, <4 x i32> <i32 0, i32 9, i32 10, i32 11>1751 %0 = bitcast <4 x i16> %f to i641752 ret i64 %01753}1754 1755 1756define arm_aapcs_vfpcc i32 @extract_i32_0(<4 x i32> %a) {1757; CHECK-LABEL: extract_i32_0:1758; CHECK: @ %bb.0: @ %entry1759; CHECK-NEXT: vmov r0, s01760; CHECK-NEXT: bx lr1761entry:1762 %res = extractelement <4 x i32> %a, i32 01763 ret i32 %res1764}1765 1766define arm_aapcs_vfpcc i32 @extract_i32_3(<4 x i32> %a) {1767; CHECK-LABEL: extract_i32_3:1768; CHECK: @ %bb.0: @ %entry1769; CHECK-NEXT: vmov r0, s31770; CHECK-NEXT: bx lr1771entry:1772 %res = extractelement <4 x i32> %a, i32 31773 ret i32 %res1774}1775 1776define arm_aapcs_vfpcc i16 @extract_i16_0(<8 x i16> %a) {1777; CHECK-LABEL: extract_i16_0:1778; CHECK: @ %bb.0: @ %entry1779; CHECK-NEXT: vmov.u16 r0, q0[0]1780; CHECK-NEXT: bx lr1781entry:1782 %res = extractelement <8 x i16> %a, i32 01783 ret i16 %res1784}1785 1786define arm_aapcs_vfpcc i16 @extract_i16_3(<8 x i16> %a) {1787; CHECK-LABEL: extract_i16_3:1788; CHECK: @ %bb.0: @ %entry1789; CHECK-NEXT: vmov.u16 r0, q0[3]1790; CHECK-NEXT: bx lr1791entry:1792 %res = extractelement <8 x i16> %a, i32 31793 ret i16 %res1794}1795 1796define arm_aapcs_vfpcc i8 @extract_i8_0(<16 x i8> %a) {1797; CHECK-LABEL: extract_i8_0:1798; CHECK: @ %bb.0: @ %entry1799; CHECK-NEXT: vmov.u8 r0, q0[0]1800; CHECK-NEXT: bx lr1801entry:1802 %res = extractelement <16 x i8> %a, i32 01803 ret i8 %res1804}1805 1806define arm_aapcs_vfpcc i8 @extract_i8_3(<16 x i8> %a) {1807; CHECK-LABEL: extract_i8_3:1808; CHECK: @ %bb.0: @ %entry1809; CHECK-NEXT: vmov.u8 r0, q0[3]1810; CHECK-NEXT: bx lr1811entry:1812 %res = extractelement <16 x i8> %a, i32 31813 ret i8 %res1814}1815 1816define arm_aapcs_vfpcc i64 @extract_i64_0(<2 x i64> %a) {1817; CHECK-LABEL: extract_i64_0:1818; CHECK: @ %bb.0: @ %entry1819; CHECK-NEXT: vmov r0, r1, d01820; CHECK-NEXT: bx lr1821entry:1822 %res = extractelement <2 x i64> %a, i32 01823 ret i64 %res1824}1825 1826define arm_aapcs_vfpcc i64 @extract_i64_1(<2 x i64> %a) {1827; CHECK-LABEL: extract_i64_1:1828; CHECK: @ %bb.0: @ %entry1829; CHECK-NEXT: vmov r0, r1, d11830; CHECK-NEXT: bx lr1831entry:1832 %res = extractelement <2 x i64> %a, i32 11833 ret i64 %res1834}1835 1836define arm_aapcs_vfpcc float @extract_f32_0(<4 x float> %a) {1837; CHECK-LABEL: extract_f32_0:1838; CHECK: @ %bb.0: @ %entry1839; CHECK-NEXT: bx lr1840entry:1841 %res = extractelement <4 x float> %a, i32 01842 ret float %res1843}1844 1845define arm_aapcs_vfpcc float @extract_f32_3(<4 x float> %a) {1846; CHECK-LABEL: extract_f32_3:1847; CHECK: @ %bb.0: @ %entry1848; CHECK-NEXT: vmov.f32 s0, s31849; CHECK-NEXT: bx lr1850entry:1851 %res = extractelement <4 x float> %a, i32 31852 ret float %res1853}1854 1855define arm_aapcs_vfpcc half @extract_f16_0(<8 x half> %a) {1856; CHECK-LABEL: extract_f16_0:1857; CHECK: @ %bb.0: @ %entry1858; CHECK-NEXT: bx lr1859entry:1860 %res = extractelement <8 x half> %a, i32 01861 ret half %res1862}1863 1864define arm_aapcs_vfpcc half @extract_f16_3(<8 x half> %a) {1865; CHECK-LABEL: extract_f16_3:1866; CHECK: @ %bb.0: @ %entry1867; CHECK-NEXT: vmovx.f16 s0, s11868; CHECK-NEXT: bx lr1869entry:1870 %res = extractelement <8 x half> %a, i32 31871 ret half %res1872}1873 1874define arm_aapcs_vfpcc double @extract_f64_0(<2 x double> %a) {1875; CHECK-LABEL: extract_f64_0:1876; CHECK: @ %bb.0: @ %entry1877; CHECK-NEXT: bx lr1878entry:1879 %res = extractelement <2 x double> %a, i32 01880 ret double %res1881}1882 1883define arm_aapcs_vfpcc double @extract_f64_1(<2 x double> %a) {1884; CHECK-LABEL: extract_f64_1:1885; CHECK: @ %bb.0: @ %entry1886; CHECK-NEXT: vmov.f32 s0, s21887; CHECK-NEXT: vmov.f32 s1, s31888; CHECK-NEXT: bx lr1889entry:1890 %res = extractelement <2 x double> %a, i32 11891 ret double %res1892}1893 1894