448 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4; i16 -> i325 6define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246(<8 x i16> %src) {7; CHECK-LABEL: sext_i32_0246:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vmovlb.s16 q0, q010; CHECK-NEXT: bx lr11entry:12 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>13 %out = sext <4 x i16> %strided.vec to <4 x i32>14 ret <4 x i32> %out15}16 17define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246_swapped(<8 x i16> %src) {18; CHECK-LABEL: sext_i32_0246_swapped:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: .pad #1621; CHECK-NEXT: sub sp, #1622; CHECK-NEXT: mov r0, sp23; CHECK-NEXT: vstrw.32 q0, [r0]24; CHECK-NEXT: vldrh.s32 q0, [r0]25; CHECK-NEXT: vldrh.s32 q1, [r0, #8]26; CHECK-NEXT: vmov.f32 s1, s227; CHECK-NEXT: vmov.f32 s2, s428; CHECK-NEXT: vmov.f32 s3, s629; CHECK-NEXT: add sp, #1630; CHECK-NEXT: bx lr31entry:32 %out = sext <8 x i16> %src to <8 x i32>33 %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>34 ret <4 x i32> %strided.vec35}36 37define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357(<8 x i16> %src) {38; CHECK-LABEL: sext_i32_1357:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vmovlt.s16 q0, q041; CHECK-NEXT: bx lr42entry:43 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>44 %out = sext <4 x i16> %strided.vec to <4 x i32>45 ret <4 x i32> %out46}47 48define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357_swapped(<8 x i16> %src) {49; CHECK-LABEL: sext_i32_1357_swapped:50; CHECK: @ %bb.0: @ %entry51; CHECK-NEXT: .pad #1652; CHECK-NEXT: sub sp, #1653; CHECK-NEXT: mov r0, sp54; CHECK-NEXT: vstrw.32 q0, [r0]55; CHECK-NEXT: vldrh.s32 q0, [r0]56; CHECK-NEXT: vldrh.s32 q1, [r0, #8]57; CHECK-NEXT: vmov.f32 s0, s158; CHECK-NEXT: vmov.f32 s1, s359; CHECK-NEXT: vmov.f32 s2, s560; CHECK-NEXT: vmov.f32 s3, s761; CHECK-NEXT: add sp, #1662; CHECK-NEXT: bx lr63entry:64 %out = sext <8 x i16> %src to <8 x i32>65 %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>66 ret <4 x i32> %strided.vec67}68 69define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214(<16 x i16> %src) {70; CHECK-LABEL: sext_i32_02468101214:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vmovlb.s16 q0, q073; CHECK-NEXT: vmovlb.s16 q1, q174; CHECK-NEXT: bx lr75entry:76 %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>77 %out = sext <8 x i16> %strided.vec to <8 x i32>78 ret <8 x i32> %out79}80 81define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214_swapped(<16 x i16> %src) {82; CHECK-LABEL: sext_i32_02468101214_swapped:83; CHECK: @ %bb.0: @ %entry84; CHECK-NEXT: .pad #3285; CHECK-NEXT: sub sp, #3286; CHECK-NEXT: mov r0, sp87; CHECK-NEXT: add r1, sp, #1688; CHECK-NEXT: vstrw.32 q0, [r0]89; CHECK-NEXT: vstrw.32 q1, [r1]90; CHECK-NEXT: vldrh.s32 q0, [r0]91; CHECK-NEXT: vldrh.s32 q1, [r0, #8]92; CHECK-NEXT: vldrh.s32 q2, [r1, #8]93; CHECK-NEXT: vmov.f32 s1, s294; CHECK-NEXT: vmov.f32 s2, s495; CHECK-NEXT: vmov.f32 s3, s696; CHECK-NEXT: vldrh.s32 q1, [r1]97; CHECK-NEXT: vmov.f32 s7, s1098; CHECK-NEXT: vmov.f32 s5, s699; CHECK-NEXT: vmov.f32 s6, s8100; CHECK-NEXT: add sp, #32101; CHECK-NEXT: bx lr102entry:103 %out = sext <16 x i16> %src to <16 x i32>104 %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>105 ret <8 x i32> %strided.vec106}107 108define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315(<16 x i16> %src) {109; CHECK-LABEL: sext_i32_13579111315:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vmovlt.s16 q0, q0112; CHECK-NEXT: vmovlt.s16 q1, q1113; CHECK-NEXT: bx lr114entry:115 %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>116 %out = sext <8 x i16> %strided.vec to <8 x i32>117 ret <8 x i32> %out118}119 120define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315_swapped(<16 x i16> %src) {121; CHECK-LABEL: sext_i32_13579111315_swapped:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: .pad #32124; CHECK-NEXT: sub sp, #32125; CHECK-NEXT: mov r0, sp126; CHECK-NEXT: add r1, sp, #16127; CHECK-NEXT: vstrw.32 q0, [r0]128; CHECK-NEXT: vstrw.32 q1, [r1]129; CHECK-NEXT: vldrh.s32 q0, [r0]130; CHECK-NEXT: vldrh.s32 q1, [r0, #8]131; CHECK-NEXT: vldrh.s32 q2, [r1, #8]132; CHECK-NEXT: vmov.f32 s0, s1133; CHECK-NEXT: vmov.f32 s1, s3134; CHECK-NEXT: vmov.f32 s2, s5135; CHECK-NEXT: vmov.f32 s3, s7136; CHECK-NEXT: vldrh.s32 q1, [r1]137; CHECK-NEXT: vmov.f32 s6, s9138; CHECK-NEXT: vmov.f32 s4, s5139; CHECK-NEXT: vmov.f32 s5, s7140; CHECK-NEXT: vmov.f32 s7, s11141; CHECK-NEXT: add sp, #32142; CHECK-NEXT: bx lr143entry:144 %out = sext <16 x i16> %src to <16 x i32>145 %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>146 ret <8 x i32> %strided.vec147}148 149define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246(<8 x i16> %src) {150; CHECK-LABEL: zext_i32_0246:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vmovlb.u16 q0, q0153; CHECK-NEXT: bx lr154entry:155 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>156 %out = zext <4 x i16> %strided.vec to <4 x i32>157 ret <4 x i32> %out158}159 160define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246_swapped(<8 x i16> %src) {161; CHECK-LABEL: zext_i32_0246_swapped:162; CHECK: @ %bb.0: @ %entry163; CHECK-NEXT: .pad #16164; CHECK-NEXT: sub sp, #16165; CHECK-NEXT: mov r0, sp166; CHECK-NEXT: vstrw.32 q0, [r0]167; CHECK-NEXT: vldrh.u32 q0, [r0]168; CHECK-NEXT: vldrh.u32 q1, [r0, #8]169; CHECK-NEXT: vmov.f32 s1, s2170; CHECK-NEXT: vmov.f32 s2, s4171; CHECK-NEXT: vmov.f32 s3, s6172; CHECK-NEXT: add sp, #16173; CHECK-NEXT: bx lr174entry:175 %out = zext <8 x i16> %src to <8 x i32>176 %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>177 ret <4 x i32> %strided.vec178}179 180define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357(<8 x i16> %src) {181; CHECK-LABEL: zext_i32_1357:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vmovlt.u16 q0, q0184; CHECK-NEXT: bx lr185entry:186 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>187 %out = zext <4 x i16> %strided.vec to <4 x i32>188 ret <4 x i32> %out189}190 191define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357_swapped(<8 x i16> %src) {192; CHECK-LABEL: zext_i32_1357_swapped:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: .pad #16195; CHECK-NEXT: sub sp, #16196; CHECK-NEXT: mov r0, sp197; CHECK-NEXT: vstrw.32 q0, [r0]198; CHECK-NEXT: vldrh.u32 q0, [r0]199; CHECK-NEXT: vldrh.u32 q1, [r0, #8]200; CHECK-NEXT: vmov.f32 s0, s1201; CHECK-NEXT: vmov.f32 s1, s3202; CHECK-NEXT: vmov.f32 s2, s5203; CHECK-NEXT: vmov.f32 s3, s7204; CHECK-NEXT: add sp, #16205; CHECK-NEXT: bx lr206entry:207 %out = zext <8 x i16> %src to <8 x i32>208 %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>209 ret <4 x i32> %strided.vec210}211 212define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214(<16 x i16> %src) {213; CHECK-LABEL: zext_i32_02468101214:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vmovlb.u16 q0, q0216; CHECK-NEXT: vmovlb.u16 q1, q1217; CHECK-NEXT: bx lr218entry:219 %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>220 %out = zext <8 x i16> %strided.vec to <8 x i32>221 ret <8 x i32> %out222}223 224define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214_swapped(<16 x i16> %src) {225; CHECK-LABEL: zext_i32_02468101214_swapped:226; CHECK: @ %bb.0: @ %entry227; CHECK-NEXT: .pad #32228; CHECK-NEXT: sub sp, #32229; CHECK-NEXT: mov r0, sp230; CHECK-NEXT: add r1, sp, #16231; CHECK-NEXT: vstrw.32 q0, [r0]232; CHECK-NEXT: vstrw.32 q1, [r1]233; CHECK-NEXT: vldrh.u32 q0, [r0]234; CHECK-NEXT: vldrh.u32 q1, [r0, #8]235; CHECK-NEXT: vldrh.u32 q2, [r1, #8]236; CHECK-NEXT: vmov.f32 s1, s2237; CHECK-NEXT: vmov.f32 s2, s4238; CHECK-NEXT: vmov.f32 s3, s6239; CHECK-NEXT: vldrh.u32 q1, [r1]240; CHECK-NEXT: vmov.f32 s7, s10241; CHECK-NEXT: vmov.f32 s5, s6242; CHECK-NEXT: vmov.f32 s6, s8243; CHECK-NEXT: add sp, #32244; CHECK-NEXT: bx lr245entry:246 %out = zext <16 x i16> %src to <16 x i32>247 %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>248 ret <8 x i32> %strided.vec249}250 251define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315(<16 x i16> %src) {252; CHECK-LABEL: zext_i32_13579111315:253; CHECK: @ %bb.0: @ %entry254; CHECK-NEXT: vmovlt.u16 q0, q0255; CHECK-NEXT: vmovlt.u16 q1, q1256; CHECK-NEXT: bx lr257entry:258 %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>259 %out = zext <8 x i16> %strided.vec to <8 x i32>260 ret <8 x i32> %out261}262 263define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315_swapped(<16 x i16> %src) {264; CHECK-LABEL: zext_i32_13579111315_swapped:265; CHECK: @ %bb.0: @ %entry266; CHECK-NEXT: .pad #32267; CHECK-NEXT: sub sp, #32268; CHECK-NEXT: mov r0, sp269; CHECK-NEXT: add r1, sp, #16270; CHECK-NEXT: vstrw.32 q0, [r0]271; CHECK-NEXT: vstrw.32 q1, [r1]272; CHECK-NEXT: vldrh.u32 q0, [r0]273; CHECK-NEXT: vldrh.u32 q1, [r0, #8]274; CHECK-NEXT: vldrh.u32 q2, [r1, #8]275; CHECK-NEXT: vmov.f32 s0, s1276; CHECK-NEXT: vmov.f32 s1, s3277; CHECK-NEXT: vmov.f32 s2, s5278; CHECK-NEXT: vmov.f32 s3, s7279; CHECK-NEXT: vldrh.u32 q1, [r1]280; CHECK-NEXT: vmov.f32 s6, s9281; CHECK-NEXT: vmov.f32 s4, s5282; CHECK-NEXT: vmov.f32 s5, s7283; CHECK-NEXT: vmov.f32 s7, s11284; CHECK-NEXT: add sp, #32285; CHECK-NEXT: bx lr286entry:287 %out = zext <16 x i16> %src to <16 x i32>288 %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>289 ret <8 x i32> %strided.vec290}291 292define arm_aapcs_vfpcc <8 x i32> @sext_i32_02481357(<8 x i16> %src) {293; CHECK-LABEL: sext_i32_02481357:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vmovlb.s16 q2, q0296; CHECK-NEXT: vmovlt.s16 q1, q0297; CHECK-NEXT: vmov q0, q2298; CHECK-NEXT: bx lr299entry:300 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>301 %out = sext <8 x i16> %strided.vec to <8 x i32>302 ret <8 x i32> %out303}304 305 306; i8 -> i16307 308define arm_aapcs_vfpcc <8 x i16> @sext_i16_02468101214(<16 x i8> %src) {309; CHECK-LABEL: sext_i16_02468101214:310; CHECK: @ %bb.0: @ %entry311; CHECK-NEXT: vmovlb.s8 q0, q0312; CHECK-NEXT: bx lr313entry:314 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>315 %out = sext <8 x i8> %strided.vec to <8 x i16>316 ret <8 x i16> %out317}318 319define arm_aapcs_vfpcc <8 x i16> @sext_i16_13579111315(<16 x i8> %src) {320; CHECK-LABEL: sext_i16_13579111315:321; CHECK: @ %bb.0: @ %entry322; CHECK-NEXT: vmovlt.s8 q0, q0323; CHECK-NEXT: bx lr324entry:325 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>326 %out = sext <8 x i8> %strided.vec to <8 x i16>327 ret <8 x i16> %out328}329 330define arm_aapcs_vfpcc <16 x i16> @sext_i16_024681012141618202224262830(<32 x i8> %src) {331; CHECK-LABEL: sext_i16_024681012141618202224262830:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vmovlb.s8 q0, q0334; CHECK-NEXT: vmovlb.s8 q1, q1335; CHECK-NEXT: bx lr336entry:337 %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>338 %out = sext <16 x i8> %strided.vec to <16 x i16>339 ret <16 x i16> %out340}341 342define arm_aapcs_vfpcc <16 x i16> @sext_i16_135791113151719212325272931(<32 x i8> %src) {343; CHECK-LABEL: sext_i16_135791113151719212325272931:344; CHECK: @ %bb.0: @ %entry345; CHECK-NEXT: vmovlt.s8 q0, q0346; CHECK-NEXT: vmovlt.s8 q1, q1347; CHECK-NEXT: bx lr348entry:349 %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>350 %out = sext <16 x i8> %strided.vec to <16 x i16>351 ret <16 x i16> %out352}353 354define arm_aapcs_vfpcc <8 x i16> @zext_i16_02468101214(<16 x i8> %src) {355; CHECK-LABEL: zext_i16_02468101214:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vmovlb.u8 q0, q0358; CHECK-NEXT: bx lr359entry:360 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>361 %out = zext <8 x i8> %strided.vec to <8 x i16>362 ret <8 x i16> %out363}364 365define arm_aapcs_vfpcc <8 x i16> @zext_i16_13579111315(<16 x i8> %src) {366; CHECK-LABEL: zext_i16_13579111315:367; CHECK: @ %bb.0: @ %entry368; CHECK-NEXT: vmovlt.u8 q0, q0369; CHECK-NEXT: bx lr370entry:371 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>372 %out = zext <8 x i8> %strided.vec to <8 x i16>373 ret <8 x i16> %out374}375 376define arm_aapcs_vfpcc <16 x i16> @zext_i16_024681012141618202224262830(<32 x i8> %src) {377; CHECK-LABEL: zext_i16_024681012141618202224262830:378; CHECK: @ %bb.0: @ %entry379; CHECK-NEXT: vmovlb.u8 q0, q0380; CHECK-NEXT: vmovlb.u8 q1, q1381; CHECK-NEXT: bx lr382entry:383 %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>384 %out = zext <16 x i8> %strided.vec to <16 x i16>385 ret <16 x i16> %out386}387 388define arm_aapcs_vfpcc <16 x i16> @zext_i16_135791113151719212325272931(<32 x i8> %src) {389; CHECK-LABEL: zext_i16_135791113151719212325272931:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vmovlt.u8 q0, q0392; CHECK-NEXT: vmovlt.u8 q1, q1393; CHECK-NEXT: bx lr394entry:395 %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>396 %out = zext <16 x i8> %strided.vec to <16 x i16>397 ret <16 x i16> %out398}399 400 401; f16 -> f32402 403define arm_aapcs_vfpcc <4 x float> @fpext_0246(<8 x half> %src) {404; CHECK-LABEL: fpext_0246:405; CHECK: @ %bb.0: @ %entry406; CHECK-NEXT: vcvtb.f32.f16 q0, q0407; CHECK-NEXT: bx lr408entry:409 %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>410 %out = fpext <4 x half> %strided.vec to <4 x float>411 ret <4 x float> %out412}413 414define arm_aapcs_vfpcc <4 x float> @fpext_1357(<8 x half> %src) {415; CHECK-LABEL: fpext_1357:416; CHECK: @ %bb.0: @ %entry417; CHECK-NEXT: vcvtt.f32.f16 q0, q0418; CHECK-NEXT: bx lr419entry:420 %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>421 %out = fpext <4 x half> %strided.vec to <4 x float>422 ret <4 x float> %out423}424 425define arm_aapcs_vfpcc <8 x float> @fpext_02468101214(<16 x half> %src) {426; CHECK-LABEL: fpext_02468101214:427; CHECK: @ %bb.0: @ %entry428; CHECK-NEXT: vcvtb.f32.f16 q0, q0429; CHECK-NEXT: vcvtb.f32.f16 q1, q1430; CHECK-NEXT: bx lr431entry:432 %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>433 %out = fpext <8 x half> %strided.vec to <8 x float>434 ret <8 x float> %out435}436 437define arm_aapcs_vfpcc <8 x float> @fpext_13579111315(<16 x half> %src) {438; CHECK-LABEL: fpext_13579111315:439; CHECK: @ %bb.0: @ %entry440; CHECK-NEXT: vcvtt.f32.f16 q0, q0441; CHECK-NEXT: vcvtt.f32.f16 q1, q1442; CHECK-NEXT: bx lr443entry:444 %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>445 %out = fpext <8 x half> %strided.vec to <8 x float>446 ret <8 x float> %out447}448