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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s4 5; i166 7define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_45670123(<8 x i16> %s1, <8 x i16> %s2) {8; CHECK-LABEL: shuffle_i16_45670123:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: vmov.f32 s4, s211; CHECK-NEXT: vmov.f32 s6, s012; CHECK-NEXT: vmov.f32 s5, s313; CHECK-NEXT: vmov.f32 s7, s114; CHECK-NEXT: vmov q0, q115; CHECK-NEXT: bx lr16entry:17 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>18 ret <8 x i16> %out19}20 21define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_67452301(<8 x i16> %s1, <8 x i16> %s2) {22; CHECK-LABEL: shuffle_i16_67452301:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vmov.f32 s4, s325; CHECK-NEXT: vmov.f32 s5, s226; CHECK-NEXT: vmov.f32 s6, s127; CHECK-NEXT: vmov.f32 s7, s028; CHECK-NEXT: vmov q0, q129; CHECK-NEXT: bx lr30entry:31 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>32 ret <8 x i16> %out33}34 35define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) {36; CHECK-LABEL: shuffle_i16_76543210:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: vrev64.16 q1, q039; CHECK-NEXT: vmov.f32 s0, s640; CHECK-NEXT: vmov.f32 s1, s741; CHECK-NEXT: vmov.f32 s2, s442; CHECK-NEXT: vmov.f32 s3, s543; CHECK-NEXT: bx lr44entry:45 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>46 ret <8 x i16> %out47}48 49define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_01234567(<8 x i16> %s1, <8 x i16> %s2) {50; CHECK-LABEL: shuffle_i16_01234567:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: bx lr53entry:54 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>55 ret <8 x i16> %out56}57 58define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_0123cdef(<8 x i16> %s1, <8 x i16> %s2) {59; CHECK-LABEL: shuffle_i16_0123cdef:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: vmov.f32 s2, s662; CHECK-NEXT: vmov.f32 s3, s763; CHECK-NEXT: bx lr64entry:65 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>66 ret <8 x i16> %out67}68 69define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_u7u5u3u1(<8 x i16> %s1, <8 x i16> %s2) {70; CHECK-LABEL: shuffle_i16_u7u5u3u1:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vmov.f32 s4, s373; CHECK-NEXT: vmov.f32 s5, s274; CHECK-NEXT: vmov.f32 s6, s175; CHECK-NEXT: vmov.f32 s7, s076; CHECK-NEXT: vmov q0, q177; CHECK-NEXT: bx lr78entry:79 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 undef, i32 7, i32 undef, i32 5, i32 undef, i32 3, i32 undef, i32 1>80 ret <8 x i16> %out81}82 83define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_6u4u2u0u(<8 x i16> %s1, <8 x i16> %s2) {84; CHECK-LABEL: shuffle_i16_6u4u2u0u:85; CHECK: @ %bb.0: @ %entry86; CHECK-NEXT: vmov.f32 s4, s387; CHECK-NEXT: vmov.f32 s5, s288; CHECK-NEXT: vmov.f32 s6, s189; CHECK-NEXT: vmov.f32 s7, s090; CHECK-NEXT: vmov q0, q191; CHECK-NEXT: bx lr92entry:93 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 6, i32 undef, i32 4, i32 undef, i32 2, i32 undef, i32 0, i32 undef>94 ret <8 x i16> %out95}96 97define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_0uuuuuuu(<8 x i16> %s1, <8 x i16> %s2) {98; CHECK-LABEL: shuffle_i16_0uuuuuuu:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: bx lr101entry:102 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>103 ret <8 x i16> %out104}105 106define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_uuuu0uuu(<8 x i16> %s1, <8 x i16> %s2) {107; CHECK-LABEL: shuffle_i16_uuuu0uuu:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmov.u16 r0, q0[0]110; CHECK-NEXT: vdup.16 q0, r0111; CHECK-NEXT: bx lr112entry:113 %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef>114 ret <8 x i16> %out115}116 117 118; i8119 120define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdef89ab45670123(<16 x i8> %s1, <16 x i8> %s2) {121; CHECK-LABEL: shuffle_i8_cdef89ab45670123:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vmov.f32 s4, s3124; CHECK-NEXT: vmov.f32 s5, s2125; CHECK-NEXT: vmov.f32 s6, s1126; CHECK-NEXT: vmov.f32 s7, s0127; CHECK-NEXT: vmov q0, q1128; CHECK-NEXT: bx lr129entry:130 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>131 ret <16 x i8> %out132}133 134define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_efcdab8967452301(<16 x i8> %s1, <16 x i8> %s2) {135; CHECK-LABEL: shuffle_i8_efcdab8967452301:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vmov q1, q0138; CHECK-NEXT: vmov.u8 r0, q0[14]139; CHECK-NEXT: vmov.8 q0[0], r0140; CHECK-NEXT: vmov.u8 r0, q1[15]141; CHECK-NEXT: vmov.8 q0[1], r0142; CHECK-NEXT: vmov.u8 r0, q1[12]143; CHECK-NEXT: vmov.8 q0[2], r0144; CHECK-NEXT: vmov.u8 r0, q1[13]145; CHECK-NEXT: vmov.8 q0[3], r0146; CHECK-NEXT: vmov.u8 r0, q1[10]147; CHECK-NEXT: vmov.8 q0[4], r0148; CHECK-NEXT: vmov.u8 r0, q1[11]149; CHECK-NEXT: vmov.8 q0[5], r0150; CHECK-NEXT: vmov.u8 r0, q1[8]151; CHECK-NEXT: vmov.8 q0[6], r0152; CHECK-NEXT: vmov.u8 r0, q1[9]153; CHECK-NEXT: vmov.8 q0[7], r0154; CHECK-NEXT: vmov.u8 r0, q1[6]155; CHECK-NEXT: vmov.8 q0[8], r0156; CHECK-NEXT: vmov.u8 r0, q1[7]157; CHECK-NEXT: vmov.8 q0[9], r0158; CHECK-NEXT: vmov.u8 r0, q1[4]159; CHECK-NEXT: vmov.8 q0[10], r0160; CHECK-NEXT: vmov.u8 r0, q1[5]161; CHECK-NEXT: vmov.8 q0[11], r0162; CHECK-NEXT: vmov.u8 r0, q1[2]163; CHECK-NEXT: vmov.8 q0[12], r0164; CHECK-NEXT: vmov.u8 r0, q1[3]165; CHECK-NEXT: vmov.8 q0[13], r0166; CHECK-NEXT: vmov.u8 r0, q1[0]167; CHECK-NEXT: vmov.8 q0[14], r0168; CHECK-NEXT: vmov.u8 r0, q1[1]169; CHECK-NEXT: vmov.8 q0[15], r0170; CHECK-NEXT: bx lr171entry:172 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 14, i32 15, i32 12, i32 13, i32 10, i32 11, i32 8, i32 9, i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>173 ret <16 x i8> %out174}175 176define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_fedcba9876543210(<16 x i8> %s1, <16 x i8> %s2) {177; CHECK-LABEL: shuffle_i8_fedcba9876543210:178; CHECK: @ %bb.0: @ %entry179; CHECK-NEXT: vrev64.8 q1, q0180; CHECK-NEXT: vmov.f32 s0, s6181; CHECK-NEXT: vmov.f32 s1, s7182; CHECK-NEXT: vmov.f32 s2, s4183; CHECK-NEXT: vmov.f32 s3, s5184; CHECK-NEXT: bx lr185entry:186 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>187 ret <16 x i8> %out188}189 190define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_0123456789abcdef(<16 x i8> %s1, <16 x i8> %s2) {191; CHECK-LABEL: shuffle_i8_0123456789abcdef:192; CHECK: @ %bb.0: @ %entry193; CHECK-NEXT: bx lr194entry:195 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>196 ret <16 x i8> %out197}198 199define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_0123ghij4567klmn(<16 x i8> %s1, <16 x i8> %s2) {200; CHECK-LABEL: shuffle_i8_0123ghij4567klmn:201; CHECK: @ %bb.0: @ %entry202; CHECK-NEXT: vmov.f32 s8, s0203; CHECK-NEXT: vmov.f32 s9, s4204; CHECK-NEXT: vmov.f32 s10, s1205; CHECK-NEXT: vmov.f32 s11, s5206; CHECK-NEXT: vmov q0, q2207; CHECK-NEXT: bx lr208entry:209 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>210 ret <16 x i8> %out211}212 213define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdeu89ub4u67u123(<16 x i8> %s1, <16 x i8> %s2) {214; CHECK-LABEL: shuffle_i8_cdeu89ub4u67u123:215; CHECK: @ %bb.0: @ %entry216; CHECK-NEXT: vmov.f32 s4, s3217; CHECK-NEXT: vmov.f32 s5, s2218; CHECK-NEXT: vmov.f32 s6, s1219; CHECK-NEXT: vmov.f32 s7, s0220; CHECK-NEXT: vmov q0, q1221; CHECK-NEXT: bx lr222entry:223 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 undef, i32 8, i32 9, i32 undef, i32 11, i32 4, i32 undef, i32 6, i32 7, i32 undef, i32 1, i32 2, i32 3>224 ret <16 x i8> %out225}226 227define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cduu8uubuu67u12u(<16 x i8> %s1, <16 x i8> %s2) {228; CHECK-LABEL: shuffle_i8_cduu8uubuu67u12u:229; CHECK: @ %bb.0: @ %entry230; CHECK-NEXT: vmov.f32 s4, s3231; CHECK-NEXT: vmov.f32 s5, s2232; CHECK-NEXT: vmov.f32 s6, s1233; CHECK-NEXT: vmov.f32 s7, s0234; CHECK-NEXT: vmov q0, q1235; CHECK-NEXT: bx lr236entry:237 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 11, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1, i32 2, i32 undef>238 ret <16 x i8> %out239}240 241define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cuuuuuubuu6uuu2u(<16 x i8> %s1, <16 x i8> %s2) {242; CHECK-LABEL: shuffle_i8_cuuuuuubuu6uuu2u:243; CHECK: @ %bb.0: @ %entry244; CHECK-NEXT: vmov.f32 s4, s3245; CHECK-NEXT: vmov.f32 s5, s2246; CHECK-NEXT: vmov.f32 s6, s1247; CHECK-NEXT: vmov.f32 s7, s0248; CHECK-NEXT: vmov q0, q1249; CHECK-NEXT: bx lr250entry:251 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 undef, i32 undef, i32 6, i32 undef, i32 undef, i32 undef, i32 2, i32 undef>252 ret <16 x i8> %out253}254 255define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdef89ab45u700123(<16 x i8> %s1, <16 x i8> %s2) {256; CHECK-LABEL: shuffle_i8_cdef89ab45u700123:257; CHECK: @ %bb.0: @ %entry258; CHECK-NEXT: vmov.u8 r0, q0[4]259; CHECK-NEXT: vmov.8 q1[8], r0260; CHECK-NEXT: vmov.u8 r0, q0[5]261; CHECK-NEXT: vmov.8 q1[9], r0262; CHECK-NEXT: vmov.u8 r0, q0[0]263; CHECK-NEXT: vmov.8 q1[11], r0264; CHECK-NEXT: vmov.f32 s4, s3265; CHECK-NEXT: vmov.f32 s5, s2266; CHECK-NEXT: vmov.f32 s7, s0267; CHECK-NEXT: vmov q0, q1268; CHECK-NEXT: bx lr269entry:270 %out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 undef, i32 0, i32 0, i32 1, i32 2, i32 3>271 ret <16 x i8> %out272}273 274 275 276; f16277 278define arm_aapcs_vfpcc <8 x half> @shuffle_f16_45670123(<8 x half> %s1, <8 x half> %s2) {279; CHECK-LABEL: shuffle_f16_45670123:280; CHECK: @ %bb.0: @ %entry281; CHECK-NEXT: vmov.f32 s4, s2282; CHECK-NEXT: vmov.f32 s6, s0283; CHECK-NEXT: vmov.f32 s5, s3284; CHECK-NEXT: vmov.f32 s7, s1285; CHECK-NEXT: vmov q0, q1286; CHECK-NEXT: bx lr287entry:288 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>289 ret <8 x half> %out290}291 292define arm_aapcs_vfpcc <8 x half> @shuffle_f16_67452301(<8 x half> %s1, <8 x half> %s2) {293; CHECK-LABEL: shuffle_f16_67452301:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vmov.f32 s4, s3296; CHECK-NEXT: vmov.f32 s5, s2297; CHECK-NEXT: vmov.f32 s6, s1298; CHECK-NEXT: vmov.f32 s7, s0299; CHECK-NEXT: vmov q0, q1300; CHECK-NEXT: bx lr301entry:302 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>303 ret <8 x half> %out304}305 306define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) {307; CHECK-LABEL: shuffle_f16_76543210:308; CHECK: @ %bb.0: @ %entry309; CHECK-NEXT: vrev64.16 q1, q0310; CHECK-NEXT: vmov.f32 s0, s6311; CHECK-NEXT: vmov.f32 s1, s7312; CHECK-NEXT: vmov.f32 s2, s4313; CHECK-NEXT: vmov.f32 s3, s5314; CHECK-NEXT: bx lr315entry:316 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>317 ret <8 x half> %out318}319 320define arm_aapcs_vfpcc <8 x half> @shuffle_f16_01234567(<8 x half> %s1, <8 x half> %s2) {321; CHECK-LABEL: shuffle_f16_01234567:322; CHECK: @ %bb.0: @ %entry323; CHECK-NEXT: bx lr324entry:325 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>326 ret <8 x half> %out327}328 329define arm_aapcs_vfpcc <8 x half> @shuffle_f16_0123cdef(<8 x half> %s1, <8 x half> %s2) {330; CHECK-LABEL: shuffle_f16_0123cdef:331; CHECK: @ %bb.0: @ %entry332; CHECK-NEXT: vmov.f32 s2, s6333; CHECK-NEXT: vmov.f32 s3, s7334; CHECK-NEXT: bx lr335entry:336 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>337 ret <8 x half> %out338}339 340define arm_aapcs_vfpcc <8 x half> @shuffle_f16_u7u5u3u1(<8 x half> %s1, <8 x half> %s2) {341; CHECK-LABEL: shuffle_f16_u7u5u3u1:342; CHECK: @ %bb.0: @ %entry343; CHECK-NEXT: vmov.f32 s4, s3344; CHECK-NEXT: vmov.f32 s5, s2345; CHECK-NEXT: vmov.f32 s6, s1346; CHECK-NEXT: vmov.f32 s7, s0347; CHECK-NEXT: vmov q0, q1348; CHECK-NEXT: bx lr349entry:350 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 undef, i32 7, i32 undef, i32 5, i32 undef, i32 3, i32 undef, i32 1>351 ret <8 x half> %out352}353 354define arm_aapcs_vfpcc <8 x half> @shuffle_f16_6u4u2u0u(<8 x half> %s1, <8 x half> %s2) {355; CHECK-LABEL: shuffle_f16_6u4u2u0u:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vmov.f32 s4, s3358; CHECK-NEXT: vmov.f32 s5, s2359; CHECK-NEXT: vmov.f32 s6, s1360; CHECK-NEXT: vmov.f32 s7, s0361; CHECK-NEXT: vmov q0, q1362; CHECK-NEXT: bx lr363entry:364 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 6, i32 undef, i32 4, i32 undef, i32 2, i32 undef, i32 0, i32 undef>365 ret <8 x half> %out366}367 368define arm_aapcs_vfpcc <8 x half> @shuffle_f16_0uuuuuuu(<8 x half> %s1, <8 x half> %s2) {369; CHECK-LABEL: shuffle_f16_0uuuuuuu:370; CHECK: @ %bb.0: @ %entry371; CHECK-NEXT: bx lr372entry:373 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>374 ret <8 x half> %out375}376 377define arm_aapcs_vfpcc <8 x half> @shuffle_f16_uuuu0uuu(<8 x half> %s1, <8 x half> %s2) {378; CHECK-LABEL: shuffle_f16_uuuu0uuu:379; CHECK: @ %bb.0: @ %entry380; CHECK-NEXT: vmov.u16 r0, q0[0]381; CHECK-NEXT: vdup.16 q0, r0382; CHECK-NEXT: bx lr383entry:384 %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef>385 ret <8 x half> %out386}387