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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP4 5define arm_aapcs_vfpcc <16 x i8> @add_int8_t(<16 x i8> %src1, <16 x i8> %src2) {6; CHECK-LABEL: add_int8_t:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vadd.i8 q0, q0, q19; CHECK-NEXT: bx lr10entry:11 %0 = add <16 x i8> %src1, %src212 ret <16 x i8> %013}14 15define arm_aapcs_vfpcc <8 x i16> @add_int16_t(<8 x i16> %src1, <8 x i16> %src2) {16; CHECK-LABEL: add_int16_t:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: vadd.i16 q0, q0, q119; CHECK-NEXT: bx lr20entry:21 %0 = add <8 x i16> %src1, %src222 ret <8 x i16> %023}24 25define arm_aapcs_vfpcc <4 x i32> @add_int32_t(<4 x i32> %src1, <4 x i32> %src2) {26; CHECK-LABEL: add_int32_t:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: vadd.i32 q0, q0, q129; CHECK-NEXT: bx lr30entry:31 %0 = add nsw <4 x i32> %src1, %src232 ret <4 x i32> %033}34 35define arm_aapcs_vfpcc <2 x i64> @add_int64_t(<2 x i64> %src1, <2 x i64> %src2) {36; CHECK-LABEL: add_int64_t:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: .save {r4, r5, r7, lr}39; CHECK-NEXT: push {r4, r5, r7, lr}40; CHECK-NEXT: vmov lr, r12, d341; CHECK-NEXT: vmov r2, r3, d142; CHECK-NEXT: vmov r1, r0, d243; CHECK-NEXT: vmov r4, r5, d044; CHECK-NEXT: adds.w r2, r2, lr45; CHECK-NEXT: adc.w r3, r3, r1246; CHECK-NEXT: adds r1, r1, r447; CHECK-NEXT: adcs r0, r548; CHECK-NEXT: vmov q0[2], q0[0], r1, r249; CHECK-NEXT: vmov q0[3], q0[1], r0, r350; CHECK-NEXT: pop {r4, r5, r7, pc}51entry:52 %0 = add nsw <2 x i64> %src1, %src253 ret <2 x i64> %054}55 56define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) {57; CHECK-MVE-LABEL: add_float32_t:58; CHECK-MVE: @ %bb.0: @ %entry59; CHECK-MVE-NEXT: vadd.f32 s3, s7, s360; CHECK-MVE-NEXT: vadd.f32 s2, s6, s261; CHECK-MVE-NEXT: vadd.f32 s1, s5, s162; CHECK-MVE-NEXT: vadd.f32 s0, s4, s063; CHECK-MVE-NEXT: bx lr64;65; CHECK-MVEFP-LABEL: add_float32_t:66; CHECK-MVEFP: @ %bb.0: @ %entry67; CHECK-MVEFP-NEXT: vadd.f32 q0, q1, q068; CHECK-MVEFP-NEXT: bx lr69entry:70 %0 = fadd nnan ninf nsz <4 x float> %src2, %src171 ret <4 x float> %072}73 74define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) {75; CHECK-MVE-LABEL: add_float16_t:76; CHECK-MVE: @ %bb.0: @ %entry77; CHECK-MVE-NEXT: vmovx.f16 s8, s078; CHECK-MVE-NEXT: vmovx.f16 s10, s479; CHECK-MVE-NEXT: vadd.f16 s0, s4, s080; CHECK-MVE-NEXT: vadd.f16 s8, s10, s881; CHECK-MVE-NEXT: vins.f16 s0, s882; CHECK-MVE-NEXT: vmovx.f16 s4, s183; CHECK-MVE-NEXT: vmovx.f16 s8, s584; CHECK-MVE-NEXT: vadd.f16 s1, s5, s185; CHECK-MVE-NEXT: vadd.f16 s4, s8, s486; CHECK-MVE-NEXT: vmovx.f16 s8, s687; CHECK-MVE-NEXT: vins.f16 s1, s488; CHECK-MVE-NEXT: vmovx.f16 s4, s289; CHECK-MVE-NEXT: vadd.f16 s2, s6, s290; CHECK-MVE-NEXT: vadd.f16 s4, s8, s491; CHECK-MVE-NEXT: vins.f16 s2, s492; CHECK-MVE-NEXT: vmovx.f16 s4, s393; CHECK-MVE-NEXT: vmovx.f16 s6, s794; CHECK-MVE-NEXT: vadd.f16 s3, s7, s395; CHECK-MVE-NEXT: vadd.f16 s4, s6, s496; CHECK-MVE-NEXT: vins.f16 s3, s497; CHECK-MVE-NEXT: bx lr98;99; CHECK-MVEFP-LABEL: add_float16_t:100; CHECK-MVEFP: @ %bb.0: @ %entry101; CHECK-MVEFP-NEXT: vadd.f16 q0, q1, q0102; CHECK-MVEFP-NEXT: bx lr103entry:104 %0 = fadd nnan ninf nsz <8 x half> %src2, %src1105 ret <8 x half> %0106}107 108define arm_aapcs_vfpcc <2 x double> @add_float64_t(<2 x double> %src1, <2 x double> %src2) {109; CHECK-LABEL: add_float64_t:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: .save {r7, lr}112; CHECK-NEXT: push {r7, lr}113; CHECK-NEXT: .vsave {d8, d9, d10, d11}114; CHECK-NEXT: vpush {d8, d9, d10, d11}115; CHECK-NEXT: vmov q5, q1116; CHECK-NEXT: vmov q4, q0117; CHECK-NEXT: vmov r0, r1, d11118; CHECK-NEXT: vmov r2, r3, d9119; CHECK-NEXT: bl __aeabi_dadd120; CHECK-NEXT: vmov lr, r12, d10121; CHECK-NEXT: vmov r2, r3, d8122; CHECK-NEXT: vmov d9, r0, r1123; CHECK-NEXT: mov r0, lr124; CHECK-NEXT: mov r1, r12125; CHECK-NEXT: bl __aeabi_dadd126; CHECK-NEXT: vmov d8, r0, r1127; CHECK-NEXT: vmov q0, q4128; CHECK-NEXT: vpop {d8, d9, d10, d11}129; CHECK-NEXT: pop {r7, pc}130entry:131 %0 = fadd nnan ninf nsz <2 x double> %src2, %src1132 ret <2 x double> %0133}134 135 136define arm_aapcs_vfpcc <16 x i8> @sub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {137; CHECK-LABEL: sub_int8_t:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vsub.i8 q0, q1, q0140; CHECK-NEXT: bx lr141entry:142 %0 = sub <16 x i8> %src2, %src1143 ret <16 x i8> %0144}145 146define arm_aapcs_vfpcc <8 x i16> @sub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {147; CHECK-LABEL: sub_int16_t:148; CHECK: @ %bb.0: @ %entry149; CHECK-NEXT: vsub.i16 q0, q1, q0150; CHECK-NEXT: bx lr151entry:152 %0 = sub <8 x i16> %src2, %src1153 ret <8 x i16> %0154}155 156define arm_aapcs_vfpcc <4 x i32> @sub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {157; CHECK-LABEL: sub_int32_t:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: vsub.i32 q0, q1, q0160; CHECK-NEXT: bx lr161entry:162 %0 = sub nsw <4 x i32> %src2, %src1163 ret <4 x i32> %0164}165 166define arm_aapcs_vfpcc <2 x i64> @sub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {167; CHECK-LABEL: sub_int64_t:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: .save {r4, r5, r7, lr}170; CHECK-NEXT: push {r4, r5, r7, lr}171; CHECK-NEXT: vmov lr, r12, d1172; CHECK-NEXT: vmov r2, r3, d3173; CHECK-NEXT: vmov r1, r0, d0174; CHECK-NEXT: vmov r4, r5, d2175; CHECK-NEXT: subs.w r2, r2, lr176; CHECK-NEXT: sbc.w r3, r3, r12177; CHECK-NEXT: subs r1, r4, r1178; CHECK-NEXT: sbc.w r0, r5, r0179; CHECK-NEXT: vmov q0[2], q0[0], r1, r2180; CHECK-NEXT: vmov q0[3], q0[1], r0, r3181; CHECK-NEXT: pop {r4, r5, r7, pc}182entry:183 %0 = sub nsw <2 x i64> %src2, %src1184 ret <2 x i64> %0185}186 187define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) {188; CHECK-MVE-LABEL: sub_float32_t:189; CHECK-MVE: @ %bb.0: @ %entry190; CHECK-MVE-NEXT: vsub.f32 s3, s7, s3191; CHECK-MVE-NEXT: vsub.f32 s2, s6, s2192; CHECK-MVE-NEXT: vsub.f32 s1, s5, s1193; CHECK-MVE-NEXT: vsub.f32 s0, s4, s0194; CHECK-MVE-NEXT: bx lr195;196; CHECK-MVEFP-LABEL: sub_float32_t:197; CHECK-MVEFP: @ %bb.0: @ %entry198; CHECK-MVEFP-NEXT: vsub.f32 q0, q1, q0199; CHECK-MVEFP-NEXT: bx lr200entry:201 %0 = fsub nnan ninf nsz <4 x float> %src2, %src1202 ret <4 x float> %0203}204 205define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) {206; CHECK-MVE-LABEL: sub_float16_t:207; CHECK-MVE: @ %bb.0: @ %entry208; CHECK-MVE-NEXT: vmovx.f16 s8, s0209; CHECK-MVE-NEXT: vmovx.f16 s10, s4210; CHECK-MVE-NEXT: vsub.f16 s0, s4, s0211; CHECK-MVE-NEXT: vsub.f16 s8, s10, s8212; CHECK-MVE-NEXT: vins.f16 s0, s8213; CHECK-MVE-NEXT: vmovx.f16 s4, s1214; CHECK-MVE-NEXT: vmovx.f16 s8, s5215; CHECK-MVE-NEXT: vsub.f16 s1, s5, s1216; CHECK-MVE-NEXT: vsub.f16 s4, s8, s4217; CHECK-MVE-NEXT: vmovx.f16 s8, s6218; CHECK-MVE-NEXT: vins.f16 s1, s4219; CHECK-MVE-NEXT: vmovx.f16 s4, s2220; CHECK-MVE-NEXT: vsub.f16 s2, s6, s2221; CHECK-MVE-NEXT: vsub.f16 s4, s8, s4222; CHECK-MVE-NEXT: vins.f16 s2, s4223; CHECK-MVE-NEXT: vmovx.f16 s4, s3224; CHECK-MVE-NEXT: vmovx.f16 s6, s7225; CHECK-MVE-NEXT: vsub.f16 s3, s7, s3226; CHECK-MVE-NEXT: vsub.f16 s4, s6, s4227; CHECK-MVE-NEXT: vins.f16 s3, s4228; CHECK-MVE-NEXT: bx lr229;230; CHECK-MVEFP-LABEL: sub_float16_t:231; CHECK-MVEFP: @ %bb.0: @ %entry232; CHECK-MVEFP-NEXT: vsub.f16 q0, q1, q0233; CHECK-MVEFP-NEXT: bx lr234entry:235 %0 = fsub nnan ninf nsz <8 x half> %src2, %src1236 ret <8 x half> %0237}238 239define arm_aapcs_vfpcc <2 x double> @sub_float64_t(<2 x double> %src1, <2 x double> %src2) {240; CHECK-LABEL: sub_float64_t:241; CHECK: @ %bb.0: @ %entry242; CHECK-NEXT: .save {r7, lr}243; CHECK-NEXT: push {r7, lr}244; CHECK-NEXT: .vsave {d8, d9, d10, d11}245; CHECK-NEXT: vpush {d8, d9, d10, d11}246; CHECK-NEXT: vmov q5, q1247; CHECK-NEXT: vmov q4, q0248; CHECK-NEXT: vmov r0, r1, d11249; CHECK-NEXT: vmov r2, r3, d9250; CHECK-NEXT: bl __aeabi_dsub251; CHECK-NEXT: vmov lr, r12, d10252; CHECK-NEXT: vmov r2, r3, d8253; CHECK-NEXT: vmov d9, r0, r1254; CHECK-NEXT: mov r0, lr255; CHECK-NEXT: mov r1, r12256; CHECK-NEXT: bl __aeabi_dsub257; CHECK-NEXT: vmov d8, r0, r1258; CHECK-NEXT: vmov q0, q4259; CHECK-NEXT: vpop {d8, d9, d10, d11}260; CHECK-NEXT: pop {r7, pc}261entry:262 %0 = fsub nnan ninf nsz <2 x double> %src2, %src1263 ret <2 x double> %0264}265 266 267define arm_aapcs_vfpcc <16 x i8> @mul_int8_t(<16 x i8> %src1, <16 x i8> %src2) {268; CHECK-LABEL: mul_int8_t:269; CHECK: @ %bb.0: @ %entry270; CHECK-NEXT: vmul.i8 q0, q0, q1271; CHECK-NEXT: bx lr272entry:273 %0 = mul <16 x i8> %src1, %src2274 ret <16 x i8> %0275}276 277define arm_aapcs_vfpcc <8 x i16> @mul_int16_t(<8 x i16> %src1, <8 x i16> %src2) {278; CHECK-LABEL: mul_int16_t:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vmul.i16 q0, q0, q1281; CHECK-NEXT: bx lr282entry:283 %0 = mul <8 x i16> %src1, %src2284 ret <8 x i16> %0285}286 287define arm_aapcs_vfpcc <4 x i32> @mul_int32_t(<4 x i32> %src1, <4 x i32> %src2) {288; CHECK-LABEL: mul_int32_t:289; CHECK: @ %bb.0: @ %entry290; CHECK-NEXT: vmul.i32 q0, q0, q1291; CHECK-NEXT: bx lr292entry:293 %0 = mul nsw <4 x i32> %src1, %src2294 ret <4 x i32> %0295}296 297define arm_aapcs_vfpcc <2 x i64> @mul_int64_t(<2 x i64> %src1, <2 x i64> %src2) {298; CHECK-LABEL: mul_int64_t:299; CHECK: @ %bb.0: @ %entry300; CHECK-NEXT: .save {r4, r5, r6, r7, lr}301; CHECK-NEXT: push {r4, r5, r6, r7, lr}302; CHECK-NEXT: vmov r0, r1, d2303; CHECK-NEXT: vmov r2, lr, d0304; CHECK-NEXT: vmov r4, r5, d3305; CHECK-NEXT: umull r12, r3, r2, r0306; CHECK-NEXT: mla r1, r2, r1, r3307; CHECK-NEXT: vmov r2, r3, d1308; CHECK-NEXT: mla r0, lr, r0, r1309; CHECK-NEXT: umull r6, r7, r2, r4310; CHECK-NEXT: mla r2, r2, r5, r7311; CHECK-NEXT: vmov q0[2], q0[0], r12, r6312; CHECK-NEXT: mla r2, r3, r4, r2313; CHECK-NEXT: vmov q0[3], q0[1], r0, r2314; CHECK-NEXT: pop {r4, r5, r6, r7, pc}315entry:316 %0 = mul nsw <2 x i64> %src1, %src2317 ret <2 x i64> %0318}319 320define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %src2) {321; CHECK-MVE-LABEL: mul_float16_t:322; CHECK-MVE: @ %bb.0: @ %entry323; CHECK-MVE-NEXT: vmovx.f16 s8, s0324; CHECK-MVE-NEXT: vmovx.f16 s10, s4325; CHECK-MVE-NEXT: vmul.f16 s0, s4, s0326; CHECK-MVE-NEXT: vmul.f16 s8, s10, s8327; CHECK-MVE-NEXT: vins.f16 s0, s8328; CHECK-MVE-NEXT: vmovx.f16 s4, s1329; CHECK-MVE-NEXT: vmovx.f16 s8, s5330; CHECK-MVE-NEXT: vmul.f16 s1, s5, s1331; CHECK-MVE-NEXT: vmul.f16 s4, s8, s4332; CHECK-MVE-NEXT: vmovx.f16 s8, s6333; CHECK-MVE-NEXT: vins.f16 s1, s4334; CHECK-MVE-NEXT: vmovx.f16 s4, s2335; CHECK-MVE-NEXT: vmul.f16 s2, s6, s2336; CHECK-MVE-NEXT: vmul.f16 s4, s8, s4337; CHECK-MVE-NEXT: vins.f16 s2, s4338; CHECK-MVE-NEXT: vmovx.f16 s4, s3339; CHECK-MVE-NEXT: vmovx.f16 s6, s7340; CHECK-MVE-NEXT: vmul.f16 s3, s7, s3341; CHECK-MVE-NEXT: vmul.f16 s4, s6, s4342; CHECK-MVE-NEXT: vins.f16 s3, s4343; CHECK-MVE-NEXT: bx lr344;345; CHECK-MVEFP-LABEL: mul_float16_t:346; CHECK-MVEFP: @ %bb.0: @ %entry347; CHECK-MVEFP-NEXT: vmul.f16 q0, q1, q0348; CHECK-MVEFP-NEXT: bx lr349entry:350 %0 = fmul nnan ninf nsz <8 x half> %src2, %src1351 ret <8 x half> %0352}353 354define arm_aapcs_vfpcc <4 x float> @mul_float32_t(<4 x float> %src1, <4 x float> %src2) {355; CHECK-MVE-LABEL: mul_float32_t:356; CHECK-MVE: @ %bb.0: @ %entry357; CHECK-MVE-NEXT: vmul.f32 s3, s7, s3358; CHECK-MVE-NEXT: vmul.f32 s2, s6, s2359; CHECK-MVE-NEXT: vmul.f32 s1, s5, s1360; CHECK-MVE-NEXT: vmul.f32 s0, s4, s0361; CHECK-MVE-NEXT: bx lr362;363; CHECK-MVEFP-LABEL: mul_float32_t:364; CHECK-MVEFP: @ %bb.0: @ %entry365; CHECK-MVEFP-NEXT: vmul.f32 q0, q1, q0366; CHECK-MVEFP-NEXT: bx lr367entry:368 %0 = fmul nnan ninf nsz <4 x float> %src2, %src1369 ret <4 x float> %0370}371 372define arm_aapcs_vfpcc <2 x double> @mul_float64_t(<2 x double> %src1, <2 x double> %src2) {373; CHECK-LABEL: mul_float64_t:374; CHECK: @ %bb.0: @ %entry375; CHECK-NEXT: .save {r7, lr}376; CHECK-NEXT: push {r7, lr}377; CHECK-NEXT: .vsave {d8, d9, d10, d11}378; CHECK-NEXT: vpush {d8, d9, d10, d11}379; CHECK-NEXT: vmov q5, q1380; CHECK-NEXT: vmov q4, q0381; CHECK-NEXT: vmov r0, r1, d11382; CHECK-NEXT: vmov r2, r3, d9383; CHECK-NEXT: bl __aeabi_dmul384; CHECK-NEXT: vmov lr, r12, d10385; CHECK-NEXT: vmov r2, r3, d8386; CHECK-NEXT: vmov d9, r0, r1387; CHECK-NEXT: mov r0, lr388; CHECK-NEXT: mov r1, r12389; CHECK-NEXT: bl __aeabi_dmul390; CHECK-NEXT: vmov d8, r0, r1391; CHECK-NEXT: vmov q0, q4392; CHECK-NEXT: vpop {d8, d9, d10, d11}393; CHECK-NEXT: pop {r7, pc}394entry:395 %0 = fmul nnan ninf nsz <2 x double> %src2, %src1396 ret <2 x double> %0397}398 399