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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-MVE3; RUN: llc -mtriple=thumbebv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefix=CHECK-BE4; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-FP5 6define <16 x i8> @vector_add_i8(<16 x i8> %lhs, <16 x i8> %rhs) {7; CHECK-LE-LABEL: vector_add_i8:8; CHECK-LE: @ %bb.0: @ %entry9; CHECK-LE-NEXT: vmov d0, r0, r110; CHECK-LE-NEXT: mov r0, sp11; CHECK-LE-NEXT: vldrw.u32 q1, [r0]12; CHECK-LE-NEXT: vmov d1, r2, r313; CHECK-LE-NEXT: vadd.i8 q0, q0, q114; CHECK-LE-NEXT: vmov r0, r1, d015; CHECK-LE-NEXT: vmov r2, r3, d116; CHECK-LE-NEXT: bx lr17;18; CHECK-BE-LABEL: vector_add_i8:19; CHECK-BE: @ %bb.0: @ %entry20; CHECK-BE-NEXT: vmov d0, r1, r021; CHECK-BE-NEXT: mov r0, sp22; CHECK-BE-NEXT: vmov d1, r3, r223; CHECK-BE-NEXT: vrev64.8 q1, q024; CHECK-BE-NEXT: vldrb.u8 q0, [r0]25; CHECK-BE-NEXT: vadd.i8 q0, q1, q026; CHECK-BE-NEXT: vrev64.8 q1, q027; CHECK-BE-NEXT: vmov r1, r0, d228; CHECK-BE-NEXT: vmov r3, r2, d329; CHECK-BE-NEXT: bx lr30entry:31 %sum = add <16 x i8> %lhs, %rhs32 ret <16 x i8> %sum33}34 35define <8 x i16> @vector_add_i16(<8 x i16> %lhs, <8 x i16> %rhs) {36; CHECK-LE-LABEL: vector_add_i16:37; CHECK-LE: @ %bb.0: @ %entry38; CHECK-LE-NEXT: vmov d0, r0, r139; CHECK-LE-NEXT: mov r0, sp40; CHECK-LE-NEXT: vldrw.u32 q1, [r0]41; CHECK-LE-NEXT: vmov d1, r2, r342; CHECK-LE-NEXT: vadd.i16 q0, q0, q143; CHECK-LE-NEXT: vmov r0, r1, d044; CHECK-LE-NEXT: vmov r2, r3, d145; CHECK-LE-NEXT: bx lr46;47; CHECK-BE-LABEL: vector_add_i16:48; CHECK-BE: @ %bb.0: @ %entry49; CHECK-BE-NEXT: vmov d0, r1, r050; CHECK-BE-NEXT: mov r0, sp51; CHECK-BE-NEXT: vmov d1, r3, r252; CHECK-BE-NEXT: vrev64.16 q1, q053; CHECK-BE-NEXT: vldrh.u16 q0, [r0]54; CHECK-BE-NEXT: vadd.i16 q0, q1, q055; CHECK-BE-NEXT: vrev64.16 q1, q056; CHECK-BE-NEXT: vmov r1, r0, d257; CHECK-BE-NEXT: vmov r3, r2, d358; CHECK-BE-NEXT: bx lr59entry:60 %sum = add <8 x i16> %lhs, %rhs61 ret <8 x i16> %sum62}63 64define <4 x i32> @vector_add_i32(<4 x i32> %lhs, <4 x i32> %rhs) {65; CHECK-LE-LABEL: vector_add_i32:66; CHECK-LE: @ %bb.0: @ %entry67; CHECK-LE-NEXT: vmov d0, r0, r168; CHECK-LE-NEXT: mov r0, sp69; CHECK-LE-NEXT: vldrw.u32 q1, [r0]70; CHECK-LE-NEXT: vmov d1, r2, r371; CHECK-LE-NEXT: vadd.i32 q0, q0, q172; CHECK-LE-NEXT: vmov r0, r1, d073; CHECK-LE-NEXT: vmov r2, r3, d174; CHECK-LE-NEXT: bx lr75;76; CHECK-BE-LABEL: vector_add_i32:77; CHECK-BE: @ %bb.0: @ %entry78; CHECK-BE-NEXT: vmov d0, r1, r079; CHECK-BE-NEXT: mov r0, sp80; CHECK-BE-NEXT: vmov d1, r3, r281; CHECK-BE-NEXT: vrev64.32 q1, q082; CHECK-BE-NEXT: vldrw.u32 q0, [r0]83; CHECK-BE-NEXT: vadd.i32 q0, q1, q084; CHECK-BE-NEXT: vrev64.32 q1, q085; CHECK-BE-NEXT: vmov r1, r0, d286; CHECK-BE-NEXT: vmov r3, r2, d387; CHECK-BE-NEXT: bx lr88entry:89 %sum = add <4 x i32> %lhs, %rhs90 ret <4 x i32> %sum91}92 93define <2 x i64> @vector_add_i64(<2 x i64> %lhs, <2 x i64> %rhs) {94; CHECK-MVE-LABEL: vector_add_i64:95; CHECK-MVE: @ %bb.0: @ %entry96; CHECK-MVE-NEXT: .save {r7, lr}97; CHECK-MVE-NEXT: push {r7, lr}98; CHECK-MVE-NEXT: add.w r12, sp, #899; CHECK-MVE-NEXT: vldrw.u32 q0, [r12]100; CHECK-MVE-NEXT: vmov r12, lr, d0101; CHECK-MVE-NEXT: adds.w r0, r0, r12102; CHECK-MVE-NEXT: adc.w r1, r1, lr103; CHECK-MVE-NEXT: vmov r12, lr, d1104; CHECK-MVE-NEXT: adds.w r2, r2, r12105; CHECK-MVE-NEXT: adc.w r3, r3, lr106; CHECK-MVE-NEXT: pop {r7, pc}107;108; CHECK-BE-LABEL: vector_add_i64:109; CHECK-BE: @ %bb.0: @ %entry110; CHECK-BE-NEXT: .save {r7, lr}111; CHECK-BE-NEXT: push {r7, lr}112; CHECK-BE-NEXT: add.w r12, sp, #8113; CHECK-BE-NEXT: vldrw.u32 q0, [r12]114; CHECK-BE-NEXT: vmov r12, lr, d0115; CHECK-BE-NEXT: adds.w r1, r1, lr116; CHECK-BE-NEXT: adc.w r0, r0, r12117; CHECK-BE-NEXT: vmov r12, lr, d1118; CHECK-BE-NEXT: adds.w r3, r3, lr119; CHECK-BE-NEXT: adc.w r2, r2, r12120; CHECK-BE-NEXT: pop {r7, pc}121;122; CHECK-FP-LABEL: vector_add_i64:123; CHECK-FP: @ %bb.0: @ %entry124; CHECK-FP-NEXT: .save {r4, r5, r7, lr}125; CHECK-FP-NEXT: push {r4, r5, r7, lr}126; CHECK-FP-NEXT: add.w r12, sp, #16127; CHECK-FP-NEXT: vldrw.u32 q0, [r12]128; CHECK-FP-NEXT: vmov r12, lr, d0129; CHECK-FP-NEXT: vmov r4, r5, d1130; CHECK-FP-NEXT: adds.w r0, r0, r12131; CHECK-FP-NEXT: adc.w r1, r1, lr132; CHECK-FP-NEXT: adds r2, r2, r4133; CHECK-FP-NEXT: adcs r3, r5134; CHECK-FP-NEXT: pop {r4, r5, r7, pc}135entry:136 %sum = add <2 x i64> %lhs, %rhs137 ret <2 x i64> %sum138}139 140define <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) {141; CHECK-MVE-LABEL: vector_add_f16:142; CHECK-MVE: @ %bb.0: @ %entry143; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}144; CHECK-MVE-NEXT: push {r4, r5, r7, lr}145; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}146; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}147; CHECK-MVE-NEXT: vmov d8, r0, r1148; CHECK-MVE-NEXT: add r0, sp, #64149; CHECK-MVE-NEXT: vldrw.u32 q6, [r0]150; CHECK-MVE-NEXT: vmov d9, r2, r3151; CHECK-MVE-NEXT: vmov.u16 r4, q4[0]152; CHECK-MVE-NEXT: vmov.u16 r0, q6[0]153; CHECK-MVE-NEXT: bl __aeabi_h2f154; CHECK-MVE-NEXT: mov r5, r0155; CHECK-MVE-NEXT: mov r0, r4156; CHECK-MVE-NEXT: bl __aeabi_h2f157; CHECK-MVE-NEXT: mov r1, r5158; CHECK-MVE-NEXT: bl __aeabi_fadd159; CHECK-MVE-NEXT: bl __aeabi_f2h160; CHECK-MVE-NEXT: vmov.16 q5[0], r0161; CHECK-MVE-NEXT: vmov.u16 r0, q6[1]162; CHECK-MVE-NEXT: vmov.u16 r4, q4[1]163; CHECK-MVE-NEXT: bl __aeabi_h2f164; CHECK-MVE-NEXT: mov r5, r0165; CHECK-MVE-NEXT: mov r0, r4166; CHECK-MVE-NEXT: bl __aeabi_h2f167; CHECK-MVE-NEXT: mov r1, r5168; CHECK-MVE-NEXT: bl __aeabi_fadd169; CHECK-MVE-NEXT: bl __aeabi_f2h170; CHECK-MVE-NEXT: vmov.16 q5[1], r0171; CHECK-MVE-NEXT: vmov.u16 r0, q6[2]172; CHECK-MVE-NEXT: vmov.u16 r4, q4[2]173; CHECK-MVE-NEXT: bl __aeabi_h2f174; CHECK-MVE-NEXT: mov r5, r0175; CHECK-MVE-NEXT: mov r0, r4176; CHECK-MVE-NEXT: bl __aeabi_h2f177; CHECK-MVE-NEXT: mov r1, r5178; CHECK-MVE-NEXT: bl __aeabi_fadd179; CHECK-MVE-NEXT: bl __aeabi_f2h180; CHECK-MVE-NEXT: vmov.16 q5[2], r0181; CHECK-MVE-NEXT: vmov.u16 r0, q6[3]182; CHECK-MVE-NEXT: vmov.u16 r4, q4[3]183; CHECK-MVE-NEXT: bl __aeabi_h2f184; CHECK-MVE-NEXT: mov r5, r0185; CHECK-MVE-NEXT: mov r0, r4186; CHECK-MVE-NEXT: bl __aeabi_h2f187; CHECK-MVE-NEXT: mov r1, r5188; CHECK-MVE-NEXT: bl __aeabi_fadd189; CHECK-MVE-NEXT: bl __aeabi_f2h190; CHECK-MVE-NEXT: vmov.16 q5[3], r0191; CHECK-MVE-NEXT: vmov.u16 r0, q6[4]192; CHECK-MVE-NEXT: vmov.u16 r4, q4[4]193; CHECK-MVE-NEXT: bl __aeabi_h2f194; CHECK-MVE-NEXT: mov r5, r0195; CHECK-MVE-NEXT: mov r0, r4196; CHECK-MVE-NEXT: bl __aeabi_h2f197; CHECK-MVE-NEXT: mov r1, r5198; CHECK-MVE-NEXT: bl __aeabi_fadd199; CHECK-MVE-NEXT: bl __aeabi_f2h200; CHECK-MVE-NEXT: vmov.16 q5[4], r0201; CHECK-MVE-NEXT: vmov.u16 r0, q6[5]202; CHECK-MVE-NEXT: vmov.u16 r4, q4[5]203; CHECK-MVE-NEXT: bl __aeabi_h2f204; CHECK-MVE-NEXT: mov r5, r0205; CHECK-MVE-NEXT: mov r0, r4206; CHECK-MVE-NEXT: bl __aeabi_h2f207; CHECK-MVE-NEXT: mov r1, r5208; CHECK-MVE-NEXT: bl __aeabi_fadd209; CHECK-MVE-NEXT: bl __aeabi_f2h210; CHECK-MVE-NEXT: vmov.16 q5[5], r0211; CHECK-MVE-NEXT: vmov.u16 r0, q6[6]212; CHECK-MVE-NEXT: vmov.u16 r4, q4[6]213; CHECK-MVE-NEXT: bl __aeabi_h2f214; CHECK-MVE-NEXT: mov r5, r0215; CHECK-MVE-NEXT: mov r0, r4216; CHECK-MVE-NEXT: bl __aeabi_h2f217; CHECK-MVE-NEXT: mov r1, r5218; CHECK-MVE-NEXT: bl __aeabi_fadd219; CHECK-MVE-NEXT: bl __aeabi_f2h220; CHECK-MVE-NEXT: vmov.16 q5[6], r0221; CHECK-MVE-NEXT: vmov.u16 r0, q6[7]222; CHECK-MVE-NEXT: vmov.u16 r4, q4[7]223; CHECK-MVE-NEXT: bl __aeabi_h2f224; CHECK-MVE-NEXT: mov r5, r0225; CHECK-MVE-NEXT: mov r0, r4226; CHECK-MVE-NEXT: bl __aeabi_h2f227; CHECK-MVE-NEXT: mov r1, r5228; CHECK-MVE-NEXT: bl __aeabi_fadd229; CHECK-MVE-NEXT: bl __aeabi_f2h230; CHECK-MVE-NEXT: vmov.16 q5[7], r0231; CHECK-MVE-NEXT: vmov r0, r1, d10232; CHECK-MVE-NEXT: vmov r2, r3, d11233; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}234; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}235;236; CHECK-BE-LABEL: vector_add_f16:237; CHECK-BE: @ %bb.0: @ %entry238; CHECK-BE-NEXT: .save {r4, r5, r7, lr}239; CHECK-BE-NEXT: push {r4, r5, r7, lr}240; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}241; CHECK-BE-NEXT: vpush {d8, d9, d10, d11, d12, d13}242; CHECK-BE-NEXT: vmov d0, r1, r0243; CHECK-BE-NEXT: add r0, sp, #64244; CHECK-BE-NEXT: vldrh.u16 q6, [r0]245; CHECK-BE-NEXT: vmov d1, r3, r2246; CHECK-BE-NEXT: vrev64.16 q4, q0247; CHECK-BE-NEXT: vmov.u16 r0, q6[0]248; CHECK-BE-NEXT: vmov.u16 r4, q4[0]249; CHECK-BE-NEXT: bl __aeabi_h2f250; CHECK-BE-NEXT: mov r5, r0251; CHECK-BE-NEXT: mov r0, r4252; CHECK-BE-NEXT: bl __aeabi_h2f253; CHECK-BE-NEXT: mov r1, r5254; CHECK-BE-NEXT: bl __aeabi_fadd255; CHECK-BE-NEXT: bl __aeabi_f2h256; CHECK-BE-NEXT: vmov.16 q5[0], r0257; CHECK-BE-NEXT: vmov.u16 r0, q6[1]258; CHECK-BE-NEXT: vmov.u16 r4, q4[1]259; CHECK-BE-NEXT: bl __aeabi_h2f260; CHECK-BE-NEXT: mov r5, r0261; CHECK-BE-NEXT: mov r0, r4262; CHECK-BE-NEXT: bl __aeabi_h2f263; CHECK-BE-NEXT: mov r1, r5264; CHECK-BE-NEXT: bl __aeabi_fadd265; CHECK-BE-NEXT: bl __aeabi_f2h266; CHECK-BE-NEXT: vmov.16 q5[1], r0267; CHECK-BE-NEXT: vmov.u16 r0, q6[2]268; CHECK-BE-NEXT: vmov.u16 r4, q4[2]269; CHECK-BE-NEXT: bl __aeabi_h2f270; CHECK-BE-NEXT: mov r5, r0271; CHECK-BE-NEXT: mov r0, r4272; CHECK-BE-NEXT: bl __aeabi_h2f273; CHECK-BE-NEXT: mov r1, r5274; CHECK-BE-NEXT: bl __aeabi_fadd275; CHECK-BE-NEXT: bl __aeabi_f2h276; CHECK-BE-NEXT: vmov.16 q5[2], r0277; CHECK-BE-NEXT: vmov.u16 r0, q6[3]278; CHECK-BE-NEXT: vmov.u16 r4, q4[3]279; CHECK-BE-NEXT: bl __aeabi_h2f280; CHECK-BE-NEXT: mov r5, r0281; CHECK-BE-NEXT: mov r0, r4282; CHECK-BE-NEXT: bl __aeabi_h2f283; CHECK-BE-NEXT: mov r1, r5284; CHECK-BE-NEXT: bl __aeabi_fadd285; CHECK-BE-NEXT: bl __aeabi_f2h286; CHECK-BE-NEXT: vmov.16 q5[3], r0287; CHECK-BE-NEXT: vmov.u16 r0, q6[4]288; CHECK-BE-NEXT: vmov.u16 r4, q4[4]289; CHECK-BE-NEXT: bl __aeabi_h2f290; CHECK-BE-NEXT: mov r5, r0291; CHECK-BE-NEXT: mov r0, r4292; CHECK-BE-NEXT: bl __aeabi_h2f293; CHECK-BE-NEXT: mov r1, r5294; CHECK-BE-NEXT: bl __aeabi_fadd295; CHECK-BE-NEXT: bl __aeabi_f2h296; CHECK-BE-NEXT: vmov.16 q5[4], r0297; CHECK-BE-NEXT: vmov.u16 r0, q6[5]298; CHECK-BE-NEXT: vmov.u16 r4, q4[5]299; CHECK-BE-NEXT: bl __aeabi_h2f300; CHECK-BE-NEXT: mov r5, r0301; CHECK-BE-NEXT: mov r0, r4302; CHECK-BE-NEXT: bl __aeabi_h2f303; CHECK-BE-NEXT: mov r1, r5304; CHECK-BE-NEXT: bl __aeabi_fadd305; CHECK-BE-NEXT: bl __aeabi_f2h306; CHECK-BE-NEXT: vmov.16 q5[5], r0307; CHECK-BE-NEXT: vmov.u16 r0, q6[6]308; CHECK-BE-NEXT: vmov.u16 r4, q4[6]309; CHECK-BE-NEXT: bl __aeabi_h2f310; CHECK-BE-NEXT: mov r5, r0311; CHECK-BE-NEXT: mov r0, r4312; CHECK-BE-NEXT: bl __aeabi_h2f313; CHECK-BE-NEXT: mov r1, r5314; CHECK-BE-NEXT: bl __aeabi_fadd315; CHECK-BE-NEXT: bl __aeabi_f2h316; CHECK-BE-NEXT: vmov.16 q5[6], r0317; CHECK-BE-NEXT: vmov.u16 r0, q6[7]318; CHECK-BE-NEXT: vmov.u16 r4, q4[7]319; CHECK-BE-NEXT: bl __aeabi_h2f320; CHECK-BE-NEXT: mov r5, r0321; CHECK-BE-NEXT: mov r0, r4322; CHECK-BE-NEXT: bl __aeabi_h2f323; CHECK-BE-NEXT: mov r1, r5324; CHECK-BE-NEXT: bl __aeabi_fadd325; CHECK-BE-NEXT: bl __aeabi_f2h326; CHECK-BE-NEXT: vmov.16 q5[7], r0327; CHECK-BE-NEXT: vrev64.16 q0, q5328; CHECK-BE-NEXT: vmov r1, r0, d0329; CHECK-BE-NEXT: vmov r3, r2, d1330; CHECK-BE-NEXT: vpop {d8, d9, d10, d11, d12, d13}331; CHECK-BE-NEXT: pop {r4, r5, r7, pc}332;333; CHECK-FP-LABEL: vector_add_f16:334; CHECK-FP: @ %bb.0: @ %entry335; CHECK-FP-NEXT: vmov d0, r0, r1336; CHECK-FP-NEXT: mov r0, sp337; CHECK-FP-NEXT: vldrw.u32 q1, [r0]338; CHECK-FP-NEXT: vmov d1, r2, r3339; CHECK-FP-NEXT: vadd.f16 q0, q0, q1340; CHECK-FP-NEXT: vmov r0, r1, d0341; CHECK-FP-NEXT: vmov r2, r3, d1342; CHECK-FP-NEXT: bx lr343entry:344 %sum = fadd <8 x half> %lhs, %rhs345 ret <8 x half> %sum346}347 348define <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {349; CHECK-MVE-LABEL: vector_add_f32:350; CHECK-MVE: @ %bb.0: @ %entry351; CHECK-MVE-NEXT: .save {r4, r5, r6, r7, r8, lr}352; CHECK-MVE-NEXT: push.w {r4, r5, r6, r7, r8, lr}353; CHECK-MVE-NEXT: .vsave {d8, d9}354; CHECK-MVE-NEXT: vpush {d8, d9}355; CHECK-MVE-NEXT: mov r8, r0356; CHECK-MVE-NEXT: add r0, sp, #40357; CHECK-MVE-NEXT: vldrw.u32 q4, [r0]358; CHECK-MVE-NEXT: mov r7, r1359; CHECK-MVE-NEXT: mov r0, r3360; CHECK-MVE-NEXT: mov r6, r2361; CHECK-MVE-NEXT: vmov r4, r1, d9362; CHECK-MVE-NEXT: bl __aeabi_fadd363; CHECK-MVE-NEXT: mov r5, r0364; CHECK-MVE-NEXT: mov r0, r6365; CHECK-MVE-NEXT: mov r1, r4366; CHECK-MVE-NEXT: bl __aeabi_fadd367; CHECK-MVE-NEXT: vmov r6, r1, d8368; CHECK-MVE-NEXT: mov r4, r0369; CHECK-MVE-NEXT: mov r0, r7370; CHECK-MVE-NEXT: bl __aeabi_fadd371; CHECK-MVE-NEXT: mov r7, r0372; CHECK-MVE-NEXT: mov r0, r8373; CHECK-MVE-NEXT: mov r1, r6374; CHECK-MVE-NEXT: bl __aeabi_fadd375; CHECK-MVE-NEXT: mov r1, r7376; CHECK-MVE-NEXT: mov r2, r4377; CHECK-MVE-NEXT: mov r3, r5378; CHECK-MVE-NEXT: vpop {d8, d9}379; CHECK-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, pc}380;381; CHECK-BE-LABEL: vector_add_f32:382; CHECK-BE: @ %bb.0: @ %entry383; CHECK-BE-NEXT: .save {r4, r5, r7, lr}384; CHECK-BE-NEXT: push {r4, r5, r7, lr}385; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11}386; CHECK-BE-NEXT: vpush {d8, d9, d10, d11}387; CHECK-BE-NEXT: vmov d0, r1, r0388; CHECK-BE-NEXT: add r1, sp, #48389; CHECK-BE-NEXT: vldrw.u32 q5, [r1]390; CHECK-BE-NEXT: vmov d1, r3, r2391; CHECK-BE-NEXT: vrev64.32 q4, q0392; CHECK-BE-NEXT: vmov r4, r0, d9393; CHECK-BE-NEXT: vmov r5, r1, d11394; CHECK-BE-NEXT: bl __aeabi_fadd395; CHECK-BE-NEXT: vmov s19, r0396; CHECK-BE-NEXT: mov r0, r4397; CHECK-BE-NEXT: mov r1, r5398; CHECK-BE-NEXT: bl __aeabi_fadd399; CHECK-BE-NEXT: vmov s18, r0400; CHECK-BE-NEXT: vmov r4, r0, d8401; CHECK-BE-NEXT: vmov r5, r1, d10402; CHECK-BE-NEXT: bl __aeabi_fadd403; CHECK-BE-NEXT: vmov s17, r0404; CHECK-BE-NEXT: mov r0, r4405; CHECK-BE-NEXT: mov r1, r5406; CHECK-BE-NEXT: bl __aeabi_fadd407; CHECK-BE-NEXT: vmov s16, r0408; CHECK-BE-NEXT: vrev64.32 q0, q4409; CHECK-BE-NEXT: vmov r1, r0, d0410; CHECK-BE-NEXT: vmov r3, r2, d1411; CHECK-BE-NEXT: vpop {d8, d9, d10, d11}412; CHECK-BE-NEXT: pop {r4, r5, r7, pc}413;414; CHECK-FP-LABEL: vector_add_f32:415; CHECK-FP: @ %bb.0: @ %entry416; CHECK-FP-NEXT: vmov d0, r0, r1417; CHECK-FP-NEXT: mov r0, sp418; CHECK-FP-NEXT: vldrw.u32 q1, [r0]419; CHECK-FP-NEXT: vmov d1, r2, r3420; CHECK-FP-NEXT: vadd.f32 q0, q0, q1421; CHECK-FP-NEXT: vmov r0, r1, d0422; CHECK-FP-NEXT: vmov r2, r3, d1423; CHECK-FP-NEXT: bx lr424entry:425 %sum = fadd <4 x float> %lhs, %rhs426 ret <4 x float> %sum427}428 429define <2 x double> @vector_add_f64(<2 x double> %lhs, <2 x double> %rhs) {430; CHECK-MVE-LABEL: vector_add_f64:431; CHECK-MVE: @ %bb.0: @ %entry432; CHECK-MVE-NEXT: .save {r4, r5, r6, r7, lr}433; CHECK-MVE-NEXT: push {r4, r5, r6, r7, lr}434; CHECK-MVE-NEXT: .pad #4435; CHECK-MVE-NEXT: sub sp, #4436; CHECK-MVE-NEXT: .vsave {d8, d9}437; CHECK-MVE-NEXT: vpush {d8, d9}438; CHECK-MVE-NEXT: mov r5, r0439; CHECK-MVE-NEXT: add r0, sp, #40440; CHECK-MVE-NEXT: vldrw.u32 q4, [r0]441; CHECK-MVE-NEXT: mov r4, r2442; CHECK-MVE-NEXT: mov r6, r3443; CHECK-MVE-NEXT: mov r7, r1444; CHECK-MVE-NEXT: vmov r2, r3, d9445; CHECK-MVE-NEXT: mov r0, r4446; CHECK-MVE-NEXT: mov r1, r6447; CHECK-MVE-NEXT: bl __aeabi_dadd448; CHECK-MVE-NEXT: vmov r2, r3, d8449; CHECK-MVE-NEXT: mov r4, r0450; CHECK-MVE-NEXT: mov r6, r1451; CHECK-MVE-NEXT: mov r0, r5452; CHECK-MVE-NEXT: mov r1, r7453; CHECK-MVE-NEXT: bl __aeabi_dadd454; CHECK-MVE-NEXT: mov r2, r4455; CHECK-MVE-NEXT: mov r3, r6456; CHECK-MVE-NEXT: vpop {d8, d9}457; CHECK-MVE-NEXT: add sp, #4458; CHECK-MVE-NEXT: pop {r4, r5, r6, r7, pc}459;460; CHECK-BE-LABEL: vector_add_f64:461; CHECK-BE: @ %bb.0: @ %entry462; CHECK-BE-NEXT: .save {r4, r5, r6, r7, lr}463; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}464; CHECK-BE-NEXT: .pad #4465; CHECK-BE-NEXT: sub sp, #4466; CHECK-BE-NEXT: .vsave {d8, d9}467; CHECK-BE-NEXT: vpush {d8, d9}468; CHECK-BE-NEXT: mov r5, r0469; CHECK-BE-NEXT: add r0, sp, #40470; CHECK-BE-NEXT: vldrb.u8 q0, [r0]471; CHECK-BE-NEXT: mov r6, r2472; CHECK-BE-NEXT: mov r4, r3473; CHECK-BE-NEXT: mov r7, r1474; CHECK-BE-NEXT: vrev64.8 q4, q0475; CHECK-BE-NEXT: mov r0, r6476; CHECK-BE-NEXT: vmov r3, r2, d9477; CHECK-BE-NEXT: mov r1, r4478; CHECK-BE-NEXT: bl __aeabi_dadd479; CHECK-BE-NEXT: vmov r3, r2, d8480; CHECK-BE-NEXT: mov r4, r0481; CHECK-BE-NEXT: mov r6, r1482; CHECK-BE-NEXT: mov r0, r5483; CHECK-BE-NEXT: mov r1, r7484; CHECK-BE-NEXT: bl __aeabi_dadd485; CHECK-BE-NEXT: mov r2, r4486; CHECK-BE-NEXT: mov r3, r6487; CHECK-BE-NEXT: vpop {d8, d9}488; CHECK-BE-NEXT: add sp, #4489; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}490;491; CHECK-FP-LABEL: vector_add_f64:492; CHECK-FP: @ %bb.0: @ %entry493; CHECK-FP-NEXT: .save {r4, r5, r6, r7, lr}494; CHECK-FP-NEXT: push {r4, r5, r6, r7, lr}495; CHECK-FP-NEXT: .pad #4496; CHECK-FP-NEXT: sub sp, #4497; CHECK-FP-NEXT: .vsave {d8, d9}498; CHECK-FP-NEXT: vpush {d8, d9}499; CHECK-FP-NEXT: mov r5, r2500; CHECK-FP-NEXT: add r2, sp, #40501; CHECK-FP-NEXT: vldrw.u32 q4, [r2]502; CHECK-FP-NEXT: mov r4, r3503; CHECK-FP-NEXT: vmov r2, r3, d8504; CHECK-FP-NEXT: bl __aeabi_dadd505; CHECK-FP-NEXT: vmov r2, r3, d9506; CHECK-FP-NEXT: mov r6, r0507; CHECK-FP-NEXT: mov r7, r1508; CHECK-FP-NEXT: mov r0, r5509; CHECK-FP-NEXT: mov r1, r4510; CHECK-FP-NEXT: bl __aeabi_dadd511; CHECK-FP-NEXT: mov r2, r0512; CHECK-FP-NEXT: mov r3, r1513; CHECK-FP-NEXT: mov r0, r6514; CHECK-FP-NEXT: mov r1, r7515; CHECK-FP-NEXT: vpop {d8, d9}516; CHECK-FP-NEXT: add sp, #4517; CHECK-FP-NEXT: pop {r4, r5, r6, r7, pc}518entry:519 %sum = fadd <2 x double> %lhs, %rhs520 ret <2 x double> %sum521}522 523define <4 x i32> @insertextract(i32 %x, i32 %y) {524; CHECK-LE-LABEL: insertextract:525; CHECK-LE: @ %bb.0:526; CHECK-LE-NEXT: mov r3, r1527; CHECK-LE-NEXT: mov r1, r0528; CHECK-LE-NEXT: mov r2, r0529; CHECK-LE-NEXT: bx lr530;531; CHECK-BE-LABEL: insertextract:532; CHECK-BE: @ %bb.0:533; CHECK-BE-NEXT: mov r3, r1534; CHECK-BE-NEXT: mov r1, r0535; CHECK-BE-NEXT: mov r2, r0536; CHECK-BE-NEXT: bx lr537 %1 = insertelement <4 x i32> undef, i32 %x, i32 0538 %2 = insertelement <4 x i32> %1, i32 %x, i32 1539 %3 = insertelement <4 x i32> %2, i32 %x, i32 2540 %4 = insertelement <4 x i32> %3, i32 %y, i32 3541 ret <4 x i32> %4542}543 544declare void @print_uint32x4_t(<4 x i32> %val)545define i32 @main(i64 %x, i64 %y) {546; CHECK-LE-LABEL: main:547; CHECK-LE: @ %bb.0: @ %entry548; CHECK-LE-NEXT: .save {r4, lr}549; CHECK-LE-NEXT: push {r4, lr}550; CHECK-LE-NEXT: .vsave {d8, d9}551; CHECK-LE-NEXT: vpush {d8, d9}552; CHECK-LE-NEXT: .pad #8553; CHECK-LE-NEXT: sub sp, #8554; CHECK-LE-NEXT: vmov.32 q4[2], r2555; CHECK-LE-NEXT: mov r4, r1556; CHECK-LE-NEXT: mov r1, r0557; CHECK-LE-NEXT: vmov.32 q4[3], r3558; CHECK-LE-NEXT: movs r0, #0559; CHECK-LE-NEXT: mov r2, r1560; CHECK-LE-NEXT: mov r3, r4561; CHECK-LE-NEXT: vstr d9, [sp]562; CHECK-LE-NEXT: bl print_uint32x4_t563; CHECK-LE-NEXT: movs r0, #0564; CHECK-LE-NEXT: movs r2, #1565; CHECK-LE-NEXT: mov r3, r4566; CHECK-LE-NEXT: vstr d9, [sp]567; CHECK-LE-NEXT: bl print_uint32x4_t568; CHECK-LE-NEXT: movs r0, #0569; CHECK-LE-NEXT: add sp, #8570; CHECK-LE-NEXT: vpop {d8, d9}571; CHECK-LE-NEXT: pop {r4, pc}572;573; CHECK-BE-LABEL: main:574; CHECK-BE: @ %bb.0: @ %entry575; CHECK-BE-NEXT: .save {r4, lr}576; CHECK-BE-NEXT: push {r4, lr}577; CHECK-BE-NEXT: .vsave {d8, d9}578; CHECK-BE-NEXT: vpush {d8, d9}579; CHECK-BE-NEXT: .pad #8580; CHECK-BE-NEXT: sub sp, #8581; CHECK-BE-NEXT: vmov.32 q0[2], r2582; CHECK-BE-NEXT: mov r4, r1583; CHECK-BE-NEXT: mov r1, r0584; CHECK-BE-NEXT: vmov.32 q0[3], r3585; CHECK-BE-NEXT: vrev64.32 q4, q0586; CHECK-BE-NEXT: movs r0, #0587; CHECK-BE-NEXT: mov r2, r1588; CHECK-BE-NEXT: mov r3, r4589; CHECK-BE-NEXT: vstr d9, [sp]590; CHECK-BE-NEXT: bl print_uint32x4_t591; CHECK-BE-NEXT: movs r0, #0592; CHECK-BE-NEXT: movs r2, #1593; CHECK-BE-NEXT: mov r3, r4594; CHECK-BE-NEXT: vstr d9, [sp]595; CHECK-BE-NEXT: bl print_uint32x4_t596; CHECK-BE-NEXT: movs r0, #0597; CHECK-BE-NEXT: add sp, #8598; CHECK-BE-NEXT: vpop {d8, d9}599; CHECK-BE-NEXT: pop {r4, pc}600entry:601 %a = insertelement <2 x i64> poison, i64 %x, i64 0602 %b = insertelement <2 x i64> %a, i64 %y, i64 1603 %c = bitcast <2 x i64> %b to <4 x i32>604 %i = insertelement <4 x i32> %c, i32 1, i64 0605 tail call void @print_uint32x4_t(i32 0, <4 x i32> %c)606 tail call void @print_uint32x4_t(i32 0, <4 x i32> %i)607 ret i32 0608}609