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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc void @vstrw32() {5; CHECK-LABEL: vstrw32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r7, lr}8; CHECK-NEXT: push {r7, lr}9; CHECK-NEXT: .pad #1610; CHECK-NEXT: sub sp, #1611; CHECK-NEXT: vmov.i32 q0, #0x012; CHECK-NEXT: mov r0, sp13; CHECK-NEXT: vstrw.32 q0, [sp, #8]14; CHECK-NEXT: bl func15; CHECK-NEXT: add sp, #1616; CHECK-NEXT: pop {r7, pc}17entry:18 %d = alloca [4 x i32], align 419 %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 220 store <4 x i32> zeroinitializer, ptr %g, align 221 call arm_aapcs_vfpcc void @func(ptr %d)22 ret void23}24 25define arm_aapcs_vfpcc void @vstrh16() {26; CHECK-LABEL: vstrh16:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: .save {r7, lr}29; CHECK-NEXT: push {r7, lr}30; CHECK-NEXT: .pad #1631; CHECK-NEXT: sub sp, #1632; CHECK-NEXT: vmov.i32 q0, #0x033; CHECK-NEXT: mov r0, sp34; CHECK-NEXT: vstrh.16 q0, [sp, #4]35; CHECK-NEXT: bl func36; CHECK-NEXT: add sp, #1637; CHECK-NEXT: pop {r7, pc}38entry:39 %d = alloca [8 x i16], align 240 %g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 241 store <8 x i16> zeroinitializer, ptr %g, align 242 call arm_aapcs_vfpcc void @func(ptr %d)43 ret void44}45 46define arm_aapcs_vfpcc void @vstrb8() {47; CHECK-LABEL: vstrb8:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: .save {r7, lr}50; CHECK-NEXT: push {r7, lr}51; CHECK-NEXT: .pad #1652; CHECK-NEXT: sub sp, #1653; CHECK-NEXT: vmov.i32 q0, #0x054; CHECK-NEXT: mov r0, sp55; CHECK-NEXT: vstrh.16 q0, [sp, #2]56; CHECK-NEXT: bl func57; CHECK-NEXT: add sp, #1658; CHECK-NEXT: pop {r7, pc}59entry:60 %d = alloca [16 x i8], align 461 %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 262 store <16 x i8> zeroinitializer, ptr %g, align 263 call arm_aapcs_vfpcc void @func(ptr %d)64 ret void65}66 67define arm_aapcs_vfpcc void @vstrh32() {68; CHECK-LABEL: vstrh32:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: .save {r7, lr}71; CHECK-NEXT: push {r7, lr}72; CHECK-NEXT: .pad #873; CHECK-NEXT: sub sp, #874; CHECK-NEXT: mov r0, sp75; CHECK-NEXT: vmov.i32 q0, #0x676; CHECK-NEXT: vstrh.32 q0, [r0, #4]77; CHECK-NEXT: bl func78; CHECK-NEXT: add sp, #879; CHECK-NEXT: pop {r7, pc}80entry:81 %d = alloca [4 x i16], align 482 %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 283 store <4 x i16> <i16 6, i16 6, i16 6, i16 6>, ptr %g, align 284 call arm_aapcs_vfpcc void @func(ptr %d)85 ret void86}87 88define arm_aapcs_vfpcc void @vstrb32() {89; CHECK-LABEL: vstrb32:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: .save {r7, lr}92; CHECK-NEXT: push {r7, lr}93; CHECK-NEXT: .pad #894; CHECK-NEXT: sub sp, #895; CHECK-NEXT: add r0, sp, #496; CHECK-NEXT: vmov.i32 q0, #0x697; CHECK-NEXT: vstrb.32 q0, [r0, #2]98; CHECK-NEXT: bl func99; CHECK-NEXT: add sp, #8100; CHECK-NEXT: pop {r7, pc}101entry:102 %d = alloca [4 x i8], align 4103 %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2104 store <4 x i8> <i8 6, i8 6, i8 6, i8 6>, ptr %g, align 2105 call arm_aapcs_vfpcc void @func(ptr %d)106 ret void107}108 109define arm_aapcs_vfpcc void @vstrb16() {110; CHECK-LABEL: vstrb16:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: .save {r7, lr}113; CHECK-NEXT: push {r7, lr}114; CHECK-NEXT: .pad #8115; CHECK-NEXT: sub sp, #8116; CHECK-NEXT: mov r0, sp117; CHECK-NEXT: vmov.i32 q0, #0x0118; CHECK-NEXT: vstrb.16 q0, [r0, #2]119; CHECK-NEXT: bl func120; CHECK-NEXT: add sp, #8121; CHECK-NEXT: pop {r7, pc}122entry:123 %d = alloca [8 x i8], align 4124 %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2125 store <8 x i8> zeroinitializer, ptr %g, align 2126 call arm_aapcs_vfpcc void @func(ptr %d)127 ret void128}129 130 131define arm_aapcs_vfpcc <4 x i32> @vldrw32() {132; CHECK-LABEL: vldrw32:133; CHECK: @ %bb.0: @ %entry134; CHECK-NEXT: .save {r7, lr}135; CHECK-NEXT: push {r7, lr}136; CHECK-NEXT: .pad #16137; CHECK-NEXT: sub sp, #16138; CHECK-NEXT: mov r0, sp139; CHECK-NEXT: bl func140; CHECK-NEXT: vldrw.u32 q0, [sp, #8]141; CHECK-NEXT: add sp, #16142; CHECK-NEXT: pop {r7, pc}143entry:144 %d = alloca [4 x i32], align 4145 call arm_aapcs_vfpcc void @func(ptr %d)146 %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2147 %l = load <4 x i32>, ptr %g, align 2148 ret <4 x i32> %l149}150 151define arm_aapcs_vfpcc <8 x i16> @vldrh16() {152; CHECK-LABEL: vldrh16:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: .save {r7, lr}155; CHECK-NEXT: push {r7, lr}156; CHECK-NEXT: .pad #16157; CHECK-NEXT: sub sp, #16158; CHECK-NEXT: mov r0, sp159; CHECK-NEXT: bl func160; CHECK-NEXT: vldrh.u16 q0, [sp, #4]161; CHECK-NEXT: add sp, #16162; CHECK-NEXT: pop {r7, pc}163entry:164 %d = alloca [8 x i16], align 2165 call arm_aapcs_vfpcc void @func(ptr %d)166 %g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 2167 %l = load <8 x i16>, ptr %g, align 2168 ret <8 x i16> %l169}170 171define arm_aapcs_vfpcc <16 x i8> @vldrb8() {172; CHECK-LABEL: vldrb8:173; CHECK: @ %bb.0: @ %entry174; CHECK-NEXT: .save {r7, lr}175; CHECK-NEXT: push {r7, lr}176; CHECK-NEXT: .pad #16177; CHECK-NEXT: sub sp, #16178; CHECK-NEXT: mov r0, sp179; CHECK-NEXT: bl func180; CHECK-NEXT: vldrh.u16 q0, [sp, #2]181; CHECK-NEXT: add sp, #16182; CHECK-NEXT: pop {r7, pc}183entry:184 %d = alloca [16 x i8], align 4185 call arm_aapcs_vfpcc void @func(ptr %d)186 %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2187 %l = load <16 x i8>, ptr %g, align 2188 ret <16 x i8> %l189}190 191define arm_aapcs_vfpcc <4 x i16> @vldrh32() {192; CHECK-LABEL: vldrh32:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: .save {r4, lr}195; CHECK-NEXT: push {r4, lr}196; CHECK-NEXT: .pad #8197; CHECK-NEXT: sub sp, #8198; CHECK-NEXT: mov r4, sp199; CHECK-NEXT: mov r0, r4200; CHECK-NEXT: bl func201; CHECK-NEXT: vldrh.u32 q0, [r4, #4]202; CHECK-NEXT: add sp, #8203; CHECK-NEXT: pop {r4, pc}204entry:205 %d = alloca [4 x i16], align 4206 call arm_aapcs_vfpcc void @func(ptr %d)207 %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2208 %l = load <4 x i16>, ptr %g, align 2209 ret <4 x i16> %l210}211 212define arm_aapcs_vfpcc <4 x i8> @vldrb32() {213; CHECK-LABEL: vldrb32:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: .save {r4, lr}216; CHECK-NEXT: push {r4, lr}217; CHECK-NEXT: .pad #8218; CHECK-NEXT: sub sp, #8219; CHECK-NEXT: add r4, sp, #4220; CHECK-NEXT: mov r0, r4221; CHECK-NEXT: bl func222; CHECK-NEXT: vldrb.u32 q0, [r4, #2]223; CHECK-NEXT: add sp, #8224; CHECK-NEXT: pop {r4, pc}225entry:226 %d = alloca [4 x i8], align 4227 call arm_aapcs_vfpcc void @func(ptr %d)228 %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2229 %l = load <4 x i8>, ptr %g, align 2230 ret <4 x i8> %l231}232 233define arm_aapcs_vfpcc <8 x i8> @vldrb16() {234; CHECK-LABEL: vldrb16:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: .save {r4, lr}237; CHECK-NEXT: push {r4, lr}238; CHECK-NEXT: .pad #8239; CHECK-NEXT: sub sp, #8240; CHECK-NEXT: mov r4, sp241; CHECK-NEXT: mov r0, r4242; CHECK-NEXT: bl func243; CHECK-NEXT: vldrb.u16 q0, [r4, #2]244; CHECK-NEXT: add sp, #8245; CHECK-NEXT: pop {r4, pc}246entry:247 %d = alloca [8 x i8], align 4248 call arm_aapcs_vfpcc void @func(ptr %d)249 %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2250 %l = load <8 x i8>, ptr %g, align 2251 ret <8 x i8> %l252}253 254declare dso_local arm_aapcs_vfpcc void @func(...)255