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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir --verify-machineinstrs -run-pass=finalize-isel %s -o - | FileCheck %s3# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir -passes=finalize-isel %s -o - | FileCheck %s4--- |5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6 target triple = "arm-arm-none-eabi"7 8 ; Function Attrs: argmemonly nofree nosync nounwind willreturn9 declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)10 ; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly11 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)12 13 define void @test1(ptr noalias %X, ptr noalias readonly %Y, i32 %n) {14 entry:15 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %X, ptr align 4 %Y, i32 %n, i1 false)16 ret void17 }18 19 define void @test2(ptr noalias %X, ptr noalias readonly %Y, i32 %n) {20 entry:21 %cmp6 = icmp sgt i32 %n, 022 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup23 24 for.body.preheader: ; preds = %entry25 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %X, ptr align 4 %Y, i32 %n, i1 false)26 br label %for.cond.cleanup27 28 for.cond.cleanup: ; preds = %for.body.preheader, %entry29 ret void30 }31 32 define void @test3(ptr nocapture %X, i8 zeroext %c, i32 %n) {33 entry:34 tail call void @llvm.memset.p0.i32(ptr align 4 %X, i8 %c, i32 %n, i1 false)35 ret void36 }37 38 39 define void @test4(ptr nocapture %X, i8 zeroext %c, i32 %n) {40 entry:41 %cmp4 = icmp sgt i32 %n, 042 br i1 %cmp4, label %for.body.preheader, label %for.cond.cleanup43 44 for.body.preheader: ; preds = %entry45 call void @llvm.memset.p0.i32(ptr align 1 %X, i8 %c, i32 %n, i1 false)46 br label %for.cond.cleanup47 48 for.cond.cleanup: ; preds = %for.body.preheader, %entry49 ret void50 }51 52...53---54name: test155tracksRegLiveness: true56body: |57 bb.0.entry:58 liveins: $r0, $r1, $r259 60 ; CHECK-LABEL: name: test161 ; CHECK: liveins: $r0, $r1, $r262 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r263 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r164 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r065 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg66 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg67 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]68 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr69 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg70 ; CHECK: .1:71 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %7, %bb.172 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %9, %bb.173 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %11, %bb.174 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %13, %bb.175 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg76 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg77 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg78 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg79 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 180 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr81 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg82 ; CHECK: .2.entry:83 ; CHECK: tBX_RET 14 /* CC::al */, $noreg84 %2:rgpr = COPY $r285 %1:rgpr = COPY $r186 %0:rgpr = COPY $r087 MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr88 tBX_RET 14 /* CC::al */, $noreg89 90...91---92name: test293tracksRegLiveness: true94body: |95 ; CHECK-LABEL: name: test296 ; CHECK: bb.0.entry:97 ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)98 ; CHECK: liveins: $r0, $r1, $r299 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2100 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1101 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0102 ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr103 ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr104 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg105 ; CHECK: bb.1.for.body.preheader:106 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg107 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg108 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]109 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr110 ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg111 ; CHECK: bb.3:112 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %7, %bb.3113 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %9, %bb.3114 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %11, %bb.3115 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %13, %bb.3116 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg117 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg118 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg119 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg120 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1121 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr122 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg123 ; CHECK: bb.4.for.body.preheader:124 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg125 ; CHECK: bb.2.for.cond.cleanup:126 ; CHECK: tBX_RET 14 /* CC::al */, $noreg127 bb.0.entry:128 successors: %bb.1(0x50000000), %bb.2(0x30000000)129 liveins: $r0, $r1, $r2130 131 %2:rgpr = COPY $r2132 %1:rgpr = COPY $r1133 %0:rgpr = COPY $r0134 t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr135 t2Bcc %bb.2, 11 /* CC::lt */, $cpsr136 t2B %bb.1, 14 /* CC::al */, $noreg137 138 bb.1.for.body.preheader:139 successors: %bb.2(0x80000000)140 141 MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr142 143 bb.2.for.cond.cleanup:144 tBX_RET 14 /* CC::al */, $noreg145 146...147---148name: test3149tracksRegLiveness: true150body: |151 bb.0.entry:152 liveins: $r0, $r1, $r2153 154 ; CHECK-LABEL: name: test3155 ; CHECK: liveins: $r0, $r1, $r2156 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2157 ; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1158 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0159 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg160 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg161 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]162 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr163 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg164 ; CHECK: .1:165 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %7, %bb.1166 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %9, %bb.1167 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %11, %bb.1168 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg169 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg170 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg171 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1172 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr173 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg174 ; CHECK: .2.entry:175 ; CHECK: tBX_RET 14 /* CC::al */, $noreg176 %2:rgpr = COPY $r2177 %1:mqpr = COPY $r1178 %0:rgpr = COPY $r0179 MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr180 tBX_RET 14 /* CC::al */, $noreg181 182...183---184name: test4185alignment: 2186tracksRegLiveness: true187body: |188 ; CHECK-LABEL: name: test4189 ; CHECK: bb.0.entry:190 ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)191 ; CHECK: liveins: $r0, $r1, $r2192 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2193 ; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1194 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0195 ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr196 ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr197 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg198 ; CHECK: bb.1.for.body.preheader:199 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg200 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg201 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]202 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr203 ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg204 ; CHECK: bb.3:205 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %7, %bb.3206 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %9, %bb.3207 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %11, %bb.3208 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg209 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg210 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg211 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1212 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr213 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg214 ; CHECK: bb.4.for.body.preheader:215 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg216 ; CHECK: bb.2.for.cond.cleanup:217 ; CHECK: tBX_RET 14 /* CC::al */, $noreg218 bb.0.entry:219 successors: %bb.1(0x50000000), %bb.2(0x30000000)220 liveins: $r0, $r1, $r2221 222 %2:rgpr = COPY $r2223 %1:mqpr = COPY $r1224 %0:rgpr = COPY $r0225 t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr226 t2Bcc %bb.2, 11 /* CC::lt */, $cpsr227 t2B %bb.1, 14 /* CC::al */, $noreg228 229 bb.1.for.body.preheader:230 MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr231 232 bb.2.for.cond.cleanup:233 tBX_RET 14 /* CC::al */, $noreg234 235...236