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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @vabd_v16s8(<16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: vabd_v16s8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vabd.s8 q0, q0, q18; CHECK-NEXT: bx lr9 %sextsrc1 = sext <16 x i8> %src1 to <16 x i16>10 %sextsrc2 = sext <16 x i8> %src2 to <16 x i16>11 %add1 = sub <16 x i16> %sextsrc1, %sextsrc212 %add2 = sub <16 x i16> zeroinitializer, %add113 %c = icmp sge <16 x i16> %add1, zeroinitializer14 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add215 %result = trunc <16 x i16> %s to <16 x i8>16 ret <16 x i8> %result17}18 19define arm_aapcs_vfpcc <8 x i8> @vabd_v8s8(<8 x i8> %src1, <8 x i8> %src2) {20; CHECK-LABEL: vabd_v8s8:21; CHECK: @ %bb.0:22; CHECK-NEXT: vmovlb.s8 q1, q123; CHECK-NEXT: vmovlb.s8 q0, q024; CHECK-NEXT: vabd.s16 q0, q0, q125; CHECK-NEXT: bx lr26 %sextsrc1 = sext <8 x i8> %src1 to <8 x i16>27 %sextsrc2 = sext <8 x i8> %src2 to <8 x i16>28 %add1 = sub <8 x i16> %sextsrc1, %sextsrc229 %add2 = sub <8 x i16> zeroinitializer, %add130 %c = icmp sge <8 x i16> %add1, zeroinitializer31 %s = select <8 x i1> %c, <8 x i16> %add1, <8 x i16> %add232 %result = trunc <8 x i16> %s to <8 x i8>33 ret <8 x i8> %result34}35 36define arm_aapcs_vfpcc <4 x i8> @vabd_v4s8(<4 x i8> %src1, <4 x i8> %src2) {37; CHECK-LABEL: vabd_v4s8:38; CHECK: @ %bb.0:39; CHECK-NEXT: vmovlb.s8 q1, q140; CHECK-NEXT: vmovlb.s8 q0, q041; CHECK-NEXT: vmovlb.s16 q1, q142; CHECK-NEXT: vmovlb.s16 q0, q043; CHECK-NEXT: vabd.s32 q0, q0, q144; CHECK-NEXT: bx lr45 %sextsrc1 = sext <4 x i8> %src1 to <4 x i16>46 %sextsrc2 = sext <4 x i8> %src2 to <4 x i16>47 %add1 = sub <4 x i16> %sextsrc1, %sextsrc248 %add2 = sub <4 x i16> zeroinitializer, %add149 %c = icmp sge <4 x i16> %add1, zeroinitializer50 %s = select <4 x i1> %c, <4 x i16> %add1, <4 x i16> %add251 %result = trunc <4 x i16> %s to <4 x i8>52 ret <4 x i8> %result53}54 55define arm_aapcs_vfpcc <8 x i16> @vabd_v8s16(<8 x i16> %src1, <8 x i16> %src2) {56; CHECK-LABEL: vabd_v8s16:57; CHECK: @ %bb.0:58; CHECK-NEXT: vabd.s16 q0, q0, q159; CHECK-NEXT: bx lr60 %sextsrc1 = sext <8 x i16> %src1 to <8 x i32>61 %sextsrc2 = sext <8 x i16> %src2 to <8 x i32>62 %add1 = sub <8 x i32> %sextsrc1, %sextsrc263 %add2 = sub <8 x i32> zeroinitializer, %add164 %c = icmp sge <8 x i32> %add1, zeroinitializer65 %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add266 %result = trunc <8 x i32> %s to <8 x i16>67 ret <8 x i16> %result68}69 70define arm_aapcs_vfpcc <4 x i16> @vabd_v4s16(<4 x i16> %src1, <4 x i16> %src2) {71; CHECK-LABEL: vabd_v4s16:72; CHECK: @ %bb.0:73; CHECK-NEXT: vmovlb.s16 q1, q174; CHECK-NEXT: vmovlb.s16 q0, q075; CHECK-NEXT: vabd.s32 q0, q0, q176; CHECK-NEXT: bx lr77 %sextsrc1 = sext <4 x i16> %src1 to <4 x i32>78 %sextsrc2 = sext <4 x i16> %src2 to <4 x i32>79 %add1 = sub <4 x i32> %sextsrc1, %sextsrc280 %add2 = sub <4 x i32> zeroinitializer, %add181 %c = icmp sge <4 x i32> %add1, zeroinitializer82 %s = select <4 x i1> %c, <4 x i32> %add1, <4 x i32> %add283 %result = trunc <4 x i32> %s to <4 x i16>84 ret <4 x i16> %result85}86 87define arm_aapcs_vfpcc <4 x i32> @vabd_v4s32(<4 x i32> %src1, <4 x i32> %src2) {88; CHECK-LABEL: vabd_v4s32:89; CHECK: @ %bb.0:90; CHECK-NEXT: vabd.s32 q0, q0, q191; CHECK-NEXT: bx lr92 %sextsrc1 = sext <4 x i32> %src1 to <4 x i64>93 %sextsrc2 = sext <4 x i32> %src2 to <4 x i64>94 %add1 = sub <4 x i64> %sextsrc1, %sextsrc295 %add2 = sub <4 x i64> zeroinitializer, %add196 %c = icmp sge <4 x i64> %add1, zeroinitializer97 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add298 %result = trunc <4 x i64> %s to <4 x i32>99 ret <4 x i32> %result100}101 102define arm_aapcs_vfpcc <2 x i32> @vabd_v2s32(<2 x i32> %src1, <2 x i32> %src2) {103; CHECK-LABEL: vabd_v2s32:104; CHECK: @ %bb.0:105; CHECK-NEXT: vmov r0, s2106; CHECK-NEXT: vmov r2, s6107; CHECK-NEXT: asrs r1, r0, #31108; CHECK-NEXT: subs r0, r0, r2109; CHECK-NEXT: sbc.w r1, r1, r2, asr #31110; CHECK-NEXT: eor.w r0, r0, r1, asr #31111; CHECK-NEXT: eor.w r2, r1, r1, asr #31112; CHECK-NEXT: subs.w r0, r0, r1, asr #31113; CHECK-NEXT: sbc.w r12, r2, r1, asr #31114; CHECK-NEXT: vmov r2, s0115; CHECK-NEXT: vmov r1, s4116; CHECK-NEXT: asrs r3, r2, #31117; CHECK-NEXT: subs r2, r2, r1118; CHECK-NEXT: sbc.w r1, r3, r1, asr #31119; CHECK-NEXT: eor.w r2, r2, r1, asr #31120; CHECK-NEXT: subs.w r2, r2, r1, asr #31121; CHECK-NEXT: vmov q0[2], q0[0], r2, r0122; CHECK-NEXT: eor.w r0, r1, r1, asr #31123; CHECK-NEXT: sbc.w r0, r0, r1, asr #31124; CHECK-NEXT: vmov q0[3], q0[1], r0, r12125; CHECK-NEXT: bx lr126 %sextsrc1 = sext <2 x i32> %src1 to <2 x i64>127 %sextsrc2 = sext <2 x i32> %src2 to <2 x i64>128 %add1 = sub <2 x i64> %sextsrc1, %sextsrc2129 %add2 = sub <2 x i64> zeroinitializer, %add1130 %c = icmp sge <2 x i64> %add1, zeroinitializer131 %s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2132 %result = trunc <2 x i64> %s to <2 x i32>133 ret <2 x i32> %result134}135 136define arm_aapcs_vfpcc <16 x i8> @vabd_v16u8(<16 x i8> %src1, <16 x i8> %src2) {137; CHECK-LABEL: vabd_v16u8:138; CHECK: @ %bb.0:139; CHECK-NEXT: vabd.u8 q0, q0, q1140; CHECK-NEXT: bx lr141 %zextsrc1 = zext <16 x i8> %src1 to <16 x i16>142 %zextsrc2 = zext <16 x i8> %src2 to <16 x i16>143 %add1 = sub <16 x i16> %zextsrc1, %zextsrc2144 %add2 = sub <16 x i16> zeroinitializer, %add1145 %c = icmp sge <16 x i16> %add1, zeroinitializer146 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2147 %result = trunc <16 x i16> %s to <16 x i8>148 ret <16 x i8> %result149}150 151define arm_aapcs_vfpcc <8 x i8> @vabd_v8u8(<8 x i8> %src1, <8 x i8> %src2) {152; CHECK-LABEL: vabd_v8u8:153; CHECK: @ %bb.0:154; CHECK-NEXT: vmovlb.u8 q1, q1155; CHECK-NEXT: vmovlb.u8 q0, q0156; CHECK-NEXT: vabd.u16 q0, q0, q1157; CHECK-NEXT: bx lr158 %zextsrc1 = zext <8 x i8> %src1 to <8 x i16>159 %zextsrc2 = zext <8 x i8> %src2 to <8 x i16>160 %add1 = sub <8 x i16> %zextsrc1, %zextsrc2161 %add2 = sub <8 x i16> zeroinitializer, %add1162 %c = icmp sge <8 x i16> %add1, zeroinitializer163 %s = select <8 x i1> %c, <8 x i16> %add1, <8 x i16> %add2164 %result = trunc <8 x i16> %s to <8 x i8>165 ret <8 x i8> %result166}167 168define arm_aapcs_vfpcc <4 x i8> @vabd_v4u8(<4 x i8> %src1, <4 x i8> %src2) {169; CHECK-LABEL: vabd_v4u8:170; CHECK: @ %bb.0:171; CHECK-NEXT: vmov.i32 q2, #0xff172; CHECK-NEXT: vand q1, q1, q2173; CHECK-NEXT: vand q0, q0, q2174; CHECK-NEXT: vabd.u32 q0, q0, q1175; CHECK-NEXT: bx lr176 %zextsrc1 = zext <4 x i8> %src1 to <4 x i16>177 %zextsrc2 = zext <4 x i8> %src2 to <4 x i16>178 %add1 = sub <4 x i16> %zextsrc1, %zextsrc2179 %add2 = sub <4 x i16> zeroinitializer, %add1180 %c = icmp sge <4 x i16> %add1, zeroinitializer181 %s = select <4 x i1> %c, <4 x i16> %add1, <4 x i16> %add2182 %result = trunc <4 x i16> %s to <4 x i8>183 ret <4 x i8> %result184}185 186define arm_aapcs_vfpcc <8 x i16> @vabd_v8u16(<8 x i16> %src1, <8 x i16> %src2) {187; CHECK-LABEL: vabd_v8u16:188; CHECK: @ %bb.0:189; CHECK-NEXT: vabd.u16 q0, q0, q1190; CHECK-NEXT: bx lr191 %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>192 %zextsrc2 = zext <8 x i16> %src2 to <8 x i32>193 %add1 = sub <8 x i32> %zextsrc1, %zextsrc2194 %add2 = sub <8 x i32> zeroinitializer, %add1195 %c = icmp sge <8 x i32> %add1, zeroinitializer196 %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2197 %result = trunc <8 x i32> %s to <8 x i16>198 ret <8 x i16> %result199}200 201define arm_aapcs_vfpcc <4 x i16> @vabd_v4u16(<4 x i16> %src1, <4 x i16> %src2) {202; CHECK-LABEL: vabd_v4u16:203; CHECK: @ %bb.0:204; CHECK-NEXT: vmovlb.u16 q1, q1205; CHECK-NEXT: vmovlb.u16 q0, q0206; CHECK-NEXT: vabd.u32 q0, q0, q1207; CHECK-NEXT: bx lr208 %zextsrc1 = zext <4 x i16> %src1 to <4 x i32>209 %zextsrc2 = zext <4 x i16> %src2 to <4 x i32>210 %add1 = sub <4 x i32> %zextsrc1, %zextsrc2211 %add2 = sub <4 x i32> zeroinitializer, %add1212 %c = icmp sge <4 x i32> %add1, zeroinitializer213 %s = select <4 x i1> %c, <4 x i32> %add1, <4 x i32> %add2214 %result = trunc <4 x i32> %s to <4 x i16>215 ret <4 x i16> %result216}217 218define arm_aapcs_vfpcc <4 x i32> @vabd_u32(<4 x i32> %src1, <4 x i32> %src2) {219; CHECK-LABEL: vabd_u32:220; CHECK: @ %bb.0:221; CHECK-NEXT: vabd.u32 q0, q0, q1222; CHECK-NEXT: bx lr223 %zextsrc1 = zext <4 x i32> %src1 to <4 x i64>224 %zextsrc2 = zext <4 x i32> %src2 to <4 x i64>225 %add1 = sub <4 x i64> %zextsrc1, %zextsrc2226 %add2 = sub <4 x i64> zeroinitializer, %add1227 %c = icmp sge <4 x i64> %add1, zeroinitializer228 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2229 %result = trunc <4 x i64> %s to <4 x i32>230 ret <4 x i32> %result231}232 233define arm_aapcs_vfpcc <4 x i32> @vabd_v4u32(<4 x i32> %src1, <4 x i32> %src2) {234; CHECK-LABEL: vabd_v4u32:235; CHECK: @ %bb.0:236; CHECK-NEXT: vabd.u32 q0, q0, q1237; CHECK-NEXT: bx lr238 %zextsrc1 = zext <4 x i32> %src1 to <4 x i64>239 %zextsrc2 = zext <4 x i32> %src2 to <4 x i64>240 %add1 = sub <4 x i64> %zextsrc1, %zextsrc2241 %add2 = sub <4 x i64> zeroinitializer, %add1242 %c = icmp sge <4 x i64> %add1, zeroinitializer243 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2244 %result = trunc <4 x i64> %s to <4 x i32>245 ret <4 x i32> %result246}247 248define arm_aapcs_vfpcc <2 x i32> @vabd_v2u32(<2 x i32> %src1, <2 x i32> %src2) {249; CHECK-LABEL: vabd_v2u32:250; CHECK: @ %bb.0:251; CHECK-NEXT: .save {r7, lr}252; CHECK-NEXT: push {r7, lr}253; CHECK-NEXT: vmov.i64 q2, #0xffffffff254; CHECK-NEXT: vand q1, q1, q2255; CHECK-NEXT: vand q0, q0, q2256; CHECK-NEXT: vmov r0, r1, d3257; CHECK-NEXT: vmov r2, r3, d1258; CHECK-NEXT: subs r0, r2, r0259; CHECK-NEXT: sbc.w r1, r3, r1260; CHECK-NEXT: eor.w r0, r0, r1, asr #31261; CHECK-NEXT: eor.w r2, r1, r1, asr #31262; CHECK-NEXT: subs.w lr, r0, r1, asr #31263; CHECK-NEXT: sbc.w r12, r2, r1, asr #31264; CHECK-NEXT: vmov r2, r3, d2265; CHECK-NEXT: vmov r1, r0, d0266; CHECK-NEXT: subs r1, r1, r2267; CHECK-NEXT: sbcs r0, r3268; CHECK-NEXT: eor.w r1, r1, r0, asr #31269; CHECK-NEXT: subs.w r1, r1, r0, asr #31270; CHECK-NEXT: vmov q0[2], q0[0], r1, lr271; CHECK-NEXT: eor.w r1, r0, r0, asr #31272; CHECK-NEXT: sbc.w r0, r1, r0, asr #31273; CHECK-NEXT: vmov q0[3], q0[1], r0, r12274; CHECK-NEXT: pop {r7, pc}275 %zextsrc1 = zext <2 x i32> %src1 to <2 x i64>276 %zextsrc2 = zext <2 x i32> %src2 to <2 x i64>277 %add1 = sub <2 x i64> %zextsrc1, %zextsrc2278 %add2 = sub <2 x i64> zeroinitializer, %add1279 %c = icmp sge <2 x i64> %add1, zeroinitializer280 %s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2281 %result = trunc <2 x i64> %s to <2 x i32>282 ret <2 x i32> %result283}284 285define void @vabd_loop_s8(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {286; CHECK-LABEL: vabd_loop_s8:287; CHECK: @ %bb.0: @ %entry288; CHECK-NEXT: .save {r7, lr}289; CHECK-NEXT: push {r7, lr}290; CHECK-NEXT: mov.w lr, #64291; CHECK-NEXT: .LBB15_1: @ %vector.body292; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1293; CHECK-NEXT: vldrb.u8 q0, [r1], #16294; CHECK-NEXT: vldrb.u8 q1, [r0], #16295; CHECK-NEXT: vabd.s8 q0, q1, q0296; CHECK-NEXT: vstrb.8 q0, [r2], #16297; CHECK-NEXT: le lr, .LBB15_1298; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup299; CHECK-NEXT: pop {r7, pc}300entry:301 br label %vector.body302 303vector.body: ; preds = %vector.body, %entry304 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]305 %0 = getelementptr inbounds i8, ptr %x, i32 %index306 %wide.load = load <16 x i8>, ptr %0, align 1307 %1 = sext <16 x i8> %wide.load to <16 x i32>308 %2 = getelementptr inbounds i8, ptr %y, i32 %index309 %wide.load22 = load <16 x i8>, ptr %2, align 1310 %3 = sext <16 x i8> %wide.load22 to <16 x i32>311 %4 = sub nsw <16 x i32> %1, %3312 %5 = icmp slt <16 x i32> %4, zeroinitializer313 %6 = sub nsw <16 x i32> zeroinitializer, %4314 %7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %4315 %8 = trunc <16 x i32> %7 to <16 x i8>316 %9 = getelementptr inbounds i8, ptr %z, i32 %index317 store <16 x i8> %8, ptr %9, align 1318 %index.next = add i32 %index, 16319 %10 = icmp eq i32 %index.next, 1024320 br i1 %10, label %for.cond.cleanup, label %vector.body321 322for.cond.cleanup: ; preds = %vector.body323 ret void324}325 326define void @vabd_loop_s16(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {327; CHECK-LABEL: vabd_loop_s16:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: .save {r7, lr}330; CHECK-NEXT: push {r7, lr}331; CHECK-NEXT: mov.w lr, #128332; CHECK-NEXT: .LBB16_1: @ %vector.body333; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1334; CHECK-NEXT: vldrh.u16 q0, [r1], #16335; CHECK-NEXT: vldrh.u16 q1, [r0], #16336; CHECK-NEXT: vabd.s16 q0, q1, q0337; CHECK-NEXT: vstrb.8 q0, [r2], #16338; CHECK-NEXT: le lr, .LBB16_1339; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup340; CHECK-NEXT: pop {r7, pc}341entry:342 br label %vector.body343 344vector.body: ; preds = %vector.body, %entry345 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]346 %0 = getelementptr inbounds i16, ptr %x, i32 %index347 %wide.load = load <8 x i16>, ptr %0, align 2348 %1 = sext <8 x i16> %wide.load to <8 x i32>349 %2 = getelementptr inbounds i16, ptr %y, i32 %index350 %wide.load22 = load <8 x i16>, ptr %2, align 2351 %3 = sext <8 x i16> %wide.load22 to <8 x i32>352 %4 = sub nsw <8 x i32> %1, %3353 %5 = icmp slt <8 x i32> %4, zeroinitializer354 %6 = sub nsw <8 x i32> zeroinitializer, %4355 %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4356 %8 = trunc <8 x i32> %7 to <8 x i16>357 %9 = getelementptr inbounds i16, ptr %z, i32 %index358 store <8 x i16> %8, ptr %9, align 2359 %index.next = add i32 %index, 8360 %10 = icmp eq i32 %index.next, 1024361 br i1 %10, label %for.cond.cleanup, label %vector.body362 363for.cond.cleanup: ; preds = %vector.body364 ret void365}366 367define void @vabd_loop_s32(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {368; CHECK-LABEL: vabd_loop_s32:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}371; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}372; CHECK-NEXT: mov.w lr, #256373; CHECK-NEXT: vmov.i32 q0, #0x0374; CHECK-NEXT: .LBB17_1: @ %vector.body375; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1376; CHECK-NEXT: vldrw.u32 q1, [r0], #16377; CHECK-NEXT: vldrw.u32 q3, [r1], #16378; CHECK-NEXT: vmov.f32 s8, s6379; CHECK-NEXT: vmov.f32 s6, s5380; CHECK-NEXT: vmov r7, s4381; CHECK-NEXT: vmov.f32 s10, s7382; CHECK-NEXT: vmov r3, s8383; CHECK-NEXT: vmov.f32 s8, s14384; CHECK-NEXT: vmov.f32 s14, s15385; CHECK-NEXT: vmov r4, s8386; CHECK-NEXT: asr.w r12, r3, #31387; CHECK-NEXT: subs.w r8, r3, r4388; CHECK-NEXT: sbc.w r12, r12, r4, asr #31389; CHECK-NEXT: vmov r4, s6390; CHECK-NEXT: vmov.f32 s6, s13391; CHECK-NEXT: vmov r6, s6392; CHECK-NEXT: asrs r5, r4, #31393; CHECK-NEXT: subs.w r9, r4, r6394; CHECK-NEXT: vmov r4, s10395; CHECK-NEXT: sbc.w r5, r5, r6, asr #31396; CHECK-NEXT: vmov r6, s12397; CHECK-NEXT: asrs r5, r5, #31398; CHECK-NEXT: subs r3, r7, r6399; CHECK-NEXT: asr.w r7, r7, #31400; CHECK-NEXT: vmov q1[2], q1[0], r3, r8401; CHECK-NEXT: vmov r3, s14402; CHECK-NEXT: sbc.w r6, r7, r6, asr #31403; CHECK-NEXT: asrs r6, r6, #31404; CHECK-NEXT: subs r7, r4, r3405; CHECK-NEXT: vmov q1[3], q1[1], r9, r7406; CHECK-NEXT: mov.w r7, #0407; CHECK-NEXT: bfi r7, r6, #0, #4408; CHECK-NEXT: asr.w r6, r12, #31409; CHECK-NEXT: bfi r7, r5, #4, #4410; CHECK-NEXT: bfi r7, r6, #8, #4411; CHECK-NEXT: asr.w r6, r4, #31412; CHECK-NEXT: sbc.w r3, r6, r3, asr #31413; CHECK-NEXT: asrs r3, r3, #31414; CHECK-NEXT: bfi r7, r3, #12, #4415; CHECK-NEXT: vmsr p0, r7416; CHECK-NEXT: vpst417; CHECK-NEXT: vsubt.i32 q1, q0, q1418; CHECK-NEXT: vstrb.8 q1, [r2], #16419; CHECK-NEXT: le lr, .LBB17_1420; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup421; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}422entry:423 br label %vector.body424 425vector.body: ; preds = %vector.body, %entry426 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]427 %0 = getelementptr inbounds i32, ptr %x, i32 %index428 %wide.load = load <4 x i32>, ptr %0, align 4429 %1 = sext <4 x i32> %wide.load to <4 x i64>430 %2 = getelementptr inbounds i32, ptr %y, i32 %index431 %wide.load23 = load <4 x i32>, ptr %2, align 4432 %3 = sext <4 x i32> %wide.load23 to <4 x i64>433 %4 = sub nsw <4 x i64> %1, %3434 %5 = icmp slt <4 x i64> %4, zeroinitializer435 %6 = trunc <4 x i64> %4 to <4 x i32>436 %7 = sub <4 x i32> zeroinitializer, %6437 %8 = select <4 x i1> %5, <4 x i32> %7, <4 x i32> %6438 %9 = getelementptr inbounds i32, ptr %z, i32 %index439 store <4 x i32> %8, ptr %9, align 4440 %index.next = add i32 %index, 4441 %10 = icmp eq i32 %index.next, 1024442 br i1 %10, label %for.cond.cleanup, label %vector.body443 444for.cond.cleanup: ; preds = %vector.body445 ret void446}447 448define void @vabd_loop_u8(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {449; CHECK-LABEL: vabd_loop_u8:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: .save {r7, lr}452; CHECK-NEXT: push {r7, lr}453; CHECK-NEXT: mov.w lr, #64454; CHECK-NEXT: .LBB18_1: @ %vector.body455; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1456; CHECK-NEXT: vldrb.u8 q0, [r1], #16457; CHECK-NEXT: vldrb.u8 q1, [r0], #16458; CHECK-NEXT: vabd.u8 q0, q1, q0459; CHECK-NEXT: vstrb.8 q0, [r2], #16460; CHECK-NEXT: le lr, .LBB18_1461; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup462; CHECK-NEXT: pop {r7, pc}463entry:464 br label %vector.body465 466vector.body: ; preds = %vector.body, %entry467 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]468 %0 = getelementptr inbounds i8, ptr %x, i32 %index469 %wide.load = load <16 x i8>, ptr %0, align 1470 %1 = zext <16 x i8> %wide.load to <16 x i32>471 %2 = getelementptr inbounds i8, ptr %y, i32 %index472 %wide.load22 = load <16 x i8>, ptr %2, align 1473 %3 = zext <16 x i8> %wide.load22 to <16 x i32>474 %4 = sub nsw <16 x i32> %1, %3475 %5 = icmp slt <16 x i32> %4, zeroinitializer476 %6 = sub nsw <16 x i32> zeroinitializer, %4477 %7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %4478 %8 = trunc <16 x i32> %7 to <16 x i8>479 %9 = getelementptr inbounds i8, ptr %z, i32 %index480 store <16 x i8> %8, ptr %9, align 1481 %index.next = add i32 %index, 16482 %10 = icmp eq i32 %index.next, 1024483 br i1 %10, label %for.cond.cleanup, label %vector.body484 485for.cond.cleanup: ; preds = %vector.body486 ret void487}488 489define void @vabd_loop_u16(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {490; CHECK-LABEL: vabd_loop_u16:491; CHECK: @ %bb.0: @ %entry492; CHECK-NEXT: .save {r7, lr}493; CHECK-NEXT: push {r7, lr}494; CHECK-NEXT: mov.w lr, #128495; CHECK-NEXT: .LBB19_1: @ %vector.body496; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1497; CHECK-NEXT: vldrh.u16 q0, [r1], #16498; CHECK-NEXT: vldrh.u16 q1, [r0], #16499; CHECK-NEXT: vabd.u16 q0, q1, q0500; CHECK-NEXT: vstrb.8 q0, [r2], #16501; CHECK-NEXT: le lr, .LBB19_1502; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup503; CHECK-NEXT: pop {r7, pc}504entry:505 br label %vector.body506 507vector.body: ; preds = %vector.body, %entry508 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]509 %0 = getelementptr inbounds i16, ptr %x, i32 %index510 %wide.load = load <8 x i16>, ptr %0, align 2511 %1 = zext <8 x i16> %wide.load to <8 x i32>512 %2 = getelementptr inbounds i16, ptr %y, i32 %index513 %wide.load22 = load <8 x i16>, ptr %2, align 2514 %3 = zext <8 x i16> %wide.load22 to <8 x i32>515 %4 = sub nsw <8 x i32> %1, %3516 %5 = icmp slt <8 x i32> %4, zeroinitializer517 %6 = sub nsw <8 x i32> zeroinitializer, %4518 %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4519 %8 = trunc <8 x i32> %7 to <8 x i16>520 %9 = getelementptr inbounds i16, ptr %z, i32 %index521 store <8 x i16> %8, ptr %9, align 2522 %index.next = add i32 %index, 8523 %10 = icmp eq i32 %index.next, 1024524 br i1 %10, label %for.cond.cleanup, label %vector.body525 526for.cond.cleanup: ; preds = %vector.body527 ret void528}529 530define void @vabd_loop_u32(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {531; CHECK-LABEL: vabd_loop_u32:532; CHECK: @ %bb.0: @ %entry533; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}534; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}535; CHECK-NEXT: .vsave {d8, d9, d10, d11}536; CHECK-NEXT: vpush {d8, d9, d10, d11}537; CHECK-NEXT: mov.w lr, #256538; CHECK-NEXT: vmov.i64 q0, #0xffffffff539; CHECK-NEXT: vmov.i32 q1, #0x0540; CHECK-NEXT: .LBB20_1: @ %vector.body541; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1542; CHECK-NEXT: vldrw.u32 q4, [r1], #16543; CHECK-NEXT: vldrw.u32 q5, [r0], #16544; CHECK-NEXT: vmov.f32 s8, s18545; CHECK-NEXT: vmov.f32 s10, s19546; CHECK-NEXT: vmov.f32 s12, s22547; CHECK-NEXT: vand q2, q2, q0548; CHECK-NEXT: vmov.f32 s14, s23549; CHECK-NEXT: vand q3, q3, q0550; CHECK-NEXT: vmov r3, r12, d4551; CHECK-NEXT: vmov r4, r5, d6552; CHECK-NEXT: vmov.f32 s18, s17553; CHECK-NEXT: vmov.f32 s22, s21554; CHECK-NEXT: vand q4, q4, q0555; CHECK-NEXT: vand q5, q5, q0556; CHECK-NEXT: vmov r6, r7, d11557; CHECK-NEXT: subs.w r8, r4, r3558; CHECK-NEXT: sbc.w r12, r5, r12559; CHECK-NEXT: vmov r5, r3, d9560; CHECK-NEXT: subs.w r10, r6, r5561; CHECK-NEXT: sbc.w r9, r7, r3562; CHECK-NEXT: vmov r6, r7, d8563; CHECK-NEXT: vmov r4, r3, d10564; CHECK-NEXT: subs r4, r4, r6565; CHECK-NEXT: sbcs r3, r7566; CHECK-NEXT: vmov q4[2], q4[0], r4, r8567; CHECK-NEXT: vmov r4, r6, d5568; CHECK-NEXT: vmov r7, r5, d7569; CHECK-NEXT: asrs r3, r3, #31570; CHECK-NEXT: subs r4, r7, r4571; CHECK-NEXT: vmov q4[3], q4[1], r10, r4572; CHECK-NEXT: mov.w r4, #0573; CHECK-NEXT: bfi r4, r3, #0, #4574; CHECK-NEXT: asr.w r3, r9, #31575; CHECK-NEXT: bfi r4, r3, #4, #4576; CHECK-NEXT: asr.w r3, r12, #31577; CHECK-NEXT: bfi r4, r3, #8, #4578; CHECK-NEXT: sbc.w r3, r5, r6579; CHECK-NEXT: asrs r3, r3, #31580; CHECK-NEXT: bfi r4, r3, #12, #4581; CHECK-NEXT: vmsr p0, r4582; CHECK-NEXT: vpst583; CHECK-NEXT: vsubt.i32 q4, q1, q4584; CHECK-NEXT: vstrb.8 q4, [r2], #16585; CHECK-NEXT: le lr, .LBB20_1586; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup587; CHECK-NEXT: vpop {d8, d9, d10, d11}588; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}589entry:590 br label %vector.body591 592vector.body: ; preds = %vector.body, %entry593 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]594 %0 = getelementptr inbounds i32, ptr %x, i32 %index595 %wide.load = load <4 x i32>, ptr %0, align 4596 %1 = zext <4 x i32> %wide.load to <4 x i64>597 %2 = getelementptr inbounds i32, ptr %y, i32 %index598 %wide.load23 = load <4 x i32>, ptr %2, align 4599 %3 = zext <4 x i32> %wide.load23 to <4 x i64>600 %4 = sub nsw <4 x i64> %1, %3601 %5 = icmp slt <4 x i64> %4, zeroinitializer602 %6 = trunc <4 x i64> %4 to <4 x i32>603 %7 = sub <4 x i32> zeroinitializer, %6604 %8 = select <4 x i1> %5, <4 x i32> %7, <4 x i32> %6605 %9 = getelementptr inbounds i32, ptr %z, i32 %index606 store <4 x i32> %8, ptr %9, align 4607 %index.next = add i32 %index, 4608 %10 = icmp eq i32 %index.next, 1024609 br i1 %10, label %for.cond.cleanup, label %vector.body610 611for.cond.cleanup: ; preds = %vector.body612 ret void613}614 615define arm_aapcs_vfpcc <4 x i32> @vabd_v4u32_commutative(<4 x i32> %src1, <4 x i32> %src2) {616; CHECK-LABEL: vabd_v4u32_commutative:617; CHECK: @ %bb.0:618; CHECK-NEXT: vabd.u32 q0, q1, q0619; CHECK-NEXT: vadd.i32 q0, q0, q0620; CHECK-NEXT: bx lr621 %azextsrc1 = zext <4 x i32> %src1 to <4 x i64>622 %azextsrc2 = zext <4 x i32> %src2 to <4 x i64>623 %aadd1 = sub <4 x i64> %azextsrc1, %azextsrc2624 %aadd2 = sub <4 x i64> zeroinitializer, %aadd1625 %ac = icmp sge <4 x i64> %aadd1, zeroinitializer626 %as = select <4 x i1> %ac, <4 x i64> %aadd1, <4 x i64> %aadd2627 %aresult = trunc <4 x i64> %as to <4 x i32>628 %bzextsrc1 = zext <4 x i32> %src2 to <4 x i64>629 %bzextsrc2 = zext <4 x i32> %src1 to <4 x i64>630 %badd1 = sub <4 x i64> %bzextsrc1, %bzextsrc2631 %badd2 = sub <4 x i64> zeroinitializer, %badd1632 %bc = icmp sge <4 x i64> %badd1, zeroinitializer633 %bs = select <4 x i1> %bc, <4 x i64> %badd1, <4 x i64> %badd2634 %bresult = trunc <4 x i64> %bs to <4 x i32>635 %r = add <4 x i32> %aresult, %bresult636 ret <4 x i32> %r637}638 639define arm_aapcs_vfpcc <4 x i32> @vabd_v4u32_shuffle(<4 x i32> %src1, <4 x i32> %src2) {640; CHECK-LABEL: vabd_v4u32_shuffle:641; CHECK: @ %bb.0:642; CHECK-NEXT: vabd.u32 q1, q0, q1643; CHECK-NEXT: vmov.f32 s0, s7644; CHECK-NEXT: vmov.f32 s1, s6645; CHECK-NEXT: vmov.f32 s2, s5646; CHECK-NEXT: vmov.f32 s3, s4647; CHECK-NEXT: bx lr648 %s1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>649 %s2 = shufflevector <4 x i32> %src2, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>650 %azextsrc1 = zext <4 x i32> %s1 to <4 x i64>651 %azextsrc2 = zext <4 x i32> %s2 to <4 x i64>652 %aadd1 = sub <4 x i64> %azextsrc1, %azextsrc2653 %aadd2 = sub <4 x i64> zeroinitializer, %aadd1654 %ac = icmp sge <4 x i64> %aadd1, zeroinitializer655 %as = select <4 x i1> %ac, <4 x i64> %aadd1, <4 x i64> %aadd2656 %aresult = trunc <4 x i64> %as to <4 x i32>657 ret <4 x i32> %aresult658}659 660 661define arm_aapcs_vfpcc i16 @vabds_reduce_v16i8(<16 x i8> %s0, <16 x i8> %s1) {662; CHECK-LABEL: vabds_reduce_v16i8:663; CHECK: @ %bb.0: @ %entry664; CHECK-NEXT: vabd.s8 q0, q0, q1665; CHECK-NEXT: vaddv.u8 r0, q0666; CHECK-NEXT: bx lr667entry:668 %sextsrc1 = sext <16 x i8> %s0 to <16 x i16>669 %sextsrc2 = sext <16 x i8> %s1 to <16 x i16>670 %add1 = sub <16 x i16> %sextsrc1, %sextsrc2671 %add2 = sub <16 x i16> zeroinitializer, %add1672 %c = icmp sge <16 x i16> %add1, zeroinitializer673 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2674 %result = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)675 ret i16 %result676}677 678define arm_aapcs_vfpcc i16 @vabdu_reduce_v16i8(<16 x i8> %s0, <16 x i8> %s1) {679; CHECK-LABEL: vabdu_reduce_v16i8:680; CHECK: @ %bb.0: @ %entry681; CHECK-NEXT: vabd.u8 q0, q0, q1682; CHECK-NEXT: vaddv.u8 r0, q0683; CHECK-NEXT: bx lr684entry:685 %sextsrc1 = zext <16 x i8> %s0 to <16 x i16>686 %sextsrc2 = zext <16 x i8> %s1 to <16 x i16>687 %add1 = sub <16 x i16> %sextsrc1, %sextsrc2688 %add2 = sub <16 x i16> zeroinitializer, %add1689 %c = icmp sge <16 x i16> %add1, zeroinitializer690 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2691 %result = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)692 ret i16 %result693}694 695declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)696