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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple thumbv8.1m.main-arm-none-eabihf -mattr=+mve | FileCheck %s3 4declare void @use_int32x4_t(<4 x i32>)5 6; A 256-bit addition, with the two halves of the result passed to function7; calls to spill the carry bit out of FPSCR.8define void @add_256(<4 x i32> %a_low, <4 x i32> %a_high, <4 x i32> %b_low, <4 x i32> %b_high) {9; CHECK-LABEL: add_256:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: .save {r7, lr}12; CHECK-NEXT: push {r7, lr}13; CHECK-NEXT: .vsave {d8, d9, d10, d11}14; CHECK-NEXT: vpush {d8, d9, d10, d11}15; CHECK-NEXT: .pad #816; CHECK-NEXT: sub sp, #817; CHECK-NEXT: vadci.i32 q0, q0, q218; CHECK-NEXT: vmov q4, q319; CHECK-NEXT: vmov q5, q120; CHECK-NEXT: vstr fpscr_nzcvqc, [sp, #4] @ 4-byte Spill21; CHECK-NEXT: bl use_int32x4_t22; CHECK-NEXT: vldr fpscr_nzcvqc, [sp, #4] @ 4-byte Reload23; CHECK-NEXT: vadc.i32 q0, q5, q424; CHECK-NEXT: add sp, #825; CHECK-NEXT: vpop {d8, d9, d10, d11}26; CHECK-NEXT: pop.w {r7, lr}27; CHECK-NEXT: b use_int32x4_t28entry:29 %adc_low = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a_low, <4 x i32> %b_low, i32 0)30 %carry = extractvalue { <4 x i32>, i32 } %adc_low, 131 %result_low = extractvalue { <4 x i32>, i32 } %adc_low, 032 tail call void @use_int32x4_t(<4 x i32> %result_low)33 %adc_high = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a_high, <4 x i32> %b_high, i32 %carry)34 %result_high = extractvalue { <4 x i32>, i32 } %adc_high, 035 tail call void @use_int32x4_t(<4 x i32> %result_high)36 ret void37}38 39; A 256-bit subtraction, with the two halves of the result passed to function40; calls to spill the carry bit out of FPSCR.41define void @sub_256(<4 x i32> %a_low, <4 x i32> %a_high, <4 x i32> %b_low, <4 x i32> %b_high) {42; CHECK-LABEL: sub_256:43; CHECK: @ %bb.0: @ %entry44; CHECK-NEXT: .save {r7, lr}45; CHECK-NEXT: push {r7, lr}46; CHECK-NEXT: .vsave {d8, d9, d10, d11}47; CHECK-NEXT: vpush {d8, d9, d10, d11}48; CHECK-NEXT: .pad #849; CHECK-NEXT: sub sp, #850; CHECK-NEXT: vsbci.i32 q0, q0, q251; CHECK-NEXT: vmov q4, q352; CHECK-NEXT: vmov q5, q153; CHECK-NEXT: vstr fpscr_nzcvqc, [sp, #4] @ 4-byte Spill54; CHECK-NEXT: bl use_int32x4_t55; CHECK-NEXT: vldr fpscr_nzcvqc, [sp, #4] @ 4-byte Reload56; CHECK-NEXT: vsbc.i32 q0, q5, q457; CHECK-NEXT: add sp, #858; CHECK-NEXT: vpop {d8, d9, d10, d11}59; CHECK-NEXT: pop.w {r7, lr}60; CHECK-NEXT: b use_int32x4_t61entry:62 %adc_low = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a_low, <4 x i32> %b_low, i32 536870912)63 %carry = extractvalue { <4 x i32>, i32 } %adc_low, 164 %result_low = extractvalue { <4 x i32>, i32 } %adc_low, 065 tail call void @use_int32x4_t(<4 x i32> %result_low)66 %adc_high = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a_high, <4 x i32> %b_high, i32 %carry)67 %result_high = extractvalue { <4 x i32>, i32 } %adc_high, 068 tail call void @use_int32x4_t(<4 x i32> %result_high)69 ret void70}71 72; The carry-out of the first VADC intrinsic call is used by two other VADCs,73; both of which will modify FPSCR, so it must be spilled and reloaded.74; Missed optimisation: the first VLDR isn't needed, because the carry bit is75; already in FPSCR.76define <4 x i32> @multiple_uses_of_carry_bit(<4 x i32> %a_low, <4 x i32> %a_high, <4 x i32> %b_low, <4 x i32> %b_high, <4 x i32> %a_high_2, <4 x i32> %b_high_2) {77; CHECK-LABEL: multiple_uses_of_carry_bit:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: .pad #880; CHECK-NEXT: sub sp, #881; CHECK-NEXT: vadci.i32 q0, q0, q282; CHECK-NEXT: add r0, sp, #2483; CHECK-NEXT: vstr fpscr_nzcvqc, [sp, #4] @ 4-byte Spill84; CHECK-NEXT: vldr fpscr_nzcvqc, [sp, #4] @ 4-byte Reload85; CHECK-NEXT: vadc.i32 q1, q1, q386; CHECK-NEXT: veor q0, q0, q187; CHECK-NEXT: vldrw.u32 q1, [r0]88; CHECK-NEXT: add r0, sp, #889; CHECK-NEXT: vldr fpscr_nzcvqc, [sp, #4] @ 4-byte Reload90; CHECK-NEXT: vldrw.u32 q2, [r0]91; CHECK-NEXT: vadc.i32 q1, q2, q192; CHECK-NEXT: veor q0, q0, q193; CHECK-NEXT: add sp, #894; CHECK-NEXT: bx lr95entry:96 %adc_low = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a_low, <4 x i32> %b_low, i32 0)97 %carry = extractvalue { <4 x i32>, i32 } %adc_low, 198 %result_low = extractvalue { <4 x i32>, i32 } %adc_low, 099 %adc_high = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a_high, <4 x i32> %b_high, i32 %carry)100 %result_high = extractvalue { <4 x i32>, i32 } %adc_high, 0101 %checksum_1 = xor <4 x i32> %result_low, %result_high102 %adc_high_2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a_high_2, <4 x i32> %b_high_2, i32 %carry)103 %result_high_2 = extractvalue { <4 x i32>, i32 } %adc_high_2, 0104 %checksum_2 = xor <4 x i32> %checksum_1, %result_high_2105 ret <4 x i32> %checksum_2106}107