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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: vaddqr_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vadd.i32 q0, q0, r08; CHECK-NEXT: bx lr9entry:10 %i = insertelement <4 x i32> undef, i32 %src2, i32 011 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer12 %c = add <4 x i32> %src, %sp13 ret <4 x i32> %c14}15 16define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {17; CHECK-LABEL: vaddqr_v8i16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vadd.i16 q0, q0, r020; CHECK-NEXT: bx lr21entry:22 %i = insertelement <8 x i16> undef, i16 %src2, i32 023 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer24 %c = add <8 x i16> %src, %sp25 ret <8 x i16> %c26}27 28define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {29; CHECK-LABEL: vaddqr_v16i8:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vadd.i8 q0, q0, r032; CHECK-NEXT: bx lr33entry:34 %i = insertelement <16 x i8> undef, i8 %src2, i32 035 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer36 %c = add <16 x i8> %src, %sp37 ret <16 x i8> %c38}39 40define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {41; CHECK-LABEL: vaddqr_v4i32_2:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vadd.i32 q0, q0, r044; CHECK-NEXT: bx lr45entry:46 %i = insertelement <4 x i32> undef, i32 %src2, i32 047 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer48 %c = add <4 x i32> %sp, %src49 ret <4 x i32> %c50}51 52define arm_aapcs_vfpcc <8 x i16> @vaddqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {53; CHECK-LABEL: vaddqr_v8i16_2:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vadd.i16 q0, q0, r056; CHECK-NEXT: bx lr57entry:58 %i = insertelement <8 x i16> undef, i16 %src2, i32 059 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer60 %c = add <8 x i16> %sp, %src61 ret <8 x i16> %c62}63 64define arm_aapcs_vfpcc <16 x i8> @vaddqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {65; CHECK-LABEL: vaddqr_v16i8_2:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vadd.i8 q0, q0, r068; CHECK-NEXT: bx lr69entry:70 %i = insertelement <16 x i8> undef, i8 %src2, i32 071 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer72 %c = add <16 x i8> %sp, %src73 ret <16 x i8> %c74}75 76define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {77; CHECK-LABEL: vaddqr_v4f32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmov r0, s480; CHECK-NEXT: vadd.f32 q0, q0, r081; CHECK-NEXT: bx lr82entry:83 %i = insertelement <4 x float> undef, float %src2, i32 084 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer85 %c = fadd <4 x float> %src, %sp86 ret <4 x float> %c87}88 89define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {90; CHECK-LABEL: vaddqr_v8f16:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmov.f16 r0, s493; CHECK-NEXT: vadd.f16 q0, q0, r094; CHECK-NEXT: bx lr95entry:96 %i = insertelement <8 x half> undef, half %src2, i32 097 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer98 %c = fadd <8 x half> %src, %sp99 ret <8 x half> %c100}101 102define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_2(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {103; CHECK-LABEL: vaddqr_v4f32_2:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmov r0, s4106; CHECK-NEXT: vadd.f32 q0, q0, r0107; CHECK-NEXT: bx lr108entry:109 %i = insertelement <4 x float> undef, float %src2, i32 0110 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer111 %c = fadd <4 x float> %sp, %src112 ret <4 x float> %c113}114 115define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_2(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {116; CHECK-LABEL: vaddqr_v8f16_2:117; CHECK: @ %bb.0: @ %entry118; CHECK-NEXT: vmov.f16 r0, s4119; CHECK-NEXT: vadd.f16 q0, q0, r0120; CHECK-NEXT: bx lr121entry:122 %i = insertelement <8 x half> undef, half %src2, i32 0123 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer124 %c = fadd <8 x half> %sp, %src125 ret <8 x half> %c126}127 128define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_3(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {129; CHECK-LABEL: vaddqr_v4f32_3:130; CHECK: @ %bb.0: @ %entry131; CHECK-NEXT: vmov r0, s4132; CHECK-NEXT: vadd.f32 q0, q0, r0133; CHECK-NEXT: bx lr134entry:135 %src2bc = bitcast float %src2 to i32136 %i = insertelement <4 x i32> undef, i32 %src2bc, i32 0137 %spbc = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer138 %sp = bitcast <4 x i32> %spbc to <4 x float>139 %c = fadd <4 x float> %src, %sp140 ret <4 x float> %c141}142 143define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_3(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {144; CHECK-LABEL: vaddqr_v8f16_3:145; CHECK: @ %bb.0: @ %entry146; CHECK-NEXT: vmov.f16 r0, s4147; CHECK-NEXT: vadd.f16 q0, q0, r0148; CHECK-NEXT: bx lr149entry:150 %src2bc = bitcast half %src2 to i16151 %i = insertelement <8 x i16> undef, i16 %src2bc, i32 0152 %spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer153 %sp = bitcast <8 x i16> %spbc to <8 x half>154 %c = fadd <8 x half> %src, %sp155 ret <8 x half> %c156}157 158define arm_aapcs_vfpcc <4 x float> @vaddqr_v4f32_4(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {159; CHECK-LABEL: vaddqr_v4f32_4:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: vmov r0, s4162; CHECK-NEXT: vadd.f32 q0, q0, r0163; CHECK-NEXT: bx lr164entry:165 %src2bc = bitcast float %src2 to i32166 %i = insertelement <4 x i32> undef, i32 %src2bc, i32 0167 %spbc = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer168 %sp = bitcast <4 x i32> %spbc to <4 x float>169 %c = fadd <4 x float> %sp, %src170 ret <4 x float> %c171}172 173define arm_aapcs_vfpcc <8 x half> @vaddqr_v8f16_4(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {174; CHECK-LABEL: vaddqr_v8f16_4:175; CHECK: @ %bb.0: @ %entry176; CHECK-NEXT: vmov.f16 r0, s4177; CHECK-NEXT: vadd.f16 q0, q0, r0178; CHECK-NEXT: bx lr179entry:180 %src2bc = bitcast half %src2 to i16181 %i = insertelement <8 x i16> undef, i16 %src2bc, i32 0182 %spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer183 %sp = bitcast <8 x i16> %spbc to <8 x half>184 %c = fadd <8 x half> %sp, %src185 ret <8 x half> %c186}187