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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4declare i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64>)5declare i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32>)6declare i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32>)7declare i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16>)8declare i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16>)9declare i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8>)10declare i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8>)11 12define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {13; CHECK-LABEL: vaddv_v2i64_i64:14; CHECK: @ %bb.0: @ %entry15; CHECK-NEXT: vmov r0, r1, d116; CHECK-NEXT: vmov r2, r3, d017; CHECK-NEXT: adds r0, r0, r218; CHECK-NEXT: adcs r1, r319; CHECK-NEXT: bx lr20entry:21 %r = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)22 ret i64 %r23}24 25define arm_aapcs_vfpcc i32 @vaddv_v4i32_i32(<4 x i32> %s1) {26; CHECK-LABEL: vaddv_v4i32_i32:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: vaddv.u32 r0, q029; CHECK-NEXT: bx lr30entry:31 %r = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)32 ret i32 %r33}34 35define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {36; CHECK-LABEL: vaddv_v8i32_i32:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: vaddv.u32 r0, q139; CHECK-NEXT: vaddva.u32 r0, q040; CHECK-NEXT: bx lr41entry:42 %r = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)43 ret i32 %r44}45 46define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {47; CHECK-LABEL: vaddv_v8i16_i16:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vaddv.u16 r0, q050; CHECK-NEXT: bx lr51entry:52 %r = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)53 ret i16 %r54}55 56define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {57; CHECK-LABEL: vaddv_v16i16_i16:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vaddv.u16 r0, q160; CHECK-NEXT: vaddva.u16 r0, q061; CHECK-NEXT: bx lr62entry:63 %r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)64 ret i16 %r65}66 67define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {68; CHECK-LABEL: vaddv_v16i8_i8:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: vaddv.u8 r0, q071; CHECK-NEXT: bx lr72entry:73 %r = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)74 ret i8 %r75}76 77define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {78; CHECK-LABEL: vaddv_v32i8_i8:79; CHECK: @ %bb.0: @ %entry80; CHECK-NEXT: vaddv.u8 r0, q181; CHECK-NEXT: vaddva.u8 r0, q082; CHECK-NEXT: bx lr83entry:84 %r = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)85 ret i8 %r86}87 88define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {89; CHECK-LABEL: vaddva_v2i64_i64:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: .save {r7, lr}92; CHECK-NEXT: push {r7, lr}93; CHECK-NEXT: vmov lr, r12, d194; CHECK-NEXT: vmov r3, r2, d095; CHECK-NEXT: adds.w r3, r3, lr96; CHECK-NEXT: adc.w r2, r2, r1297; CHECK-NEXT: adds r0, r0, r398; CHECK-NEXT: adcs r1, r299; CHECK-NEXT: pop {r7, pc}100entry:101 %t = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)102 %r = add i64 %t, %x103 ret i64 %r104}105 106define arm_aapcs_vfpcc i32 @vaddva_v4i32_i32(<4 x i32> %s1, i32 %x) {107; CHECK-LABEL: vaddva_v4i32_i32:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vaddva.u32 r0, q0110; CHECK-NEXT: bx lr111entry:112 %t = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)113 %r = add i32 %t, %x114 ret i32 %r115}116 117define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {118; CHECK-LABEL: vaddva_v8i32_i32:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vaddva.u32 r0, q0121; CHECK-NEXT: vaddva.u32 r0, q1122; CHECK-NEXT: bx lr123entry:124 %t = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)125 %r = add i32 %t, %x126 ret i32 %r127}128 129define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {130; CHECK-LABEL: vaddva_v8i16_i16:131; CHECK: @ %bb.0: @ %entry132; CHECK-NEXT: vaddva.u16 r0, q0133; CHECK-NEXT: bx lr134entry:135 %t = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)136 %r = add i16 %t, %x137 ret i16 %r138}139 140define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {141; CHECK-LABEL: vaddva_v16i16_i16:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vaddva.u16 r0, q0144; CHECK-NEXT: vaddva.u16 r0, q1145; CHECK-NEXT: bx lr146entry:147 %t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)148 %r = add i16 %t, %x149 ret i16 %r150}151 152define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {153; CHECK-LABEL: vaddva_v16i8_i8:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vaddva.u8 r0, q0156; CHECK-NEXT: bx lr157entry:158 %t = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)159 %r = add i8 %t, %x160 ret i8 %r161}162 163define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {164; CHECK-LABEL: vaddva_v32i8_i8:165; CHECK: @ %bb.0: @ %entry166; CHECK-NEXT: vaddva.u8 r0, q0167; CHECK-NEXT: vaddva.u8 r0, q1168; CHECK-NEXT: bx lr169entry:170 %t = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)171 %r = add i8 %t, %x172 ret i8 %r173}174