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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>)5declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>)6declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>)7declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>)8 9 10define arm_aapcs_vfpcc <4 x float> @reassoc_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {11; CHECK-LABEL: reassoc_f32x4:12; CHECK: @ %bb.0: @ %entry13; CHECK-NEXT: vcmla.f32 q0, q1, q2, #014; CHECK-NEXT: bx lr15entry:16 %d = tail call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> zeroinitializer, <4 x float> %b, <4 x float> %c)17 %res = fadd fast <4 x float> %d, %a18 ret <4 x float> %res19}20 21define arm_aapcs_vfpcc <4 x float> @reassoc_c_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {22; CHECK-LABEL: reassoc_c_f32x4:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vcmla.f32 q0, q1, q2, #9025; CHECK-NEXT: bx lr26entry:27 %d = tail call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> zeroinitializer, <4 x float> %b, <4 x float> %c)28 %res = fadd fast <4 x float> %a, %d29 ret <4 x float> %res30}31 32define arm_aapcs_vfpcc <8 x half> @reassoc_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {33; CHECK-LABEL: reassoc_f16x4:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vcmla.f16 q0, q1, q2, #18036; CHECK-NEXT: bx lr37entry:38 %d = tail call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> zeroinitializer, <8 x half> %b, <8 x half> %c)39 %res = fadd fast <8 x half> %d, %a40 ret <8 x half> %res41}42 43define arm_aapcs_vfpcc <8 x half> @reassoc_c_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {44; CHECK-LABEL: reassoc_c_f16x4:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vcmla.f16 q0, q1, q2, #27047; CHECK-NEXT: bx lr48entry:49 %d = tail call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> zeroinitializer, <8 x half> %b, <8 x half> %c)50 %res = fadd fast <8 x half> %a, %d51 ret <8 x half> %res52}53 54define arm_aapcs_vfpcc <4 x float> @reassoc_nonfast_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {55; CHECK-LABEL: reassoc_nonfast_f32x4:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vmov.i32 q3, #0x058; CHECK-NEXT: vcmla.f32 q3, q1, q2, #059; CHECK-NEXT: vadd.f32 q0, q3, q060; CHECK-NEXT: bx lr61entry:62 %d = tail call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> zeroinitializer, <4 x float> %b, <4 x float> %c)63 %res = fadd <4 x float> %d, %a64 ret <4 x float> %res65}66 67 68 69define arm_aapcs_vfpcc <4 x float> @muladd_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {70; CHECK-LABEL: muladd_f32x4:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vcmla.f32 q0, q1, q2, #073; CHECK-NEXT: bx lr74entry:75 %d = tail call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %b, <4 x float> %c)76 %res = fadd fast <4 x float> %d, %a77 ret <4 x float> %res78}79 80define arm_aapcs_vfpcc <4 x float> @muladd_c_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {81; CHECK-LABEL: muladd_c_f32x4:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vcmla.f32 q0, q1, q2, #9084; CHECK-NEXT: bx lr85entry:86 %d = tail call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %b, <4 x float> %c)87 %res = fadd fast <4 x float> %a, %d88 ret <4 x float> %res89}90 91define arm_aapcs_vfpcc <8 x half> @muladd_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {92; CHECK-LABEL: muladd_f16x4:93; CHECK: @ %bb.0: @ %entry94; CHECK-NEXT: vcmla.f16 q0, q1, q2, #18095; CHECK-NEXT: bx lr96entry:97 %d = tail call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %b, <8 x half> %c)98 %res = fadd fast <8 x half> %d, %a99 ret <8 x half> %res100}101 102define arm_aapcs_vfpcc <8 x half> @muladd_c_f16x4(<8 x half> %a, <8 x half> %b, <8 x half> %c) {103; CHECK-LABEL: muladd_c_f16x4:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vcmla.f16 q0, q1, q2, #270106; CHECK-NEXT: bx lr107entry:108 %d = tail call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %b, <8 x half> %c)109 %res = fadd fast <8 x half> %a, %d110 ret <8 x half> %res111}112 113define arm_aapcs_vfpcc <4 x float> @muladd_nonfast_f32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {114; CHECK-LABEL: muladd_nonfast_f32x4:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vcmul.f32 q3, q1, q2, #0117; CHECK-NEXT: vadd.f32 q0, q3, q0118; CHECK-NEXT: bx lr119entry:120 %d = tail call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %b, <4 x float> %c)121 %res = fadd <4 x float> %d, %a122 ret <4 x float> %res123}124 125define arm_aapcs_vfpcc <8 x half> @same_register_f16(<8 x half> %a) {126; CHECK-LABEL: same_register_f16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vcmla.f16 q0, q0, q0, #0129; CHECK-NEXT: bx lr130entry:131 %d = tail call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> zeroinitializer, <8 x half> %a, <8 x half> %a)132 %res = fadd fast <8 x half> %d, %a133 ret <8 x half> %res134}135 136define arm_aapcs_vfpcc <4 x float> @same_register_f32(<4 x float> %a) {137; CHECK-LABEL: same_register_f32:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmov q1, q0140; CHECK-NEXT: vcmla.f32 q1, q0, q0, #0141; CHECK-NEXT: vmov q0, q1142; CHECK-NEXT: bx lr143entry:144 %d = tail call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> zeroinitializer, <4 x float> %a, <4 x float> %a)145 %res = fadd fast <4 x float> %d, %a146 ret <4 x float> %res147}148