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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: vcmp_eq_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i32 eq, q0, q18; CHECK-NEXT: vpsel q0, q2, q39; CHECK-NEXT: bx lr10entry:11 %c = icmp eq <4 x i32> %src, %srcb12 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b13 ret <4 x i32> %s14}15 16define arm_aapcs_vfpcc <4 x i32> @vcmp_ne_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {17; CHECK-LABEL: vcmp_ne_v4i32:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vcmp.i32 ne, q0, q120; CHECK-NEXT: vpsel q0, q2, q321; CHECK-NEXT: bx lr22entry:23 %c = icmp ne <4 x i32> %src, %srcb24 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b25 ret <4 x i32> %s26}27 28define arm_aapcs_vfpcc <4 x i32> @vcmp_sgt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {29; CHECK-LABEL: vcmp_sgt_v4i32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vcmp.s32 gt, q0, q132; CHECK-NEXT: vpsel q0, q2, q333; CHECK-NEXT: bx lr34entry:35 %c = icmp sgt <4 x i32> %src, %srcb36 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b37 ret <4 x i32> %s38}39 40define arm_aapcs_vfpcc <4 x i32> @vcmp_sge_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {41; CHECK-LABEL: vcmp_sge_v4i32:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vcmp.s32 ge, q0, q144; CHECK-NEXT: vpsel q0, q2, q345; CHECK-NEXT: bx lr46entry:47 %c = icmp sge <4 x i32> %src, %srcb48 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b49 ret <4 x i32> %s50}51 52define arm_aapcs_vfpcc <4 x i32> @vcmp_slt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {53; CHECK-LABEL: vcmp_slt_v4i32:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vcmp.s32 gt, q1, q056; CHECK-NEXT: vpsel q0, q2, q357; CHECK-NEXT: bx lr58entry:59 %c = icmp slt <4 x i32> %src, %srcb60 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b61 ret <4 x i32> %s62}63 64define arm_aapcs_vfpcc <4 x i32> @vcmp_sle_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {65; CHECK-LABEL: vcmp_sle_v4i32:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vcmp.s32 ge, q1, q068; CHECK-NEXT: vpsel q0, q2, q369; CHECK-NEXT: bx lr70entry:71 %c = icmp sle <4 x i32> %src, %srcb72 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b73 ret <4 x i32> %s74}75 76define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {77; CHECK-LABEL: vcmp_ugt_v4i32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vcmp.u32 hi, q0, q180; CHECK-NEXT: vpsel q0, q2, q381; CHECK-NEXT: bx lr82entry:83 %c = icmp ugt <4 x i32> %src, %srcb84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b85 ret <4 x i32> %s86}87 88define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {89; CHECK-LABEL: vcmp_uge_v4i32:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vcmp.u32 cs, q0, q192; CHECK-NEXT: vpsel q0, q2, q393; CHECK-NEXT: bx lr94entry:95 %c = icmp uge <4 x i32> %src, %srcb96 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b97 ret <4 x i32> %s98}99 100define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {101; CHECK-LABEL: vcmp_ult_v4i32:102; CHECK: @ %bb.0: @ %entry103; CHECK-NEXT: vcmp.u32 hi, q1, q0104; CHECK-NEXT: vpsel q0, q2, q3105; CHECK-NEXT: bx lr106entry:107 %c = icmp ult <4 x i32> %src, %srcb108 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b109 ret <4 x i32> %s110}111 112define arm_aapcs_vfpcc <4 x i32> @vcmp_ule_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {113; CHECK-LABEL: vcmp_ule_v4i32:114; CHECK: @ %bb.0: @ %entry115; CHECK-NEXT: vcmp.u32 cs, q1, q0116; CHECK-NEXT: vpsel q0, q2, q3117; CHECK-NEXT: bx lr118entry:119 %c = icmp ule <4 x i32> %src, %srcb120 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b121 ret <4 x i32> %s122}123 124 125define arm_aapcs_vfpcc <8 x i16> @vcmp_eq_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {126; CHECK-LABEL: vcmp_eq_v8i16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vcmp.i16 eq, q0, q1129; CHECK-NEXT: vpsel q0, q2, q3130; CHECK-NEXT: bx lr131entry:132 %c = icmp eq <8 x i16> %src, %srcb133 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b134 ret <8 x i16> %s135}136 137define arm_aapcs_vfpcc <8 x i16> @vcmp_ne_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {138; CHECK-LABEL: vcmp_ne_v8i16:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vcmp.i16 ne, q0, q1141; CHECK-NEXT: vpsel q0, q2, q3142; CHECK-NEXT: bx lr143entry:144 %c = icmp ne <8 x i16> %src, %srcb145 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b146 ret <8 x i16> %s147}148 149define arm_aapcs_vfpcc <8 x i16> @vcmp_sgt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {150; CHECK-LABEL: vcmp_sgt_v8i16:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vcmp.s16 gt, q0, q1153; CHECK-NEXT: vpsel q0, q2, q3154; CHECK-NEXT: bx lr155entry:156 %c = icmp sgt <8 x i16> %src, %srcb157 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b158 ret <8 x i16> %s159}160 161define arm_aapcs_vfpcc <8 x i16> @vcmp_sge_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {162; CHECK-LABEL: vcmp_sge_v8i16:163; CHECK: @ %bb.0: @ %entry164; CHECK-NEXT: vcmp.s16 ge, q0, q1165; CHECK-NEXT: vpsel q0, q2, q3166; CHECK-NEXT: bx lr167entry:168 %c = icmp sge <8 x i16> %src, %srcb169 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b170 ret <8 x i16> %s171}172 173define arm_aapcs_vfpcc <8 x i16> @vcmp_slt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {174; CHECK-LABEL: vcmp_slt_v8i16:175; CHECK: @ %bb.0: @ %entry176; CHECK-NEXT: vcmp.s16 gt, q1, q0177; CHECK-NEXT: vpsel q0, q2, q3178; CHECK-NEXT: bx lr179entry:180 %c = icmp slt <8 x i16> %src, %srcb181 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b182 ret <8 x i16> %s183}184 185define arm_aapcs_vfpcc <8 x i16> @vcmp_sle_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {186; CHECK-LABEL: vcmp_sle_v8i16:187; CHECK: @ %bb.0: @ %entry188; CHECK-NEXT: vcmp.s16 ge, q1, q0189; CHECK-NEXT: vpsel q0, q2, q3190; CHECK-NEXT: bx lr191entry:192 %c = icmp sle <8 x i16> %src, %srcb193 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b194 ret <8 x i16> %s195}196 197define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {198; CHECK-LABEL: vcmp_ugt_v8i16:199; CHECK: @ %bb.0: @ %entry200; CHECK-NEXT: vcmp.u16 hi, q0, q1201; CHECK-NEXT: vpsel q0, q2, q3202; CHECK-NEXT: bx lr203entry:204 %c = icmp ugt <8 x i16> %src, %srcb205 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b206 ret <8 x i16> %s207}208 209define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {210; CHECK-LABEL: vcmp_uge_v8i16:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: vcmp.u16 cs, q0, q1213; CHECK-NEXT: vpsel q0, q2, q3214; CHECK-NEXT: bx lr215entry:216 %c = icmp uge <8 x i16> %src, %srcb217 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b218 ret <8 x i16> %s219}220 221define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {222; CHECK-LABEL: vcmp_ult_v8i16:223; CHECK: @ %bb.0: @ %entry224; CHECK-NEXT: vcmp.u16 hi, q1, q0225; CHECK-NEXT: vpsel q0, q2, q3226; CHECK-NEXT: bx lr227entry:228 %c = icmp ult <8 x i16> %src, %srcb229 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b230 ret <8 x i16> %s231}232 233define arm_aapcs_vfpcc <8 x i16> @vcmp_ule_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {234; CHECK-LABEL: vcmp_ule_v8i16:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: vcmp.u16 cs, q1, q0237; CHECK-NEXT: vpsel q0, q2, q3238; CHECK-NEXT: bx lr239entry:240 %c = icmp ule <8 x i16> %src, %srcb241 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b242 ret <8 x i16> %s243}244 245 246define arm_aapcs_vfpcc <16 x i8> @vcmp_eq_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {247; CHECK-LABEL: vcmp_eq_v16i8:248; CHECK: @ %bb.0: @ %entry249; CHECK-NEXT: vcmp.i8 eq, q0, q1250; CHECK-NEXT: vpsel q0, q2, q3251; CHECK-NEXT: bx lr252entry:253 %c = icmp eq <16 x i8> %src, %srcb254 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b255 ret <16 x i8> %s256}257 258define arm_aapcs_vfpcc <16 x i8> @vcmp_ne_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {259; CHECK-LABEL: vcmp_ne_v16i8:260; CHECK: @ %bb.0: @ %entry261; CHECK-NEXT: vcmp.i8 ne, q0, q1262; CHECK-NEXT: vpsel q0, q2, q3263; CHECK-NEXT: bx lr264entry:265 %c = icmp ne <16 x i8> %src, %srcb266 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b267 ret <16 x i8> %s268}269 270define arm_aapcs_vfpcc <16 x i8> @vcmp_sgt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {271; CHECK-LABEL: vcmp_sgt_v16i8:272; CHECK: @ %bb.0: @ %entry273; CHECK-NEXT: vcmp.s8 gt, q0, q1274; CHECK-NEXT: vpsel q0, q2, q3275; CHECK-NEXT: bx lr276entry:277 %c = icmp sgt <16 x i8> %src, %srcb278 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b279 ret <16 x i8> %s280}281 282define arm_aapcs_vfpcc <16 x i8> @vcmp_sge_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {283; CHECK-LABEL: vcmp_sge_v16i8:284; CHECK: @ %bb.0: @ %entry285; CHECK-NEXT: vcmp.s8 ge, q0, q1286; CHECK-NEXT: vpsel q0, q2, q3287; CHECK-NEXT: bx lr288entry:289 %c = icmp sge <16 x i8> %src, %srcb290 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b291 ret <16 x i8> %s292}293 294define arm_aapcs_vfpcc <16 x i8> @vcmp_slt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {295; CHECK-LABEL: vcmp_slt_v16i8:296; CHECK: @ %bb.0: @ %entry297; CHECK-NEXT: vcmp.s8 gt, q1, q0298; CHECK-NEXT: vpsel q0, q2, q3299; CHECK-NEXT: bx lr300entry:301 %c = icmp slt <16 x i8> %src, %srcb302 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b303 ret <16 x i8> %s304}305 306define arm_aapcs_vfpcc <16 x i8> @vcmp_sle_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {307; CHECK-LABEL: vcmp_sle_v16i8:308; CHECK: @ %bb.0: @ %entry309; CHECK-NEXT: vcmp.s8 ge, q1, q0310; CHECK-NEXT: vpsel q0, q2, q3311; CHECK-NEXT: bx lr312entry:313 %c = icmp sle <16 x i8> %src, %srcb314 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b315 ret <16 x i8> %s316}317 318define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {319; CHECK-LABEL: vcmp_ugt_v16i8:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: vcmp.u8 hi, q0, q1322; CHECK-NEXT: vpsel q0, q2, q3323; CHECK-NEXT: bx lr324entry:325 %c = icmp ugt <16 x i8> %src, %srcb326 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b327 ret <16 x i8> %s328}329 330define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {331; CHECK-LABEL: vcmp_uge_v16i8:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vcmp.u8 cs, q0, q1334; CHECK-NEXT: vpsel q0, q2, q3335; CHECK-NEXT: bx lr336entry:337 %c = icmp uge <16 x i8> %src, %srcb338 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b339 ret <16 x i8> %s340}341 342define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {343; CHECK-LABEL: vcmp_ult_v16i8:344; CHECK: @ %bb.0: @ %entry345; CHECK-NEXT: vcmp.u8 hi, q1, q0346; CHECK-NEXT: vpsel q0, q2, q3347; CHECK-NEXT: bx lr348entry:349 %c = icmp ult <16 x i8> %src, %srcb350 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b351 ret <16 x i8> %s352}353 354define arm_aapcs_vfpcc <16 x i8> @vcmp_ule_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {355; CHECK-LABEL: vcmp_ule_v16i8:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vcmp.u8 cs, q1, q0358; CHECK-NEXT: vpsel q0, q2, q3359; CHECK-NEXT: bx lr360entry:361 %c = icmp ule <16 x i8> %src, %srcb362 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b363 ret <16 x i8> %s364}365 366 367define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {368; CHECK-LABEL: vcmp_eq_v2i64:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: vmov r0, r1, d2371; CHECK-NEXT: vmov r2, r3, d0372; CHECK-NEXT: eors r0, r2373; CHECK-NEXT: eors r1, r3374; CHECK-NEXT: orrs r0, r1375; CHECK-NEXT: mov.w r1, #0376; CHECK-NEXT: csetm r0, eq377; CHECK-NEXT: vmov r12, r2, d3378; CHECK-NEXT: bfi r1, r0, #0, #8379; CHECK-NEXT: vmov r3, r0, d1380; CHECK-NEXT: eors r0, r2381; CHECK-NEXT: eor.w r2, r3, r12382; CHECK-NEXT: orrs r0, r2383; CHECK-NEXT: csetm r0, eq384; CHECK-NEXT: bfi r1, r0, #8, #8385; CHECK-NEXT: vmsr p0, r1386; CHECK-NEXT: vpsel q0, q2, q3387; CHECK-NEXT: bx lr388entry:389 %c = icmp eq <2 x i64> %src, %srcb390 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b391 ret <2 x i64> %s392}393 394define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {395; CHECK-LABEL: vcmp_slt_v2i64:396; CHECK: @ %bb.0: @ %entry397; CHECK-NEXT: vmov r0, r1, d2398; CHECK-NEXT: vmov r2, r3, d0399; CHECK-NEXT: subs r0, r2, r0400; CHECK-NEXT: sbcs.w r0, r3, r1401; CHECK-NEXT: mov.w r1, #0402; CHECK-NEXT: csetm r0, lt403; CHECK-NEXT: vmov r3, r2, d1404; CHECK-NEXT: bfi r1, r0, #0, #8405; CHECK-NEXT: vmov r0, r12, d3406; CHECK-NEXT: subs r0, r3, r0407; CHECK-NEXT: sbcs.w r0, r2, r12408; CHECK-NEXT: csetm r0, lt409; CHECK-NEXT: bfi r1, r0, #8, #8410; CHECK-NEXT: vmsr p0, r1411; CHECK-NEXT: vpsel q0, q2, q3412; CHECK-NEXT: bx lr413entry:414 %c = icmp slt <2 x i64> %src, %srcb415 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b416 ret <2 x i64> %s417}418 419define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb, <2 x i32> %a, <2 x i32> %b) {420; CHECK-LABEL: vcmp_eq_v2i32:421; CHECK: @ %bb.0: @ %entry422; CHECK-NEXT: vmov r0, r1, d2423; CHECK-NEXT: vmov r2, r3, d0424; CHECK-NEXT: eors r0, r2425; CHECK-NEXT: eors r1, r3426; CHECK-NEXT: orrs r0, r1427; CHECK-NEXT: mov.w r1, #0428; CHECK-NEXT: csetm r0, eq429; CHECK-NEXT: vmov r12, r2, d3430; CHECK-NEXT: bfi r1, r0, #0, #8431; CHECK-NEXT: vmov r3, r0, d1432; CHECK-NEXT: eors r0, r2433; CHECK-NEXT: eor.w r2, r3, r12434; CHECK-NEXT: orrs r0, r2435; CHECK-NEXT: csetm r0, eq436; CHECK-NEXT: bfi r1, r0, #8, #8437; CHECK-NEXT: vmsr p0, r1438; CHECK-NEXT: vpsel q0, q2, q3439; CHECK-NEXT: bx lr440entry:441 %c = icmp eq <2 x i64> %src, %srcb442 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b443 ret <2 x i32> %s444}445 446define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {447; CHECK-LABEL: vcmp_multi_v2i32:448; CHECK: @ %bb.0:449; CHECK-NEXT: vmov r0, r1, d0450; CHECK-NEXT: movs r2, #0451; CHECK-NEXT: orrs r0, r1452; CHECK-NEXT: csetm r1, eq453; CHECK-NEXT: movs r0, #0454; CHECK-NEXT: bfi r2, r1, #0, #8455; CHECK-NEXT: vmov r1, r3, d1456; CHECK-NEXT: vmov.i32 q0, #0x0457; CHECK-NEXT: orrs r1, r3458; CHECK-NEXT: csetm r1, eq459; CHECK-NEXT: bfi r2, r1, #8, #8460; CHECK-NEXT: vmsr p0, r2461; CHECK-NEXT: vmov r2, s4462; CHECK-NEXT: vpsel q0, q0, q2463; CHECK-NEXT: vmov r1, s0464; CHECK-NEXT: cmp r2, #0465; CHECK-NEXT: cset r2, ne466; CHECK-NEXT: cmp r1, #0467; CHECK-NEXT: csel r12, zr, r2, eq468; CHECK-NEXT: vmov r2, s8469; CHECK-NEXT: asrs r3, r1, #31470; CHECK-NEXT: subs r1, r1, r2471; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31472; CHECK-NEXT: vmov r2, s6473; CHECK-NEXT: csel r1, zr, r12, ge474; CHECK-NEXT: rsbs r1, r1, #0475; CHECK-NEXT: bfi r0, r1, #0, #8476; CHECK-NEXT: vmov r1, s2477; CHECK-NEXT: cmp r2, #0478; CHECK-NEXT: cset r2, ne479; CHECK-NEXT: cmp r1, #0480; CHECK-NEXT: csel r12, zr, r2, eq481; CHECK-NEXT: vmov r2, s10482; CHECK-NEXT: asrs r3, r1, #31483; CHECK-NEXT: subs r1, r1, r2484; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31485; CHECK-NEXT: csel r1, zr, r12, ge486; CHECK-NEXT: rsbs r1, r1, #0487; CHECK-NEXT: bfi r0, r1, #8, #8488; CHECK-NEXT: vmsr p0, r0489; CHECK-NEXT: vpsel q0, q2, q0490; CHECK-NEXT: bx lr491 %a4 = icmp eq <2 x i64> %a, zeroinitializer492 %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c493 %a6 = icmp ne <2 x i32> %b, zeroinitializer494 %a7 = icmp slt <2 x i32> %a5, %c495 %a8 = icmp ne <2 x i32> %a5, zeroinitializer496 %a9 = and <2 x i1> %a6, %a8497 %a10 = and <2 x i1> %a7, %a9498 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5499 ret <2 x i32> %a11500}501