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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP4 5define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {6; CHECK-MVE-LABEL: vcmp_oeq_v4f32:7; CHECK-MVE:       @ %bb.0: @ %entry8; CHECK-MVE-NEXT:    vcmp.f32 s0, s49; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr10; CHECK-MVE-NEXT:    vcmp.f32 s3, s411; CHECK-MVE-NEXT:    cset r0, eq12; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr13; CHECK-MVE-NEXT:    vcmp.f32 s1, s414; CHECK-MVE-NEXT:    cset r1, eq15; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr16; CHECK-MVE-NEXT:    vcmp.f32 s2, s417; CHECK-MVE-NEXT:    cset r2, eq18; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr19; CHECK-MVE-NEXT:    cset r3, eq20; CHECK-MVE-NEXT:    cmp r3, #021; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s1022; CHECK-MVE-NEXT:    cmp r2, #023; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s924; CHECK-MVE-NEXT:    cmp r1, #025; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s1126; CHECK-MVE-NEXT:    cmp r0, #027; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s828; CHECK-MVE-NEXT:    bx lr29;30; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:31; CHECK-MVEFP:       @ %bb.0: @ %entry32; CHECK-MVEFP-NEXT:    vmov r0, s433; CHECK-MVEFP-NEXT:    vcmp.f32 eq, q0, r034; CHECK-MVEFP-NEXT:    vpsel q0, q2, q335; CHECK-MVEFP-NEXT:    bx lr36entry:37  %i = insertelement <4 x float> undef, float %src2, i32 038  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer39  %c = fcmp oeq <4 x float> %src, %sp40  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b41  ret <4 x float> %s42}43 44define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {45; CHECK-MVE-LABEL: vcmp_one_v4f32:46; CHECK-MVE:       @ %bb.0: @ %entry47; CHECK-MVE-NEXT:    vcmp.f32 s0, s448; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr49; CHECK-MVE-NEXT:    vcmp.f32 s3, s450; CHECK-MVE-NEXT:    cset r0, mi51; CHECK-MVE-NEXT:    csinc r0, r0, zr, le52; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr53; CHECK-MVE-NEXT:    vcmp.f32 s1, s454; CHECK-MVE-NEXT:    cset r1, mi55; CHECK-MVE-NEXT:    csinc r1, r1, zr, le56; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr57; CHECK-MVE-NEXT:    vcmp.f32 s2, s458; CHECK-MVE-NEXT:    cset r2, mi59; CHECK-MVE-NEXT:    csinc r2, r2, zr, le60; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr61; CHECK-MVE-NEXT:    cset r3, mi62; CHECK-MVE-NEXT:    csinc r3, r3, zr, le63; CHECK-MVE-NEXT:    cmp r3, #064; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s1065; CHECK-MVE-NEXT:    cmp r2, #066; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s967; CHECK-MVE-NEXT:    cmp r1, #068; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s1169; CHECK-MVE-NEXT:    cmp r0, #070; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s871; CHECK-MVE-NEXT:    bx lr72;73; CHECK-MVEFP-LABEL: vcmp_one_v4f32:74; CHECK-MVEFP:       @ %bb.0: @ %entry75; CHECK-MVEFP-NEXT:    vmov r0, s476; CHECK-MVEFP-NEXT:    vpt.f32 ge, q0, r077; CHECK-MVEFP-NEXT:    vcmpt.f32 le, q0, r078; CHECK-MVEFP-NEXT:    vpsel q0, q3, q279; CHECK-MVEFP-NEXT:    bx lr80entry:81  %i = insertelement <4 x float> undef, float %src2, i32 082  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer83  %c = fcmp one <4 x float> %src, %sp84  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b85  ret <4 x float> %s86}87 88define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {89; CHECK-MVE-LABEL: vcmp_ogt_v4f32:90; CHECK-MVE:       @ %bb.0: @ %entry91; CHECK-MVE-NEXT:    vcmp.f32 s0, s492; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr93; CHECK-MVE-NEXT:    vcmp.f32 s3, s494; CHECK-MVE-NEXT:    cset r0, gt95; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr96; CHECK-MVE-NEXT:    vcmp.f32 s1, s497; CHECK-MVE-NEXT:    cset r1, gt98; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr99; CHECK-MVE-NEXT:    vcmp.f32 s2, s4100; CHECK-MVE-NEXT:    cset r2, gt101; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr102; CHECK-MVE-NEXT:    cset r3, gt103; CHECK-MVE-NEXT:    cmp r3, #0104; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10105; CHECK-MVE-NEXT:    cmp r2, #0106; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9107; CHECK-MVE-NEXT:    cmp r1, #0108; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11109; CHECK-MVE-NEXT:    cmp r0, #0110; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8111; CHECK-MVE-NEXT:    bx lr112;113; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:114; CHECK-MVEFP:       @ %bb.0: @ %entry115; CHECK-MVEFP-NEXT:    vmov r0, s4116; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q0, r0117; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3118; CHECK-MVEFP-NEXT:    bx lr119entry:120  %i = insertelement <4 x float> undef, float %src2, i32 0121  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer122  %c = fcmp ogt <4 x float> %src, %sp123  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b124  ret <4 x float> %s125}126 127define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {128; CHECK-MVE-LABEL: vcmp_oge_v4f32:129; CHECK-MVE:       @ %bb.0: @ %entry130; CHECK-MVE-NEXT:    vcmp.f32 s0, s4131; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr132; CHECK-MVE-NEXT:    vcmp.f32 s3, s4133; CHECK-MVE-NEXT:    cset r0, ge134; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr135; CHECK-MVE-NEXT:    vcmp.f32 s1, s4136; CHECK-MVE-NEXT:    cset r1, ge137; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr138; CHECK-MVE-NEXT:    vcmp.f32 s2, s4139; CHECK-MVE-NEXT:    cset r2, ge140; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr141; CHECK-MVE-NEXT:    cset r3, ge142; CHECK-MVE-NEXT:    cmp r3, #0143; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10144; CHECK-MVE-NEXT:    cmp r2, #0145; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9146; CHECK-MVE-NEXT:    cmp r1, #0147; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11148; CHECK-MVE-NEXT:    cmp r0, #0149; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8150; CHECK-MVE-NEXT:    bx lr151;152; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:153; CHECK-MVEFP:       @ %bb.0: @ %entry154; CHECK-MVEFP-NEXT:    vmov r0, s4155; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q0, r0156; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3157; CHECK-MVEFP-NEXT:    bx lr158entry:159  %i = insertelement <4 x float> undef, float %src2, i32 0160  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer161  %c = fcmp oge <4 x float> %src, %sp162  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b163  ret <4 x float> %s164}165 166define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {167; CHECK-MVE-LABEL: vcmp_olt_v4f32:168; CHECK-MVE:       @ %bb.0: @ %entry169; CHECK-MVE-NEXT:    vcmp.f32 s0, s4170; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr171; CHECK-MVE-NEXT:    vcmp.f32 s3, s4172; CHECK-MVE-NEXT:    cset r0, mi173; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr174; CHECK-MVE-NEXT:    vcmp.f32 s1, s4175; CHECK-MVE-NEXT:    cset r1, mi176; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr177; CHECK-MVE-NEXT:    vcmp.f32 s2, s4178; CHECK-MVE-NEXT:    cset r2, mi179; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr180; CHECK-MVE-NEXT:    cset r3, mi181; CHECK-MVE-NEXT:    cmp r3, #0182; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10183; CHECK-MVE-NEXT:    cmp r2, #0184; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9185; CHECK-MVE-NEXT:    cmp r1, #0186; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11187; CHECK-MVE-NEXT:    cmp r0, #0188; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8189; CHECK-MVE-NEXT:    bx lr190;191; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:192; CHECK-MVEFP:       @ %bb.0: @ %entry193; CHECK-MVEFP-NEXT:    vmov r0, s4194; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q0, r0195; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3196; CHECK-MVEFP-NEXT:    bx lr197entry:198  %i = insertelement <4 x float> undef, float %src2, i32 0199  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer200  %c = fcmp olt <4 x float> %src, %sp201  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b202  ret <4 x float> %s203}204 205define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {206; CHECK-MVE-LABEL: vcmp_ole_v4f32:207; CHECK-MVE:       @ %bb.0: @ %entry208; CHECK-MVE-NEXT:    vcmp.f32 s0, s4209; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr210; CHECK-MVE-NEXT:    vcmp.f32 s3, s4211; CHECK-MVE-NEXT:    cset r0, ls212; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr213; CHECK-MVE-NEXT:    vcmp.f32 s1, s4214; CHECK-MVE-NEXT:    cset r1, ls215; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr216; CHECK-MVE-NEXT:    vcmp.f32 s2, s4217; CHECK-MVE-NEXT:    cset r2, ls218; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr219; CHECK-MVE-NEXT:    cset r3, ls220; CHECK-MVE-NEXT:    cmp r3, #0221; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10222; CHECK-MVE-NEXT:    cmp r2, #0223; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9224; CHECK-MVE-NEXT:    cmp r1, #0225; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11226; CHECK-MVE-NEXT:    cmp r0, #0227; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8228; CHECK-MVE-NEXT:    bx lr229;230; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:231; CHECK-MVEFP:       @ %bb.0: @ %entry232; CHECK-MVEFP-NEXT:    vmov r0, s4233; CHECK-MVEFP-NEXT:    vcmp.f32 le, q0, r0234; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3235; CHECK-MVEFP-NEXT:    bx lr236entry:237  %i = insertelement <4 x float> undef, float %src2, i32 0238  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer239  %c = fcmp ole <4 x float> %src, %sp240  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b241  ret <4 x float> %s242}243 244define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {245; CHECK-MVE-LABEL: vcmp_ueq_v4f32:246; CHECK-MVE:       @ %bb.0: @ %entry247; CHECK-MVE-NEXT:    vcmp.f32 s0, s4248; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr249; CHECK-MVE-NEXT:    vcmp.f32 s3, s4250; CHECK-MVE-NEXT:    cset r0, eq251; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc252; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr253; CHECK-MVE-NEXT:    vcmp.f32 s1, s4254; CHECK-MVE-NEXT:    cset r1, eq255; CHECK-MVE-NEXT:    csinc r1, r1, zr, vc256; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr257; CHECK-MVE-NEXT:    vcmp.f32 s2, s4258; CHECK-MVE-NEXT:    cset r2, eq259; CHECK-MVE-NEXT:    csinc r2, r2, zr, vc260; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr261; CHECK-MVE-NEXT:    cset r3, eq262; CHECK-MVE-NEXT:    csinc r3, r3, zr, vc263; CHECK-MVE-NEXT:    cmp r3, #0264; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10265; CHECK-MVE-NEXT:    cmp r2, #0266; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9267; CHECK-MVE-NEXT:    cmp r1, #0268; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11269; CHECK-MVE-NEXT:    cmp r0, #0270; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8271; CHECK-MVE-NEXT:    bx lr272;273; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:274; CHECK-MVEFP:       @ %bb.0: @ %entry275; CHECK-MVEFP-NEXT:    vmov r0, s4276; CHECK-MVEFP-NEXT:    vpt.f32 ge, q0, r0277; CHECK-MVEFP-NEXT:    vcmpt.f32 le, q0, r0278; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3279; CHECK-MVEFP-NEXT:    bx lr280entry:281  %i = insertelement <4 x float> undef, float %src2, i32 0282  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer283  %c = fcmp ueq <4 x float> %src, %sp284  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b285  ret <4 x float> %s286}287 288define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {289; CHECK-MVE-LABEL: vcmp_une_v4f32:290; CHECK-MVE:       @ %bb.0: @ %entry291; CHECK-MVE-NEXT:    vcmp.f32 s2, s4292; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr293; CHECK-MVE-NEXT:    vcmp.f32 s1, s4294; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10295; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr296; CHECK-MVE-NEXT:    vcmp.f32 s3, s4297; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9298; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr299; CHECK-MVE-NEXT:    vcmp.f32 s0, s4300; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11301; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr302; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8303; CHECK-MVE-NEXT:    bx lr304;305; CHECK-MVEFP-LABEL: vcmp_une_v4f32:306; CHECK-MVEFP:       @ %bb.0: @ %entry307; CHECK-MVEFP-NEXT:    vmov r0, s4308; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, r0309; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3310; CHECK-MVEFP-NEXT:    bx lr311entry:312  %i = insertelement <4 x float> undef, float %src2, i32 0313  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer314  %c = fcmp une <4 x float> %src, %sp315  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b316  ret <4 x float> %s317}318 319define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {320; CHECK-MVE-LABEL: vcmp_ugt_v4f32:321; CHECK-MVE:       @ %bb.0: @ %entry322; CHECK-MVE-NEXT:    vcmp.f32 s0, s4323; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr324; CHECK-MVE-NEXT:    vcmp.f32 s3, s4325; CHECK-MVE-NEXT:    cset r0, hi326; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr327; CHECK-MVE-NEXT:    vcmp.f32 s1, s4328; CHECK-MVE-NEXT:    cset r1, hi329; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr330; CHECK-MVE-NEXT:    vcmp.f32 s2, s4331; CHECK-MVE-NEXT:    cset r2, hi332; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr333; CHECK-MVE-NEXT:    cset r3, hi334; CHECK-MVE-NEXT:    cmp r3, #0335; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10336; CHECK-MVE-NEXT:    cmp r2, #0337; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9338; CHECK-MVE-NEXT:    cmp r1, #0339; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11340; CHECK-MVE-NEXT:    cmp r0, #0341; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8342; CHECK-MVE-NEXT:    bx lr343;344; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:345; CHECK-MVEFP:       @ %bb.0: @ %entry346; CHECK-MVEFP-NEXT:    vmov r0, s4347; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q0, r0348; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3349; CHECK-MVEFP-NEXT:    bx lr350entry:351  %i = insertelement <4 x float> undef, float %src2, i32 0352  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer353  %c = fcmp ugt <4 x float> %src, %sp354  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b355  ret <4 x float> %s356}357 358define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {359; CHECK-MVE-LABEL: vcmp_uge_v4f32:360; CHECK-MVE:       @ %bb.0: @ %entry361; CHECK-MVE-NEXT:    vcmp.f32 s0, s4362; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr363; CHECK-MVE-NEXT:    vcmp.f32 s3, s4364; CHECK-MVE-NEXT:    cset r0, pl365; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr366; CHECK-MVE-NEXT:    vcmp.f32 s1, s4367; CHECK-MVE-NEXT:    cset r1, pl368; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr369; CHECK-MVE-NEXT:    vcmp.f32 s2, s4370; CHECK-MVE-NEXT:    cset r2, pl371; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr372; CHECK-MVE-NEXT:    cset r3, pl373; CHECK-MVE-NEXT:    cmp r3, #0374; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10375; CHECK-MVE-NEXT:    cmp r2, #0376; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9377; CHECK-MVE-NEXT:    cmp r1, #0378; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11379; CHECK-MVE-NEXT:    cmp r0, #0380; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8381; CHECK-MVE-NEXT:    bx lr382;383; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:384; CHECK-MVEFP:       @ %bb.0: @ %entry385; CHECK-MVEFP-NEXT:    vmov r0, s4386; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q0, r0387; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3388; CHECK-MVEFP-NEXT:    bx lr389entry:390  %i = insertelement <4 x float> undef, float %src2, i32 0391  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer392  %c = fcmp uge <4 x float> %src, %sp393  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b394  ret <4 x float> %s395}396 397define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {398; CHECK-MVE-LABEL: vcmp_ult_v4f32:399; CHECK-MVE:       @ %bb.0: @ %entry400; CHECK-MVE-NEXT:    vcmp.f32 s0, s4401; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr402; CHECK-MVE-NEXT:    vcmp.f32 s3, s4403; CHECK-MVE-NEXT:    cset r0, lt404; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr405; CHECK-MVE-NEXT:    vcmp.f32 s1, s4406; CHECK-MVE-NEXT:    cset r1, lt407; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr408; CHECK-MVE-NEXT:    vcmp.f32 s2, s4409; CHECK-MVE-NEXT:    cset r2, lt410; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr411; CHECK-MVE-NEXT:    cset r3, lt412; CHECK-MVE-NEXT:    cmp r3, #0413; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10414; CHECK-MVE-NEXT:    cmp r2, #0415; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9416; CHECK-MVE-NEXT:    cmp r1, #0417; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11418; CHECK-MVE-NEXT:    cmp r0, #0419; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8420; CHECK-MVE-NEXT:    bx lr421;422; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:423; CHECK-MVEFP:       @ %bb.0: @ %entry424; CHECK-MVEFP-NEXT:    vmov r0, s4425; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q0, r0426; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3427; CHECK-MVEFP-NEXT:    bx lr428entry:429  %i = insertelement <4 x float> undef, float %src2, i32 0430  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer431  %c = fcmp ult <4 x float> %src, %sp432  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b433  ret <4 x float> %s434}435 436define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {437; CHECK-MVE-LABEL: vcmp_ule_v4f32:438; CHECK-MVE:       @ %bb.0: @ %entry439; CHECK-MVE-NEXT:    vcmp.f32 s0, s4440; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr441; CHECK-MVE-NEXT:    vcmp.f32 s3, s4442; CHECK-MVE-NEXT:    cset r0, le443; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr444; CHECK-MVE-NEXT:    vcmp.f32 s1, s4445; CHECK-MVE-NEXT:    cset r1, le446; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr447; CHECK-MVE-NEXT:    vcmp.f32 s2, s4448; CHECK-MVE-NEXT:    cset r2, le449; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr450; CHECK-MVE-NEXT:    cset r3, le451; CHECK-MVE-NEXT:    cmp r3, #0452; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10453; CHECK-MVE-NEXT:    cmp r2, #0454; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9455; CHECK-MVE-NEXT:    cmp r1, #0456; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11457; CHECK-MVE-NEXT:    cmp r0, #0458; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8459; CHECK-MVE-NEXT:    bx lr460;461; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:462; CHECK-MVEFP:       @ %bb.0: @ %entry463; CHECK-MVEFP-NEXT:    vmov r0, s4464; CHECK-MVEFP-NEXT:    vcmp.f32 le, q0, r0465; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3466; CHECK-MVEFP-NEXT:    bx lr467entry:468  %i = insertelement <4 x float> undef, float %src2, i32 0469  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer470  %c = fcmp ule <4 x float> %src, %sp471  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b472  ret <4 x float> %s473}474 475define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {476; CHECK-MVE-LABEL: vcmp_ord_v4f32:477; CHECK-MVE:       @ %bb.0: @ %entry478; CHECK-MVE-NEXT:    vcmp.f32 s0, s4479; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr480; CHECK-MVE-NEXT:    vcmp.f32 s3, s4481; CHECK-MVE-NEXT:    cset r0, vc482; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr483; CHECK-MVE-NEXT:    vcmp.f32 s1, s4484; CHECK-MVE-NEXT:    cset r1, vc485; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr486; CHECK-MVE-NEXT:    vcmp.f32 s2, s4487; CHECK-MVE-NEXT:    cset r2, vc488; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr489; CHECK-MVE-NEXT:    cset r3, vc490; CHECK-MVE-NEXT:    cmp r3, #0491; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10492; CHECK-MVE-NEXT:    cmp r2, #0493; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9494; CHECK-MVE-NEXT:    cmp r1, #0495; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11496; CHECK-MVE-NEXT:    cmp r0, #0497; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8498; CHECK-MVE-NEXT:    bx lr499;500; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:501; CHECK-MVEFP:       @ %bb.0: @ %entry502; CHECK-MVEFP-NEXT:    vmov r0, s4503; CHECK-MVEFP-NEXT:    vpt.f32 ge, q0, r0504; CHECK-MVEFP-NEXT:    vcmpt.f32 lt, q0, r0505; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2506; CHECK-MVEFP-NEXT:    bx lr507entry:508  %i = insertelement <4 x float> undef, float %src2, i32 0509  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer510  %c = fcmp ord <4 x float> %src, %sp511  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b512  ret <4 x float> %s513}514 515define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {516; CHECK-MVE-LABEL: vcmp_uno_v4f32:517; CHECK-MVE:       @ %bb.0: @ %entry518; CHECK-MVE-NEXT:    vcmp.f32 s0, s4519; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr520; CHECK-MVE-NEXT:    vcmp.f32 s3, s4521; CHECK-MVE-NEXT:    cset r0, vs522; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr523; CHECK-MVE-NEXT:    vcmp.f32 s1, s4524; CHECK-MVE-NEXT:    cset r1, vs525; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr526; CHECK-MVE-NEXT:    vcmp.f32 s2, s4527; CHECK-MVE-NEXT:    cset r2, vs528; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr529; CHECK-MVE-NEXT:    cset r3, vs530; CHECK-MVE-NEXT:    cmp r3, #0531; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s10532; CHECK-MVE-NEXT:    cmp r2, #0533; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s9534; CHECK-MVE-NEXT:    cmp r1, #0535; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s11536; CHECK-MVE-NEXT:    cmp r0, #0537; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s8538; CHECK-MVE-NEXT:    bx lr539;540; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:541; CHECK-MVEFP:       @ %bb.0: @ %entry542; CHECK-MVEFP-NEXT:    vmov r0, s4543; CHECK-MVEFP-NEXT:    vpt.f32 ge, q0, r0544; CHECK-MVEFP-NEXT:    vcmpt.f32 lt, q0, r0545; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3546; CHECK-MVEFP-NEXT:    bx lr547entry:548  %i = insertelement <4 x float> undef, float %src2, i32 0549  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer550  %c = fcmp uno <4 x float> %src, %sp551  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b552  ret <4 x float> %s553}554 555 556 557define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {558; CHECK-MVE-LABEL: vcmp_oeq_v8f16:559; CHECK-MVE:       @ %bb.0: @ %entry560; CHECK-MVE-NEXT:    vmovx.f16 s6, s0561; CHECK-MVE-NEXT:    vmovx.f16 s5, s12562; CHECK-MVE-NEXT:    vcmp.f16 s6, s4563; CHECK-MVE-NEXT:    vmovx.f16 s6, s8564; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr565; CHECK-MVE-NEXT:    vcmp.f16 s0, s4566; CHECK-MVE-NEXT:    cset r0, eq567; CHECK-MVE-NEXT:    cmp r0, #0568; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6569; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr570; CHECK-MVE-NEXT:    cset r0, eq571; CHECK-MVE-NEXT:    cmp r0, #0572; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8573; CHECK-MVE-NEXT:    vmovx.f16 s8, s13574; CHECK-MVE-NEXT:    vins.f16 s0, s6575; CHECK-MVE-NEXT:    vmovx.f16 s6, s1576; CHECK-MVE-NEXT:    vcmp.f16 s6, s4577; CHECK-MVE-NEXT:    vmovx.f16 s6, s9578; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr579; CHECK-MVE-NEXT:    vcmp.f16 s1, s4580; CHECK-MVE-NEXT:    cset r0, eq581; CHECK-MVE-NEXT:    cmp r0, #0582; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6583; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr584; CHECK-MVE-NEXT:    vmovx.f16 s8, s14585; CHECK-MVE-NEXT:    cset r0, eq586; CHECK-MVE-NEXT:    cmp r0, #0587; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9588; CHECK-MVE-NEXT:    vins.f16 s1, s6589; CHECK-MVE-NEXT:    vmovx.f16 s6, s2590; CHECK-MVE-NEXT:    vcmp.f16 s6, s4591; CHECK-MVE-NEXT:    vmovx.f16 s6, s10592; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr593; CHECK-MVE-NEXT:    vcmp.f16 s2, s4594; CHECK-MVE-NEXT:    cset r0, eq595; CHECK-MVE-NEXT:    cmp r0, #0596; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6597; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr598; CHECK-MVE-NEXT:    vmovx.f16 s8, s15599; CHECK-MVE-NEXT:    cset r0, eq600; CHECK-MVE-NEXT:    cmp r0, #0601; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10602; CHECK-MVE-NEXT:    vins.f16 s2, s6603; CHECK-MVE-NEXT:    vmovx.f16 s6, s3604; CHECK-MVE-NEXT:    vcmp.f16 s6, s4605; CHECK-MVE-NEXT:    vmovx.f16 s6, s11606; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr607; CHECK-MVE-NEXT:    vcmp.f16 s3, s4608; CHECK-MVE-NEXT:    cset r0, eq609; CHECK-MVE-NEXT:    cmp r0, #0610; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6611; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr612; CHECK-MVE-NEXT:    cset r0, eq613; CHECK-MVE-NEXT:    cmp r0, #0614; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11615; CHECK-MVE-NEXT:    vins.f16 s3, s6616; CHECK-MVE-NEXT:    bx lr617;618; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:619; CHECK-MVEFP:       @ %bb.0: @ %entry620; CHECK-MVEFP-NEXT:    vmov.f16 r0, s4621; CHECK-MVEFP-NEXT:    vcmp.f16 eq, q0, r0622; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3623; CHECK-MVEFP-NEXT:    bx lr624entry:625  %i = insertelement <8 x half> undef, half %src2, i32 0626  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer627  %c = fcmp oeq <8 x half> %src, %sp628  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b629  ret <8 x half> %s630}631 632define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {633; CHECK-MVE-LABEL: vcmp_one_v8f16:634; CHECK-MVE:       @ %bb.0: @ %entry635; CHECK-MVE-NEXT:    vmovx.f16 s6, s0636; CHECK-MVE-NEXT:    vmovx.f16 s5, s12637; CHECK-MVE-NEXT:    vcmp.f16 s6, s4638; CHECK-MVE-NEXT:    vmovx.f16 s6, s8639; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr640; CHECK-MVE-NEXT:    vcmp.f16 s0, s4641; CHECK-MVE-NEXT:    cset r0, mi642; CHECK-MVE-NEXT:    csinc r0, r0, zr, le643; CHECK-MVE-NEXT:    cmp r0, #0644; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6645; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr646; CHECK-MVE-NEXT:    cset r0, mi647; CHECK-MVE-NEXT:    csinc r0, r0, zr, le648; CHECK-MVE-NEXT:    cmp r0, #0649; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8650; CHECK-MVE-NEXT:    vmovx.f16 s8, s13651; CHECK-MVE-NEXT:    vins.f16 s0, s6652; CHECK-MVE-NEXT:    vmovx.f16 s6, s1653; CHECK-MVE-NEXT:    vcmp.f16 s6, s4654; CHECK-MVE-NEXT:    vmovx.f16 s6, s9655; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr656; CHECK-MVE-NEXT:    vcmp.f16 s1, s4657; CHECK-MVE-NEXT:    cset r0, mi658; CHECK-MVE-NEXT:    csinc r0, r0, zr, le659; CHECK-MVE-NEXT:    cmp r0, #0660; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6661; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr662; CHECK-MVE-NEXT:    vmovx.f16 s8, s14663; CHECK-MVE-NEXT:    cset r0, mi664; CHECK-MVE-NEXT:    csinc r0, r0, zr, le665; CHECK-MVE-NEXT:    cmp r0, #0666; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9667; CHECK-MVE-NEXT:    vins.f16 s1, s6668; CHECK-MVE-NEXT:    vmovx.f16 s6, s2669; CHECK-MVE-NEXT:    vcmp.f16 s6, s4670; CHECK-MVE-NEXT:    vmovx.f16 s6, s10671; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr672; CHECK-MVE-NEXT:    vcmp.f16 s2, s4673; CHECK-MVE-NEXT:    cset r0, mi674; CHECK-MVE-NEXT:    csinc r0, r0, zr, le675; CHECK-MVE-NEXT:    cmp r0, #0676; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6677; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr678; CHECK-MVE-NEXT:    vmovx.f16 s8, s15679; CHECK-MVE-NEXT:    cset r0, mi680; CHECK-MVE-NEXT:    csinc r0, r0, zr, le681; CHECK-MVE-NEXT:    cmp r0, #0682; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10683; CHECK-MVE-NEXT:    vins.f16 s2, s6684; CHECK-MVE-NEXT:    vmovx.f16 s6, s3685; CHECK-MVE-NEXT:    vcmp.f16 s6, s4686; CHECK-MVE-NEXT:    vmovx.f16 s6, s11687; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr688; CHECK-MVE-NEXT:    vcmp.f16 s3, s4689; CHECK-MVE-NEXT:    cset r0, mi690; CHECK-MVE-NEXT:    csinc r0, r0, zr, le691; CHECK-MVE-NEXT:    cmp r0, #0692; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6693; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr694; CHECK-MVE-NEXT:    cset r0, mi695; CHECK-MVE-NEXT:    csinc r0, r0, zr, le696; CHECK-MVE-NEXT:    cmp r0, #0697; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11698; CHECK-MVE-NEXT:    vins.f16 s3, s6699; CHECK-MVE-NEXT:    bx lr700;701; CHECK-MVEFP-LABEL: vcmp_one_v8f16:702; CHECK-MVEFP:       @ %bb.0: @ %entry703; CHECK-MVEFP-NEXT:    vmov.f16 r0, s4704; CHECK-MVEFP-NEXT:    vpt.f16 ge, q0, r0705; CHECK-MVEFP-NEXT:    vcmpt.f16 le, q0, r0706; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2707; CHECK-MVEFP-NEXT:    bx lr708entry:709  %i = insertelement <8 x half> undef, half %src2, i32 0710  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer711  %c = fcmp one <8 x half> %src, %sp712  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b713  ret <8 x half> %s714}715 716define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {717; CHECK-MVE-LABEL: vcmp_ogt_v8f16:718; CHECK-MVE:       @ %bb.0: @ %entry719; CHECK-MVE-NEXT:    vmovx.f16 s6, s0720; CHECK-MVE-NEXT:    vmovx.f16 s5, s12721; CHECK-MVE-NEXT:    vcmp.f16 s6, s4722; CHECK-MVE-NEXT:    vmovx.f16 s6, s8723; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr724; CHECK-MVE-NEXT:    vcmp.f16 s0, s4725; CHECK-MVE-NEXT:    cset r0, gt726; CHECK-MVE-NEXT:    cmp r0, #0727; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6728; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr729; CHECK-MVE-NEXT:    cset r0, gt730; CHECK-MVE-NEXT:    cmp r0, #0731; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8732; CHECK-MVE-NEXT:    vmovx.f16 s8, s13733; CHECK-MVE-NEXT:    vins.f16 s0, s6734; CHECK-MVE-NEXT:    vmovx.f16 s6, s1735; CHECK-MVE-NEXT:    vcmp.f16 s6, s4736; CHECK-MVE-NEXT:    vmovx.f16 s6, s9737; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr738; CHECK-MVE-NEXT:    vcmp.f16 s1, s4739; CHECK-MVE-NEXT:    cset r0, gt740; CHECK-MVE-NEXT:    cmp r0, #0741; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6742; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr743; CHECK-MVE-NEXT:    vmovx.f16 s8, s14744; CHECK-MVE-NEXT:    cset r0, gt745; CHECK-MVE-NEXT:    cmp r0, #0746; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9747; CHECK-MVE-NEXT:    vins.f16 s1, s6748; CHECK-MVE-NEXT:    vmovx.f16 s6, s2749; CHECK-MVE-NEXT:    vcmp.f16 s6, s4750; CHECK-MVE-NEXT:    vmovx.f16 s6, s10751; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr752; CHECK-MVE-NEXT:    vcmp.f16 s2, s4753; CHECK-MVE-NEXT:    cset r0, gt754; CHECK-MVE-NEXT:    cmp r0, #0755; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6756; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr757; CHECK-MVE-NEXT:    vmovx.f16 s8, s15758; CHECK-MVE-NEXT:    cset r0, gt759; CHECK-MVE-NEXT:    cmp r0, #0760; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10761; CHECK-MVE-NEXT:    vins.f16 s2, s6762; CHECK-MVE-NEXT:    vmovx.f16 s6, s3763; CHECK-MVE-NEXT:    vcmp.f16 s6, s4764; CHECK-MVE-NEXT:    vmovx.f16 s6, s11765; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr766; CHECK-MVE-NEXT:    vcmp.f16 s3, s4767; CHECK-MVE-NEXT:    cset r0, gt768; CHECK-MVE-NEXT:    cmp r0, #0769; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6770; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr771; CHECK-MVE-NEXT:    cset r0, gt772; CHECK-MVE-NEXT:    cmp r0, #0773; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11774; CHECK-MVE-NEXT:    vins.f16 s3, s6775; CHECK-MVE-NEXT:    bx lr776;777; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:778; CHECK-MVEFP:       @ %bb.0: @ %entry779; CHECK-MVEFP-NEXT:    vmov.f16 r0, s4780; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q0, r0781; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3782; CHECK-MVEFP-NEXT:    bx lr783entry:784  %i = insertelement <8 x half> undef, half %src2, i32 0785  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer786  %c = fcmp ogt <8 x half> %src, %sp787  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b788  ret <8 x half> %s789}790 791define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {792; CHECK-MVE-LABEL: vcmp_oge_v8f16:793; CHECK-MVE:       @ %bb.0: @ %entry794; CHECK-MVE-NEXT:    vmovx.f16 s6, s0795; CHECK-MVE-NEXT:    vmovx.f16 s5, s12796; CHECK-MVE-NEXT:    vcmp.f16 s6, s4797; CHECK-MVE-NEXT:    vmovx.f16 s6, s8798; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr799; CHECK-MVE-NEXT:    vcmp.f16 s0, s4800; CHECK-MVE-NEXT:    cset r0, ge801; CHECK-MVE-NEXT:    cmp r0, #0802; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6803; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr804; CHECK-MVE-NEXT:    cset r0, ge805; CHECK-MVE-NEXT:    cmp r0, #0806; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8807; CHECK-MVE-NEXT:    vmovx.f16 s8, s13808; CHECK-MVE-NEXT:    vins.f16 s0, s6809; CHECK-MVE-NEXT:    vmovx.f16 s6, s1810; CHECK-MVE-NEXT:    vcmp.f16 s6, s4811; CHECK-MVE-NEXT:    vmovx.f16 s6, s9812; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr813; CHECK-MVE-NEXT:    vcmp.f16 s1, s4814; CHECK-MVE-NEXT:    cset r0, ge815; CHECK-MVE-NEXT:    cmp r0, #0816; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6817; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr818; CHECK-MVE-NEXT:    vmovx.f16 s8, s14819; CHECK-MVE-NEXT:    cset r0, ge820; CHECK-MVE-NEXT:    cmp r0, #0821; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9822; CHECK-MVE-NEXT:    vins.f16 s1, s6823; CHECK-MVE-NEXT:    vmovx.f16 s6, s2824; CHECK-MVE-NEXT:    vcmp.f16 s6, s4825; CHECK-MVE-NEXT:    vmovx.f16 s6, s10826; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr827; CHECK-MVE-NEXT:    vcmp.f16 s2, s4828; CHECK-MVE-NEXT:    cset r0, ge829; CHECK-MVE-NEXT:    cmp r0, #0830; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6831; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr832; CHECK-MVE-NEXT:    vmovx.f16 s8, s15833; CHECK-MVE-NEXT:    cset r0, ge834; CHECK-MVE-NEXT:    cmp r0, #0835; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10836; CHECK-MVE-NEXT:    vins.f16 s2, s6837; CHECK-MVE-NEXT:    vmovx.f16 s6, s3838; CHECK-MVE-NEXT:    vcmp.f16 s6, s4839; CHECK-MVE-NEXT:    vmovx.f16 s6, s11840; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr841; CHECK-MVE-NEXT:    vcmp.f16 s3, s4842; CHECK-MVE-NEXT:    cset r0, ge843; CHECK-MVE-NEXT:    cmp r0, #0844; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6845; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr846; CHECK-MVE-NEXT:    cset r0, ge847; CHECK-MVE-NEXT:    cmp r0, #0848; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11849; CHECK-MVE-NEXT:    vins.f16 s3, s6850; CHECK-MVE-NEXT:    bx lr851;852; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:853; CHECK-MVEFP:       @ %bb.0: @ %entry854; CHECK-MVEFP-NEXT:    vmov.f16 r0, s4855; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q0, r0856; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3857; CHECK-MVEFP-NEXT:    bx lr858entry:859  %i = insertelement <8 x half> undef, half %src2, i32 0860  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer861  %c = fcmp oge <8 x half> %src, %sp862  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b863  ret <8 x half> %s864}865 866define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {867; CHECK-MVE-LABEL: vcmp_olt_v8f16:868; CHECK-MVE:       @ %bb.0: @ %entry869; CHECK-MVE-NEXT:    vmovx.f16 s6, s0870; CHECK-MVE-NEXT:    vmovx.f16 s5, s12871; CHECK-MVE-NEXT:    vcmp.f16 s6, s4872; CHECK-MVE-NEXT:    vmovx.f16 s6, s8873; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr874; CHECK-MVE-NEXT:    vcmp.f16 s0, s4875; CHECK-MVE-NEXT:    cset r0, mi876; CHECK-MVE-NEXT:    cmp r0, #0877; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6878; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr879; CHECK-MVE-NEXT:    cset r0, mi880; CHECK-MVE-NEXT:    cmp r0, #0881; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8882; CHECK-MVE-NEXT:    vmovx.f16 s8, s13883; CHECK-MVE-NEXT:    vins.f16 s0, s6884; CHECK-MVE-NEXT:    vmovx.f16 s6, s1885; CHECK-MVE-NEXT:    vcmp.f16 s6, s4886; CHECK-MVE-NEXT:    vmovx.f16 s6, s9887; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr888; CHECK-MVE-NEXT:    vcmp.f16 s1, s4889; CHECK-MVE-NEXT:    cset r0, mi890; CHECK-MVE-NEXT:    cmp r0, #0891; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6892; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr893; CHECK-MVE-NEXT:    vmovx.f16 s8, s14894; CHECK-MVE-NEXT:    cset r0, mi895; CHECK-MVE-NEXT:    cmp r0, #0896; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9897; CHECK-MVE-NEXT:    vins.f16 s1, s6898; CHECK-MVE-NEXT:    vmovx.f16 s6, s2899; CHECK-MVE-NEXT:    vcmp.f16 s6, s4900; CHECK-MVE-NEXT:    vmovx.f16 s6, s10901; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr902; CHECK-MVE-NEXT:    vcmp.f16 s2, s4903; CHECK-MVE-NEXT:    cset r0, mi904; CHECK-MVE-NEXT:    cmp r0, #0905; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6906; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr907; CHECK-MVE-NEXT:    vmovx.f16 s8, s15908; CHECK-MVE-NEXT:    cset r0, mi909; CHECK-MVE-NEXT:    cmp r0, #0910; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10911; CHECK-MVE-NEXT:    vins.f16 s2, s6912; CHECK-MVE-NEXT:    vmovx.f16 s6, s3913; CHECK-MVE-NEXT:    vcmp.f16 s6, s4914; CHECK-MVE-NEXT:    vmovx.f16 s6, s11915; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr916; CHECK-MVE-NEXT:    vcmp.f16 s3, s4917; CHECK-MVE-NEXT:    cset r0, mi918; CHECK-MVE-NEXT:    cmp r0, #0919; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6920; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr921; CHECK-MVE-NEXT:    cset r0, mi922; CHECK-MVE-NEXT:    cmp r0, #0923; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11924; CHECK-MVE-NEXT:    vins.f16 s3, s6925; CHECK-MVE-NEXT:    bx lr926;927; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:928; CHECK-MVEFP:       @ %bb.0: @ %entry929; CHECK-MVEFP-NEXT:    vmov.f16 r0, s4930; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q0, r0931; CHECK-MVEFP-NEXT:    vpsel q0, q2, q3932; CHECK-MVEFP-NEXT:    bx lr933entry:934  %i = insertelement <8 x half> undef, half %src2, i32 0935  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer936  %c = fcmp olt <8 x half> %src, %sp937  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b938  ret <8 x half> %s939}940 941define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {942; CHECK-MVE-LABEL: vcmp_ole_v8f16:943; CHECK-MVE:       @ %bb.0: @ %entry944; CHECK-MVE-NEXT:    vmovx.f16 s6, s0945; CHECK-MVE-NEXT:    vmovx.f16 s5, s12946; CHECK-MVE-NEXT:    vcmp.f16 s6, s4947; CHECK-MVE-NEXT:    vmovx.f16 s6, s8948; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr949; CHECK-MVE-NEXT:    vcmp.f16 s0, s4950; CHECK-MVE-NEXT:    cset r0, ls951; CHECK-MVE-NEXT:    cmp r0, #0952; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s6953; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr954; CHECK-MVE-NEXT:    cset r0, ls955; CHECK-MVE-NEXT:    cmp r0, #0956; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s8957; CHECK-MVE-NEXT:    vmovx.f16 s8, s13958; CHECK-MVE-NEXT:    vins.f16 s0, s6959; CHECK-MVE-NEXT:    vmovx.f16 s6, s1960; CHECK-MVE-NEXT:    vcmp.f16 s6, s4961; CHECK-MVE-NEXT:    vmovx.f16 s6, s9962; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr963; CHECK-MVE-NEXT:    vcmp.f16 s1, s4964; CHECK-MVE-NEXT:    cset r0, ls965; CHECK-MVE-NEXT:    cmp r0, #0966; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6967; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr968; CHECK-MVE-NEXT:    vmovx.f16 s8, s14969; CHECK-MVE-NEXT:    cset r0, ls970; CHECK-MVE-NEXT:    cmp r0, #0971; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s9972; CHECK-MVE-NEXT:    vins.f16 s1, s6973; CHECK-MVE-NEXT:    vmovx.f16 s6, s2974; CHECK-MVE-NEXT:    vcmp.f16 s6, s4975; CHECK-MVE-NEXT:    vmovx.f16 s6, s10976; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr977; CHECK-MVE-NEXT:    vcmp.f16 s2, s4978; CHECK-MVE-NEXT:    cset r0, ls979; CHECK-MVE-NEXT:    cmp r0, #0980; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6981; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr982; CHECK-MVE-NEXT:    vmovx.f16 s8, s15983; CHECK-MVE-NEXT:    cset r0, ls984; CHECK-MVE-NEXT:    cmp r0, #0985; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s10986; CHECK-MVE-NEXT:    vins.f16 s2, s6987; CHECK-MVE-NEXT:    vmovx.f16 s6, s3988; CHECK-MVE-NEXT:    vcmp.f16 s6, s4989; CHECK-MVE-NEXT:    vmovx.f16 s6, s11990; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr991; CHECK-MVE-NEXT:    vcmp.f16 s3, s4992; CHECK-MVE-NEXT:    cset r0, ls993; CHECK-MVE-NEXT:    cmp r0, #0994; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s6995; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr996; CHECK-MVE-NEXT:    cset r0, ls997; CHECK-MVE-NEXT:    cmp r0, #0998; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s11999; CHECK-MVE-NEXT:    vins.f16 s3, s61000; CHECK-MVE-NEXT:    bx lr1001;1002; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:1003; CHECK-MVEFP:       @ %bb.0: @ %entry1004; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41005; CHECK-MVEFP-NEXT:    vcmp.f16 le, q0, r01006; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31007; CHECK-MVEFP-NEXT:    bx lr1008entry:1009  %i = insertelement <8 x half> undef, half %src2, i32 01010  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1011  %c = fcmp ole <8 x half> %src, %sp1012  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1013  ret <8 x half> %s1014}1015 1016define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1017; CHECK-MVE-LABEL: vcmp_ueq_v8f16:1018; CHECK-MVE:       @ %bb.0: @ %entry1019; CHECK-MVE-NEXT:    vmovx.f16 s6, s01020; CHECK-MVE-NEXT:    vmovx.f16 s5, s121021; CHECK-MVE-NEXT:    vcmp.f16 s6, s41022; CHECK-MVE-NEXT:    vmovx.f16 s6, s81023; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1024; CHECK-MVE-NEXT:    vcmp.f16 s0, s41025; CHECK-MVE-NEXT:    cset r0, eq1026; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1027; CHECK-MVE-NEXT:    cmp r0, #01028; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61029; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1030; CHECK-MVE-NEXT:    cset r0, eq1031; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1032; CHECK-MVE-NEXT:    cmp r0, #01033; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81034; CHECK-MVE-NEXT:    vmovx.f16 s8, s131035; CHECK-MVE-NEXT:    vins.f16 s0, s61036; CHECK-MVE-NEXT:    vmovx.f16 s6, s11037; CHECK-MVE-NEXT:    vcmp.f16 s6, s41038; CHECK-MVE-NEXT:    vmovx.f16 s6, s91039; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1040; CHECK-MVE-NEXT:    vcmp.f16 s1, s41041; CHECK-MVE-NEXT:    cset r0, eq1042; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1043; CHECK-MVE-NEXT:    cmp r0, #01044; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61045; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1046; CHECK-MVE-NEXT:    vmovx.f16 s8, s141047; CHECK-MVE-NEXT:    cset r0, eq1048; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1049; CHECK-MVE-NEXT:    cmp r0, #01050; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91051; CHECK-MVE-NEXT:    vins.f16 s1, s61052; CHECK-MVE-NEXT:    vmovx.f16 s6, s21053; CHECK-MVE-NEXT:    vcmp.f16 s6, s41054; CHECK-MVE-NEXT:    vmovx.f16 s6, s101055; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1056; CHECK-MVE-NEXT:    vcmp.f16 s2, s41057; CHECK-MVE-NEXT:    cset r0, eq1058; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1059; CHECK-MVE-NEXT:    cmp r0, #01060; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61061; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1062; CHECK-MVE-NEXT:    vmovx.f16 s8, s151063; CHECK-MVE-NEXT:    cset r0, eq1064; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1065; CHECK-MVE-NEXT:    cmp r0, #01066; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101067; CHECK-MVE-NEXT:    vins.f16 s2, s61068; CHECK-MVE-NEXT:    vmovx.f16 s6, s31069; CHECK-MVE-NEXT:    vcmp.f16 s6, s41070; CHECK-MVE-NEXT:    vmovx.f16 s6, s111071; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1072; CHECK-MVE-NEXT:    vcmp.f16 s3, s41073; CHECK-MVE-NEXT:    cset r0, eq1074; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1075; CHECK-MVE-NEXT:    cmp r0, #01076; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61077; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1078; CHECK-MVE-NEXT:    cset r0, eq1079; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1080; CHECK-MVE-NEXT:    cmp r0, #01081; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111082; CHECK-MVE-NEXT:    vins.f16 s3, s61083; CHECK-MVE-NEXT:    bx lr1084;1085; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:1086; CHECK-MVEFP:       @ %bb.0: @ %entry1087; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41088; CHECK-MVEFP-NEXT:    vpt.f16 ge, q0, r01089; CHECK-MVEFP-NEXT:    vcmpt.f16 le, q0, r01090; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31091; CHECK-MVEFP-NEXT:    bx lr1092entry:1093  %i = insertelement <8 x half> undef, half %src2, i32 01094  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1095  %c = fcmp ueq <8 x half> %src, %sp1096  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1097  ret <8 x half> %s1098}1099 1100define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1101; CHECK-MVE-LABEL: vcmp_une_v8f16:1102; CHECK-MVE:       @ %bb.0: @ %entry1103; CHECK-MVE-NEXT:    vmovx.f16 s6, s01104; CHECK-MVE-NEXT:    vmovx.f16 s5, s121105; CHECK-MVE-NEXT:    vcmp.f16 s6, s41106; CHECK-MVE-NEXT:    vmovx.f16 s6, s81107; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1108; CHECK-MVE-NEXT:    vcmp.f16 s0, s41109; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61110; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1111; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81112; CHECK-MVE-NEXT:    vmovx.f16 s8, s131113; CHECK-MVE-NEXT:    vins.f16 s0, s61114; CHECK-MVE-NEXT:    vmovx.f16 s6, s11115; CHECK-MVE-NEXT:    vcmp.f16 s6, s41116; CHECK-MVE-NEXT:    vmovx.f16 s6, s91117; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1118; CHECK-MVE-NEXT:    vcmp.f16 s1, s41119; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61120; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1121; CHECK-MVE-NEXT:    vmovx.f16 s8, s141122; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91123; CHECK-MVE-NEXT:    vins.f16 s1, s61124; CHECK-MVE-NEXT:    vmovx.f16 s6, s21125; CHECK-MVE-NEXT:    vcmp.f16 s6, s41126; CHECK-MVE-NEXT:    vmovx.f16 s6, s101127; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1128; CHECK-MVE-NEXT:    vcmp.f16 s2, s41129; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61130; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1131; CHECK-MVE-NEXT:    vmovx.f16 s8, s151132; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101133; CHECK-MVE-NEXT:    vins.f16 s2, s61134; CHECK-MVE-NEXT:    vmovx.f16 s6, s31135; CHECK-MVE-NEXT:    vcmp.f16 s6, s41136; CHECK-MVE-NEXT:    vmovx.f16 s6, s111137; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1138; CHECK-MVE-NEXT:    vcmp.f16 s3, s41139; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61140; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1141; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111142; CHECK-MVE-NEXT:    vins.f16 s3, s61143; CHECK-MVE-NEXT:    bx lr1144;1145; CHECK-MVEFP-LABEL: vcmp_une_v8f16:1146; CHECK-MVEFP:       @ %bb.0: @ %entry1147; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41148; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, r01149; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31150; CHECK-MVEFP-NEXT:    bx lr1151entry:1152  %i = insertelement <8 x half> undef, half %src2, i32 01153  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1154  %c = fcmp une <8 x half> %src, %sp1155  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1156  ret <8 x half> %s1157}1158 1159define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1160; CHECK-MVE-LABEL: vcmp_ugt_v8f16:1161; CHECK-MVE:       @ %bb.0: @ %entry1162; CHECK-MVE-NEXT:    vmovx.f16 s6, s01163; CHECK-MVE-NEXT:    vmovx.f16 s5, s121164; CHECK-MVE-NEXT:    vcmp.f16 s6, s41165; CHECK-MVE-NEXT:    vmovx.f16 s6, s81166; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1167; CHECK-MVE-NEXT:    vcmp.f16 s0, s41168; CHECK-MVE-NEXT:    cset r0, hi1169; CHECK-MVE-NEXT:    cmp r0, #01170; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61171; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1172; CHECK-MVE-NEXT:    cset r0, hi1173; CHECK-MVE-NEXT:    cmp r0, #01174; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81175; CHECK-MVE-NEXT:    vmovx.f16 s8, s131176; CHECK-MVE-NEXT:    vins.f16 s0, s61177; CHECK-MVE-NEXT:    vmovx.f16 s6, s11178; CHECK-MVE-NEXT:    vcmp.f16 s6, s41179; CHECK-MVE-NEXT:    vmovx.f16 s6, s91180; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1181; CHECK-MVE-NEXT:    vcmp.f16 s1, s41182; CHECK-MVE-NEXT:    cset r0, hi1183; CHECK-MVE-NEXT:    cmp r0, #01184; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61185; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1186; CHECK-MVE-NEXT:    vmovx.f16 s8, s141187; CHECK-MVE-NEXT:    cset r0, hi1188; CHECK-MVE-NEXT:    cmp r0, #01189; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91190; CHECK-MVE-NEXT:    vins.f16 s1, s61191; CHECK-MVE-NEXT:    vmovx.f16 s6, s21192; CHECK-MVE-NEXT:    vcmp.f16 s6, s41193; CHECK-MVE-NEXT:    vmovx.f16 s6, s101194; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1195; CHECK-MVE-NEXT:    vcmp.f16 s2, s41196; CHECK-MVE-NEXT:    cset r0, hi1197; CHECK-MVE-NEXT:    cmp r0, #01198; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61199; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1200; CHECK-MVE-NEXT:    vmovx.f16 s8, s151201; CHECK-MVE-NEXT:    cset r0, hi1202; CHECK-MVE-NEXT:    cmp r0, #01203; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101204; CHECK-MVE-NEXT:    vins.f16 s2, s61205; CHECK-MVE-NEXT:    vmovx.f16 s6, s31206; CHECK-MVE-NEXT:    vcmp.f16 s6, s41207; CHECK-MVE-NEXT:    vmovx.f16 s6, s111208; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1209; CHECK-MVE-NEXT:    vcmp.f16 s3, s41210; CHECK-MVE-NEXT:    cset r0, hi1211; CHECK-MVE-NEXT:    cmp r0, #01212; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61213; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1214; CHECK-MVE-NEXT:    cset r0, hi1215; CHECK-MVE-NEXT:    cmp r0, #01216; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111217; CHECK-MVE-NEXT:    vins.f16 s3, s61218; CHECK-MVE-NEXT:    bx lr1219;1220; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:1221; CHECK-MVEFP:       @ %bb.0: @ %entry1222; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41223; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q0, r01224; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31225; CHECK-MVEFP-NEXT:    bx lr1226entry:1227  %i = insertelement <8 x half> undef, half %src2, i32 01228  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1229  %c = fcmp ugt <8 x half> %src, %sp1230  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1231  ret <8 x half> %s1232}1233 1234define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1235; CHECK-MVE-LABEL: vcmp_uge_v8f16:1236; CHECK-MVE:       @ %bb.0: @ %entry1237; CHECK-MVE-NEXT:    vmovx.f16 s6, s01238; CHECK-MVE-NEXT:    vmovx.f16 s5, s121239; CHECK-MVE-NEXT:    vcmp.f16 s6, s41240; CHECK-MVE-NEXT:    vmovx.f16 s6, s81241; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1242; CHECK-MVE-NEXT:    vcmp.f16 s0, s41243; CHECK-MVE-NEXT:    cset r0, pl1244; CHECK-MVE-NEXT:    cmp r0, #01245; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61246; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1247; CHECK-MVE-NEXT:    cset r0, pl1248; CHECK-MVE-NEXT:    cmp r0, #01249; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81250; CHECK-MVE-NEXT:    vmovx.f16 s8, s131251; CHECK-MVE-NEXT:    vins.f16 s0, s61252; CHECK-MVE-NEXT:    vmovx.f16 s6, s11253; CHECK-MVE-NEXT:    vcmp.f16 s6, s41254; CHECK-MVE-NEXT:    vmovx.f16 s6, s91255; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1256; CHECK-MVE-NEXT:    vcmp.f16 s1, s41257; CHECK-MVE-NEXT:    cset r0, pl1258; CHECK-MVE-NEXT:    cmp r0, #01259; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61260; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1261; CHECK-MVE-NEXT:    vmovx.f16 s8, s141262; CHECK-MVE-NEXT:    cset r0, pl1263; CHECK-MVE-NEXT:    cmp r0, #01264; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91265; CHECK-MVE-NEXT:    vins.f16 s1, s61266; CHECK-MVE-NEXT:    vmovx.f16 s6, s21267; CHECK-MVE-NEXT:    vcmp.f16 s6, s41268; CHECK-MVE-NEXT:    vmovx.f16 s6, s101269; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1270; CHECK-MVE-NEXT:    vcmp.f16 s2, s41271; CHECK-MVE-NEXT:    cset r0, pl1272; CHECK-MVE-NEXT:    cmp r0, #01273; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61274; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1275; CHECK-MVE-NEXT:    vmovx.f16 s8, s151276; CHECK-MVE-NEXT:    cset r0, pl1277; CHECK-MVE-NEXT:    cmp r0, #01278; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101279; CHECK-MVE-NEXT:    vins.f16 s2, s61280; CHECK-MVE-NEXT:    vmovx.f16 s6, s31281; CHECK-MVE-NEXT:    vcmp.f16 s6, s41282; CHECK-MVE-NEXT:    vmovx.f16 s6, s111283; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1284; CHECK-MVE-NEXT:    vcmp.f16 s3, s41285; CHECK-MVE-NEXT:    cset r0, pl1286; CHECK-MVE-NEXT:    cmp r0, #01287; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61288; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1289; CHECK-MVE-NEXT:    cset r0, pl1290; CHECK-MVE-NEXT:    cmp r0, #01291; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111292; CHECK-MVE-NEXT:    vins.f16 s3, s61293; CHECK-MVE-NEXT:    bx lr1294;1295; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:1296; CHECK-MVEFP:       @ %bb.0: @ %entry1297; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41298; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q0, r01299; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31300; CHECK-MVEFP-NEXT:    bx lr1301entry:1302  %i = insertelement <8 x half> undef, half %src2, i32 01303  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1304  %c = fcmp uge <8 x half> %src, %sp1305  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1306  ret <8 x half> %s1307}1308 1309define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1310; CHECK-MVE-LABEL: vcmp_ult_v8f16:1311; CHECK-MVE:       @ %bb.0: @ %entry1312; CHECK-MVE-NEXT:    vmovx.f16 s6, s01313; CHECK-MVE-NEXT:    vmovx.f16 s5, s121314; CHECK-MVE-NEXT:    vcmp.f16 s6, s41315; CHECK-MVE-NEXT:    vmovx.f16 s6, s81316; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1317; CHECK-MVE-NEXT:    vcmp.f16 s0, s41318; CHECK-MVE-NEXT:    cset r0, lt1319; CHECK-MVE-NEXT:    cmp r0, #01320; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61321; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1322; CHECK-MVE-NEXT:    cset r0, lt1323; CHECK-MVE-NEXT:    cmp r0, #01324; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81325; CHECK-MVE-NEXT:    vmovx.f16 s8, s131326; CHECK-MVE-NEXT:    vins.f16 s0, s61327; CHECK-MVE-NEXT:    vmovx.f16 s6, s11328; CHECK-MVE-NEXT:    vcmp.f16 s6, s41329; CHECK-MVE-NEXT:    vmovx.f16 s6, s91330; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1331; CHECK-MVE-NEXT:    vcmp.f16 s1, s41332; CHECK-MVE-NEXT:    cset r0, lt1333; CHECK-MVE-NEXT:    cmp r0, #01334; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61335; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1336; CHECK-MVE-NEXT:    vmovx.f16 s8, s141337; CHECK-MVE-NEXT:    cset r0, lt1338; CHECK-MVE-NEXT:    cmp r0, #01339; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91340; CHECK-MVE-NEXT:    vins.f16 s1, s61341; CHECK-MVE-NEXT:    vmovx.f16 s6, s21342; CHECK-MVE-NEXT:    vcmp.f16 s6, s41343; CHECK-MVE-NEXT:    vmovx.f16 s6, s101344; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1345; CHECK-MVE-NEXT:    vcmp.f16 s2, s41346; CHECK-MVE-NEXT:    cset r0, lt1347; CHECK-MVE-NEXT:    cmp r0, #01348; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61349; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1350; CHECK-MVE-NEXT:    vmovx.f16 s8, s151351; CHECK-MVE-NEXT:    cset r0, lt1352; CHECK-MVE-NEXT:    cmp r0, #01353; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101354; CHECK-MVE-NEXT:    vins.f16 s2, s61355; CHECK-MVE-NEXT:    vmovx.f16 s6, s31356; CHECK-MVE-NEXT:    vcmp.f16 s6, s41357; CHECK-MVE-NEXT:    vmovx.f16 s6, s111358; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1359; CHECK-MVE-NEXT:    vcmp.f16 s3, s41360; CHECK-MVE-NEXT:    cset r0, lt1361; CHECK-MVE-NEXT:    cmp r0, #01362; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61363; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1364; CHECK-MVE-NEXT:    cset r0, lt1365; CHECK-MVE-NEXT:    cmp r0, #01366; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111367; CHECK-MVE-NEXT:    vins.f16 s3, s61368; CHECK-MVE-NEXT:    bx lr1369;1370; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:1371; CHECK-MVEFP:       @ %bb.0: @ %entry1372; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41373; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q0, r01374; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31375; CHECK-MVEFP-NEXT:    bx lr1376entry:1377  %i = insertelement <8 x half> undef, half %src2, i32 01378  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1379  %c = fcmp ult <8 x half> %src, %sp1380  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1381  ret <8 x half> %s1382}1383 1384define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1385; CHECK-MVE-LABEL: vcmp_ule_v8f16:1386; CHECK-MVE:       @ %bb.0: @ %entry1387; CHECK-MVE-NEXT:    vmovx.f16 s6, s01388; CHECK-MVE-NEXT:    vmovx.f16 s5, s121389; CHECK-MVE-NEXT:    vcmp.f16 s6, s41390; CHECK-MVE-NEXT:    vmovx.f16 s6, s81391; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1392; CHECK-MVE-NEXT:    vcmp.f16 s0, s41393; CHECK-MVE-NEXT:    cset r0, le1394; CHECK-MVE-NEXT:    cmp r0, #01395; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61396; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1397; CHECK-MVE-NEXT:    cset r0, le1398; CHECK-MVE-NEXT:    cmp r0, #01399; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81400; CHECK-MVE-NEXT:    vmovx.f16 s8, s131401; CHECK-MVE-NEXT:    vins.f16 s0, s61402; CHECK-MVE-NEXT:    vmovx.f16 s6, s11403; CHECK-MVE-NEXT:    vcmp.f16 s6, s41404; CHECK-MVE-NEXT:    vmovx.f16 s6, s91405; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1406; CHECK-MVE-NEXT:    vcmp.f16 s1, s41407; CHECK-MVE-NEXT:    cset r0, le1408; CHECK-MVE-NEXT:    cmp r0, #01409; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61410; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1411; CHECK-MVE-NEXT:    vmovx.f16 s8, s141412; CHECK-MVE-NEXT:    cset r0, le1413; CHECK-MVE-NEXT:    cmp r0, #01414; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91415; CHECK-MVE-NEXT:    vins.f16 s1, s61416; CHECK-MVE-NEXT:    vmovx.f16 s6, s21417; CHECK-MVE-NEXT:    vcmp.f16 s6, s41418; CHECK-MVE-NEXT:    vmovx.f16 s6, s101419; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1420; CHECK-MVE-NEXT:    vcmp.f16 s2, s41421; CHECK-MVE-NEXT:    cset r0, le1422; CHECK-MVE-NEXT:    cmp r0, #01423; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61424; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1425; CHECK-MVE-NEXT:    vmovx.f16 s8, s151426; CHECK-MVE-NEXT:    cset r0, le1427; CHECK-MVE-NEXT:    cmp r0, #01428; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101429; CHECK-MVE-NEXT:    vins.f16 s2, s61430; CHECK-MVE-NEXT:    vmovx.f16 s6, s31431; CHECK-MVE-NEXT:    vcmp.f16 s6, s41432; CHECK-MVE-NEXT:    vmovx.f16 s6, s111433; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1434; CHECK-MVE-NEXT:    vcmp.f16 s3, s41435; CHECK-MVE-NEXT:    cset r0, le1436; CHECK-MVE-NEXT:    cmp r0, #01437; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61438; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1439; CHECK-MVE-NEXT:    cset r0, le1440; CHECK-MVE-NEXT:    cmp r0, #01441; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111442; CHECK-MVE-NEXT:    vins.f16 s3, s61443; CHECK-MVE-NEXT:    bx lr1444;1445; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:1446; CHECK-MVEFP:       @ %bb.0: @ %entry1447; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41448; CHECK-MVEFP-NEXT:    vcmp.f16 le, q0, r01449; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31450; CHECK-MVEFP-NEXT:    bx lr1451entry:1452  %i = insertelement <8 x half> undef, half %src2, i32 01453  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1454  %c = fcmp ule <8 x half> %src, %sp1455  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1456  ret <8 x half> %s1457}1458 1459define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1460; CHECK-MVE-LABEL: vcmp_ord_v8f16:1461; CHECK-MVE:       @ %bb.0: @ %entry1462; CHECK-MVE-NEXT:    vmovx.f16 s6, s01463; CHECK-MVE-NEXT:    vmovx.f16 s5, s121464; CHECK-MVE-NEXT:    vcmp.f16 s6, s41465; CHECK-MVE-NEXT:    vmovx.f16 s6, s81466; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1467; CHECK-MVE-NEXT:    vcmp.f16 s0, s41468; CHECK-MVE-NEXT:    cset r0, vc1469; CHECK-MVE-NEXT:    cmp r0, #01470; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61471; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1472; CHECK-MVE-NEXT:    cset r0, vc1473; CHECK-MVE-NEXT:    cmp r0, #01474; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81475; CHECK-MVE-NEXT:    vmovx.f16 s8, s131476; CHECK-MVE-NEXT:    vins.f16 s0, s61477; CHECK-MVE-NEXT:    vmovx.f16 s6, s11478; CHECK-MVE-NEXT:    vcmp.f16 s6, s41479; CHECK-MVE-NEXT:    vmovx.f16 s6, s91480; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1481; CHECK-MVE-NEXT:    vcmp.f16 s1, s41482; CHECK-MVE-NEXT:    cset r0, vc1483; CHECK-MVE-NEXT:    cmp r0, #01484; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61485; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1486; CHECK-MVE-NEXT:    vmovx.f16 s8, s141487; CHECK-MVE-NEXT:    cset r0, vc1488; CHECK-MVE-NEXT:    cmp r0, #01489; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91490; CHECK-MVE-NEXT:    vins.f16 s1, s61491; CHECK-MVE-NEXT:    vmovx.f16 s6, s21492; CHECK-MVE-NEXT:    vcmp.f16 s6, s41493; CHECK-MVE-NEXT:    vmovx.f16 s6, s101494; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1495; CHECK-MVE-NEXT:    vcmp.f16 s2, s41496; CHECK-MVE-NEXT:    cset r0, vc1497; CHECK-MVE-NEXT:    cmp r0, #01498; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61499; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1500; CHECK-MVE-NEXT:    vmovx.f16 s8, s151501; CHECK-MVE-NEXT:    cset r0, vc1502; CHECK-MVE-NEXT:    cmp r0, #01503; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101504; CHECK-MVE-NEXT:    vins.f16 s2, s61505; CHECK-MVE-NEXT:    vmovx.f16 s6, s31506; CHECK-MVE-NEXT:    vcmp.f16 s6, s41507; CHECK-MVE-NEXT:    vmovx.f16 s6, s111508; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1509; CHECK-MVE-NEXT:    vcmp.f16 s3, s41510; CHECK-MVE-NEXT:    cset r0, vc1511; CHECK-MVE-NEXT:    cmp r0, #01512; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61513; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1514; CHECK-MVE-NEXT:    cset r0, vc1515; CHECK-MVE-NEXT:    cmp r0, #01516; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111517; CHECK-MVE-NEXT:    vins.f16 s3, s61518; CHECK-MVE-NEXT:    bx lr1519;1520; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:1521; CHECK-MVEFP:       @ %bb.0: @ %entry1522; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41523; CHECK-MVEFP-NEXT:    vpt.f16 ge, q0, r01524; CHECK-MVEFP-NEXT:    vcmpt.f16 lt, q0, r01525; CHECK-MVEFP-NEXT:    vpsel q0, q3, q21526; CHECK-MVEFP-NEXT:    bx lr1527entry:1528  %i = insertelement <8 x half> undef, half %src2, i32 01529  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1530  %c = fcmp ord <8 x half> %src, %sp1531  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1532  ret <8 x half> %s1533}1534 1535define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {1536; CHECK-MVE-LABEL: vcmp_uno_v8f16:1537; CHECK-MVE:       @ %bb.0: @ %entry1538; CHECK-MVE-NEXT:    vmovx.f16 s6, s01539; CHECK-MVE-NEXT:    vmovx.f16 s5, s121540; CHECK-MVE-NEXT:    vcmp.f16 s6, s41541; CHECK-MVE-NEXT:    vmovx.f16 s6, s81542; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1543; CHECK-MVE-NEXT:    vcmp.f16 s0, s41544; CHECK-MVE-NEXT:    cset r0, vs1545; CHECK-MVE-NEXT:    cmp r0, #01546; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s61547; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1548; CHECK-MVE-NEXT:    cset r0, vs1549; CHECK-MVE-NEXT:    cmp r0, #01550; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s81551; CHECK-MVE-NEXT:    vmovx.f16 s8, s131552; CHECK-MVE-NEXT:    vins.f16 s0, s61553; CHECK-MVE-NEXT:    vmovx.f16 s6, s11554; CHECK-MVE-NEXT:    vcmp.f16 s6, s41555; CHECK-MVE-NEXT:    vmovx.f16 s6, s91556; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1557; CHECK-MVE-NEXT:    vcmp.f16 s1, s41558; CHECK-MVE-NEXT:    cset r0, vs1559; CHECK-MVE-NEXT:    cmp r0, #01560; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61561; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1562; CHECK-MVE-NEXT:    vmovx.f16 s8, s141563; CHECK-MVE-NEXT:    cset r0, vs1564; CHECK-MVE-NEXT:    cmp r0, #01565; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s91566; CHECK-MVE-NEXT:    vins.f16 s1, s61567; CHECK-MVE-NEXT:    vmovx.f16 s6, s21568; CHECK-MVE-NEXT:    vcmp.f16 s6, s41569; CHECK-MVE-NEXT:    vmovx.f16 s6, s101570; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1571; CHECK-MVE-NEXT:    vcmp.f16 s2, s41572; CHECK-MVE-NEXT:    cset r0, vs1573; CHECK-MVE-NEXT:    cmp r0, #01574; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61575; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1576; CHECK-MVE-NEXT:    vmovx.f16 s8, s151577; CHECK-MVE-NEXT:    cset r0, vs1578; CHECK-MVE-NEXT:    cmp r0, #01579; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s101580; CHECK-MVE-NEXT:    vins.f16 s2, s61581; CHECK-MVE-NEXT:    vmovx.f16 s6, s31582; CHECK-MVE-NEXT:    vcmp.f16 s6, s41583; CHECK-MVE-NEXT:    vmovx.f16 s6, s111584; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1585; CHECK-MVE-NEXT:    vcmp.f16 s3, s41586; CHECK-MVE-NEXT:    cset r0, vs1587; CHECK-MVE-NEXT:    cmp r0, #01588; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s61589; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1590; CHECK-MVE-NEXT:    cset r0, vs1591; CHECK-MVE-NEXT:    cmp r0, #01592; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s111593; CHECK-MVE-NEXT:    vins.f16 s3, s61594; CHECK-MVE-NEXT:    bx lr1595;1596; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:1597; CHECK-MVEFP:       @ %bb.0: @ %entry1598; CHECK-MVEFP-NEXT:    vmov.f16 r0, s41599; CHECK-MVEFP-NEXT:    vpt.f16 ge, q0, r01600; CHECK-MVEFP-NEXT:    vcmpt.f16 lt, q0, r01601; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31602; CHECK-MVEFP-NEXT:    bx lr1603entry:1604  %i = insertelement <8 x half> undef, half %src2, i32 01605  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer1606  %c = fcmp uno <8 x half> %src, %sp1607  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b1608  ret <8 x half> %s1609}1610 1611 1612; Reversed1613 1614define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1615; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:1616; CHECK-MVE:       @ %bb.0: @ %entry1617; CHECK-MVE-NEXT:    vcmp.f32 s4, s01618; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1619; CHECK-MVE-NEXT:    vcmp.f32 s4, s31620; CHECK-MVE-NEXT:    cset r0, eq1621; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1622; CHECK-MVE-NEXT:    vcmp.f32 s4, s11623; CHECK-MVE-NEXT:    cset r1, eq1624; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1625; CHECK-MVE-NEXT:    vcmp.f32 s4, s21626; CHECK-MVE-NEXT:    cset r2, eq1627; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1628; CHECK-MVE-NEXT:    cset r3, eq1629; CHECK-MVE-NEXT:    cmp r3, #01630; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101631; CHECK-MVE-NEXT:    cmp r2, #01632; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91633; CHECK-MVE-NEXT:    cmp r1, #01634; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111635; CHECK-MVE-NEXT:    cmp r0, #01636; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81637; CHECK-MVE-NEXT:    bx lr1638;1639; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:1640; CHECK-MVEFP:       @ %bb.0: @ %entry1641; CHECK-MVEFP-NEXT:    vmov r0, s41642; CHECK-MVEFP-NEXT:    vcmp.f32 eq, q0, r01643; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31644; CHECK-MVEFP-NEXT:    bx lr1645entry:1646  %i = insertelement <4 x float> undef, float %src2, i32 01647  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1648  %c = fcmp oeq <4 x float> %sp, %src1649  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1650  ret <4 x float> %s1651}1652 1653define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1654; CHECK-MVE-LABEL: vcmp_r_one_v4f32:1655; CHECK-MVE:       @ %bb.0: @ %entry1656; CHECK-MVE-NEXT:    vcmp.f32 s4, s01657; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1658; CHECK-MVE-NEXT:    vcmp.f32 s4, s31659; CHECK-MVE-NEXT:    cset r0, mi1660; CHECK-MVE-NEXT:    csinc r0, r0, zr, le1661; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1662; CHECK-MVE-NEXT:    vcmp.f32 s4, s11663; CHECK-MVE-NEXT:    cset r1, mi1664; CHECK-MVE-NEXT:    csinc r1, r1, zr, le1665; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1666; CHECK-MVE-NEXT:    vcmp.f32 s4, s21667; CHECK-MVE-NEXT:    cset r2, mi1668; CHECK-MVE-NEXT:    csinc r2, r2, zr, le1669; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1670; CHECK-MVE-NEXT:    cset r3, mi1671; CHECK-MVE-NEXT:    csinc r3, r3, zr, le1672; CHECK-MVE-NEXT:    cmp r3, #01673; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101674; CHECK-MVE-NEXT:    cmp r2, #01675; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91676; CHECK-MVE-NEXT:    cmp r1, #01677; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111678; CHECK-MVE-NEXT:    cmp r0, #01679; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81680; CHECK-MVE-NEXT:    bx lr1681;1682; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:1683; CHECK-MVEFP:       @ %bb.0: @ %entry1684; CHECK-MVEFP-NEXT:    vmov r0, s41685; CHECK-MVEFP-NEXT:    vpt.f32 le, q0, r01686; CHECK-MVEFP-NEXT:    vcmpt.f32 ge, q0, r01687; CHECK-MVEFP-NEXT:    vpsel q0, q3, q21688; CHECK-MVEFP-NEXT:    bx lr1689entry:1690  %i = insertelement <4 x float> undef, float %src2, i32 01691  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1692  %c = fcmp one <4 x float> %sp, %src1693  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1694  ret <4 x float> %s1695}1696 1697define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1698; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:1699; CHECK-MVE:       @ %bb.0: @ %entry1700; CHECK-MVE-NEXT:    vcmp.f32 s4, s01701; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1702; CHECK-MVE-NEXT:    vcmp.f32 s4, s31703; CHECK-MVE-NEXT:    cset r0, gt1704; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1705; CHECK-MVE-NEXT:    vcmp.f32 s4, s11706; CHECK-MVE-NEXT:    cset r1, gt1707; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1708; CHECK-MVE-NEXT:    vcmp.f32 s4, s21709; CHECK-MVE-NEXT:    cset r2, gt1710; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1711; CHECK-MVE-NEXT:    cset r3, gt1712; CHECK-MVE-NEXT:    cmp r3, #01713; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101714; CHECK-MVE-NEXT:    cmp r2, #01715; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91716; CHECK-MVE-NEXT:    cmp r1, #01717; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111718; CHECK-MVE-NEXT:    cmp r0, #01719; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81720; CHECK-MVE-NEXT:    bx lr1721;1722; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:1723; CHECK-MVEFP:       @ %bb.0: @ %entry1724; CHECK-MVEFP-NEXT:    vmov r0, s41725; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q0, r01726; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31727; CHECK-MVEFP-NEXT:    bx lr1728entry:1729  %i = insertelement <4 x float> undef, float %src2, i32 01730  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1731  %c = fcmp ogt <4 x float> %sp, %src1732  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1733  ret <4 x float> %s1734}1735 1736define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1737; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:1738; CHECK-MVE:       @ %bb.0: @ %entry1739; CHECK-MVE-NEXT:    vcmp.f32 s4, s01740; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1741; CHECK-MVE-NEXT:    vcmp.f32 s4, s31742; CHECK-MVE-NEXT:    cset r0, ge1743; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1744; CHECK-MVE-NEXT:    vcmp.f32 s4, s11745; CHECK-MVE-NEXT:    cset r1, ge1746; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1747; CHECK-MVE-NEXT:    vcmp.f32 s4, s21748; CHECK-MVE-NEXT:    cset r2, ge1749; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1750; CHECK-MVE-NEXT:    cset r3, ge1751; CHECK-MVE-NEXT:    cmp r3, #01752; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101753; CHECK-MVE-NEXT:    cmp r2, #01754; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91755; CHECK-MVE-NEXT:    cmp r1, #01756; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111757; CHECK-MVE-NEXT:    cmp r0, #01758; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81759; CHECK-MVE-NEXT:    bx lr1760;1761; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:1762; CHECK-MVEFP:       @ %bb.0: @ %entry1763; CHECK-MVEFP-NEXT:    vmov r0, s41764; CHECK-MVEFP-NEXT:    vcmp.f32 le, q0, r01765; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31766; CHECK-MVEFP-NEXT:    bx lr1767entry:1768  %i = insertelement <4 x float> undef, float %src2, i32 01769  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1770  %c = fcmp oge <4 x float> %sp, %src1771  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1772  ret <4 x float> %s1773}1774 1775define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1776; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:1777; CHECK-MVE:       @ %bb.0: @ %entry1778; CHECK-MVE-NEXT:    vcmp.f32 s4, s01779; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1780; CHECK-MVE-NEXT:    vcmp.f32 s4, s31781; CHECK-MVE-NEXT:    cset r0, mi1782; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1783; CHECK-MVE-NEXT:    vcmp.f32 s4, s11784; CHECK-MVE-NEXT:    cset r1, mi1785; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1786; CHECK-MVE-NEXT:    vcmp.f32 s4, s21787; CHECK-MVE-NEXT:    cset r2, mi1788; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1789; CHECK-MVE-NEXT:    cset r3, mi1790; CHECK-MVE-NEXT:    cmp r3, #01791; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101792; CHECK-MVE-NEXT:    cmp r2, #01793; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91794; CHECK-MVE-NEXT:    cmp r1, #01795; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111796; CHECK-MVE-NEXT:    cmp r0, #01797; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81798; CHECK-MVE-NEXT:    bx lr1799;1800; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:1801; CHECK-MVEFP:       @ %bb.0: @ %entry1802; CHECK-MVEFP-NEXT:    vmov r0, s41803; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q0, r01804; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31805; CHECK-MVEFP-NEXT:    bx lr1806entry:1807  %i = insertelement <4 x float> undef, float %src2, i32 01808  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1809  %c = fcmp olt <4 x float> %sp, %src1810  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1811  ret <4 x float> %s1812}1813 1814define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1815; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:1816; CHECK-MVE:       @ %bb.0: @ %entry1817; CHECK-MVE-NEXT:    vcmp.f32 s4, s01818; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1819; CHECK-MVE-NEXT:    vcmp.f32 s4, s31820; CHECK-MVE-NEXT:    cset r0, ls1821; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1822; CHECK-MVE-NEXT:    vcmp.f32 s4, s11823; CHECK-MVE-NEXT:    cset r1, ls1824; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1825; CHECK-MVE-NEXT:    vcmp.f32 s4, s21826; CHECK-MVE-NEXT:    cset r2, ls1827; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1828; CHECK-MVE-NEXT:    cset r3, ls1829; CHECK-MVE-NEXT:    cmp r3, #01830; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101831; CHECK-MVE-NEXT:    cmp r2, #01832; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91833; CHECK-MVE-NEXT:    cmp r1, #01834; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111835; CHECK-MVE-NEXT:    cmp r0, #01836; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81837; CHECK-MVE-NEXT:    bx lr1838;1839; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:1840; CHECK-MVEFP:       @ %bb.0: @ %entry1841; CHECK-MVEFP-NEXT:    vmov r0, s41842; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q0, r01843; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31844; CHECK-MVEFP-NEXT:    bx lr1845entry:1846  %i = insertelement <4 x float> undef, float %src2, i32 01847  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1848  %c = fcmp ole <4 x float> %sp, %src1849  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1850  ret <4 x float> %s1851}1852 1853define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1854; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:1855; CHECK-MVE:       @ %bb.0: @ %entry1856; CHECK-MVE-NEXT:    vcmp.f32 s4, s01857; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1858; CHECK-MVE-NEXT:    vcmp.f32 s4, s31859; CHECK-MVE-NEXT:    cset r0, eq1860; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc1861; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1862; CHECK-MVE-NEXT:    vcmp.f32 s4, s11863; CHECK-MVE-NEXT:    cset r1, eq1864; CHECK-MVE-NEXT:    csinc r1, r1, zr, vc1865; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1866; CHECK-MVE-NEXT:    vcmp.f32 s4, s21867; CHECK-MVE-NEXT:    cset r2, eq1868; CHECK-MVE-NEXT:    csinc r2, r2, zr, vc1869; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1870; CHECK-MVE-NEXT:    cset r3, eq1871; CHECK-MVE-NEXT:    csinc r3, r3, zr, vc1872; CHECK-MVE-NEXT:    cmp r3, #01873; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101874; CHECK-MVE-NEXT:    cmp r2, #01875; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91876; CHECK-MVE-NEXT:    cmp r1, #01877; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111878; CHECK-MVE-NEXT:    cmp r0, #01879; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81880; CHECK-MVE-NEXT:    bx lr1881;1882; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:1883; CHECK-MVEFP:       @ %bb.0: @ %entry1884; CHECK-MVEFP-NEXT:    vmov r0, s41885; CHECK-MVEFP-NEXT:    vpt.f32 le, q0, r01886; CHECK-MVEFP-NEXT:    vcmpt.f32 ge, q0, r01887; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31888; CHECK-MVEFP-NEXT:    bx lr1889entry:1890  %i = insertelement <4 x float> undef, float %src2, i32 01891  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1892  %c = fcmp ueq <4 x float> %sp, %src1893  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1894  ret <4 x float> %s1895}1896 1897define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1898; CHECK-MVE-LABEL: vcmp_r_une_v4f32:1899; CHECK-MVE:       @ %bb.0: @ %entry1900; CHECK-MVE-NEXT:    vcmp.f32 s4, s21901; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1902; CHECK-MVE-NEXT:    vcmp.f32 s4, s11903; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101904; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1905; CHECK-MVE-NEXT:    vcmp.f32 s4, s31906; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91907; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1908; CHECK-MVE-NEXT:    vcmp.f32 s4, s01909; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111910; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1911; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81912; CHECK-MVE-NEXT:    bx lr1913;1914; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32:1915; CHECK-MVEFP:       @ %bb.0: @ %entry1916; CHECK-MVEFP-NEXT:    vmov r0, s41917; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, r01918; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31919; CHECK-MVEFP-NEXT:    bx lr1920entry:1921  %i = insertelement <4 x float> undef, float %src2, i32 01922  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1923  %c = fcmp une <4 x float> %sp, %src1924  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1925  ret <4 x float> %s1926}1927 1928define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1929; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:1930; CHECK-MVE:       @ %bb.0: @ %entry1931; CHECK-MVE-NEXT:    vcmp.f32 s4, s01932; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1933; CHECK-MVE-NEXT:    vcmp.f32 s4, s31934; CHECK-MVE-NEXT:    cset r0, hi1935; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1936; CHECK-MVE-NEXT:    vcmp.f32 s4, s11937; CHECK-MVE-NEXT:    cset r1, hi1938; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1939; CHECK-MVE-NEXT:    vcmp.f32 s4, s21940; CHECK-MVE-NEXT:    cset r2, hi1941; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1942; CHECK-MVE-NEXT:    cset r3, hi1943; CHECK-MVE-NEXT:    cmp r3, #01944; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101945; CHECK-MVE-NEXT:    cmp r2, #01946; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91947; CHECK-MVE-NEXT:    cmp r1, #01948; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111949; CHECK-MVE-NEXT:    cmp r0, #01950; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81951; CHECK-MVE-NEXT:    bx lr1952;1953; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:1954; CHECK-MVEFP:       @ %bb.0: @ %entry1955; CHECK-MVEFP-NEXT:    vmov r0, s41956; CHECK-MVEFP-NEXT:    vcmp.f32 lt, q0, r01957; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31958; CHECK-MVEFP-NEXT:    bx lr1959entry:1960  %i = insertelement <4 x float> undef, float %src2, i32 01961  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer1962  %c = fcmp ugt <4 x float> %sp, %src1963  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b1964  ret <4 x float> %s1965}1966 1967define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {1968; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:1969; CHECK-MVE:       @ %bb.0: @ %entry1970; CHECK-MVE-NEXT:    vcmp.f32 s4, s01971; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1972; CHECK-MVE-NEXT:    vcmp.f32 s4, s31973; CHECK-MVE-NEXT:    cset r0, pl1974; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1975; CHECK-MVE-NEXT:    vcmp.f32 s4, s11976; CHECK-MVE-NEXT:    cset r1, pl1977; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1978; CHECK-MVE-NEXT:    vcmp.f32 s4, s21979; CHECK-MVE-NEXT:    cset r2, pl1980; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr1981; CHECK-MVE-NEXT:    cset r3, pl1982; CHECK-MVE-NEXT:    cmp r3, #01983; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s101984; CHECK-MVE-NEXT:    cmp r2, #01985; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s91986; CHECK-MVE-NEXT:    cmp r1, #01987; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s111988; CHECK-MVE-NEXT:    cmp r0, #01989; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s81990; CHECK-MVE-NEXT:    bx lr1991;1992; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:1993; CHECK-MVEFP:       @ %bb.0: @ %entry1994; CHECK-MVEFP-NEXT:    vmov r0, s41995; CHECK-MVEFP-NEXT:    vcmp.f32 le, q0, r01996; CHECK-MVEFP-NEXT:    vpsel q0, q2, q31997; CHECK-MVEFP-NEXT:    bx lr1998entry:1999  %i = insertelement <4 x float> undef, float %src2, i32 02000  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2001  %c = fcmp uge <4 x float> %sp, %src2002  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b2003  ret <4 x float> %s2004}2005 2006define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {2007; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:2008; CHECK-MVE:       @ %bb.0: @ %entry2009; CHECK-MVE-NEXT:    vcmp.f32 s4, s02010; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2011; CHECK-MVE-NEXT:    vcmp.f32 s4, s32012; CHECK-MVE-NEXT:    cset r0, lt2013; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2014; CHECK-MVE-NEXT:    vcmp.f32 s4, s12015; CHECK-MVE-NEXT:    cset r1, lt2016; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2017; CHECK-MVE-NEXT:    vcmp.f32 s4, s22018; CHECK-MVE-NEXT:    cset r2, lt2019; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2020; CHECK-MVE-NEXT:    cset r3, lt2021; CHECK-MVE-NEXT:    cmp r3, #02022; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s102023; CHECK-MVE-NEXT:    cmp r2, #02024; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s92025; CHECK-MVE-NEXT:    cmp r1, #02026; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s112027; CHECK-MVE-NEXT:    cmp r0, #02028; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s82029; CHECK-MVE-NEXT:    bx lr2030;2031; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:2032; CHECK-MVEFP:       @ %bb.0: @ %entry2033; CHECK-MVEFP-NEXT:    vmov r0, s42034; CHECK-MVEFP-NEXT:    vcmp.f32 gt, q0, r02035; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32036; CHECK-MVEFP-NEXT:    bx lr2037entry:2038  %i = insertelement <4 x float> undef, float %src2, i32 02039  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2040  %c = fcmp ult <4 x float> %sp, %src2041  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b2042  ret <4 x float> %s2043}2044 2045define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {2046; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:2047; CHECK-MVE:       @ %bb.0: @ %entry2048; CHECK-MVE-NEXT:    vcmp.f32 s4, s02049; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2050; CHECK-MVE-NEXT:    vcmp.f32 s4, s32051; CHECK-MVE-NEXT:    cset r0, le2052; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2053; CHECK-MVE-NEXT:    vcmp.f32 s4, s12054; CHECK-MVE-NEXT:    cset r1, le2055; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2056; CHECK-MVE-NEXT:    vcmp.f32 s4, s22057; CHECK-MVE-NEXT:    cset r2, le2058; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2059; CHECK-MVE-NEXT:    cset r3, le2060; CHECK-MVE-NEXT:    cmp r3, #02061; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s102062; CHECK-MVE-NEXT:    cmp r2, #02063; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s92064; CHECK-MVE-NEXT:    cmp r1, #02065; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s112066; CHECK-MVE-NEXT:    cmp r0, #02067; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s82068; CHECK-MVE-NEXT:    bx lr2069;2070; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:2071; CHECK-MVEFP:       @ %bb.0: @ %entry2072; CHECK-MVEFP-NEXT:    vmov r0, s42073; CHECK-MVEFP-NEXT:    vcmp.f32 ge, q0, r02074; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32075; CHECK-MVEFP-NEXT:    bx lr2076entry:2077  %i = insertelement <4 x float> undef, float %src2, i32 02078  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2079  %c = fcmp ule <4 x float> %sp, %src2080  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b2081  ret <4 x float> %s2082}2083 2084define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {2085; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:2086; CHECK-MVE:       @ %bb.0: @ %entry2087; CHECK-MVE-NEXT:    vcmp.f32 s4, s02088; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2089; CHECK-MVE-NEXT:    vcmp.f32 s4, s32090; CHECK-MVE-NEXT:    cset r0, vc2091; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2092; CHECK-MVE-NEXT:    vcmp.f32 s4, s12093; CHECK-MVE-NEXT:    cset r1, vc2094; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2095; CHECK-MVE-NEXT:    vcmp.f32 s4, s22096; CHECK-MVE-NEXT:    cset r2, vc2097; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2098; CHECK-MVE-NEXT:    cset r3, vc2099; CHECK-MVE-NEXT:    cmp r3, #02100; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s102101; CHECK-MVE-NEXT:    cmp r2, #02102; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s92103; CHECK-MVE-NEXT:    cmp r1, #02104; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s112105; CHECK-MVE-NEXT:    cmp r0, #02106; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s82107; CHECK-MVE-NEXT:    bx lr2108;2109; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:2110; CHECK-MVEFP:       @ %bb.0: @ %entry2111; CHECK-MVEFP-NEXT:    vmov r0, s42112; CHECK-MVEFP-NEXT:    vpt.f32 le, q0, r02113; CHECK-MVEFP-NEXT:    vcmpt.f32 gt, q0, r02114; CHECK-MVEFP-NEXT:    vpsel q0, q3, q22115; CHECK-MVEFP-NEXT:    bx lr2116entry:2117  %i = insertelement <4 x float> undef, float %src2, i32 02118  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2119  %c = fcmp ord <4 x float> %sp, %src2120  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b2121  ret <4 x float> %s2122}2123 2124define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {2125; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:2126; CHECK-MVE:       @ %bb.0: @ %entry2127; CHECK-MVE-NEXT:    vcmp.f32 s4, s02128; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2129; CHECK-MVE-NEXT:    vcmp.f32 s4, s32130; CHECK-MVE-NEXT:    cset r0, vs2131; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2132; CHECK-MVE-NEXT:    vcmp.f32 s4, s12133; CHECK-MVE-NEXT:    cset r1, vs2134; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2135; CHECK-MVE-NEXT:    vcmp.f32 s4, s22136; CHECK-MVE-NEXT:    cset r2, vs2137; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2138; CHECK-MVE-NEXT:    cset r3, vs2139; CHECK-MVE-NEXT:    cmp r3, #02140; CHECK-MVE-NEXT:    vseleq.f32 s2, s14, s102141; CHECK-MVE-NEXT:    cmp r2, #02142; CHECK-MVE-NEXT:    vseleq.f32 s1, s13, s92143; CHECK-MVE-NEXT:    cmp r1, #02144; CHECK-MVE-NEXT:    vseleq.f32 s3, s15, s112145; CHECK-MVE-NEXT:    cmp r0, #02146; CHECK-MVE-NEXT:    vseleq.f32 s0, s12, s82147; CHECK-MVE-NEXT:    bx lr2148;2149; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:2150; CHECK-MVEFP:       @ %bb.0: @ %entry2151; CHECK-MVEFP-NEXT:    vmov r0, s42152; CHECK-MVEFP-NEXT:    vpt.f32 le, q0, r02153; CHECK-MVEFP-NEXT:    vcmpt.f32 gt, q0, r02154; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32155; CHECK-MVEFP-NEXT:    bx lr2156entry:2157  %i = insertelement <4 x float> undef, float %src2, i32 02158  %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer2159  %c = fcmp uno <4 x float> %sp, %src2160  %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b2161  ret <4 x float> %s2162}2163 2164 2165 2166define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2167; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:2168; CHECK-MVE:       @ %bb.0: @ %entry2169; CHECK-MVE-NEXT:    vmovx.f16 s6, s02170; CHECK-MVE-NEXT:    vmovx.f16 s5, s122171; CHECK-MVE-NEXT:    vcmp.f16 s4, s62172; CHECK-MVE-NEXT:    vmovx.f16 s6, s82173; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2174; CHECK-MVE-NEXT:    vcmp.f16 s4, s02175; CHECK-MVE-NEXT:    cset r0, eq2176; CHECK-MVE-NEXT:    cmp r0, #02177; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62178; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2179; CHECK-MVE-NEXT:    cset r0, eq2180; CHECK-MVE-NEXT:    cmp r0, #02181; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82182; CHECK-MVE-NEXT:    vmovx.f16 s8, s132183; CHECK-MVE-NEXT:    vins.f16 s0, s62184; CHECK-MVE-NEXT:    vmovx.f16 s6, s12185; CHECK-MVE-NEXT:    vcmp.f16 s4, s62186; CHECK-MVE-NEXT:    vmovx.f16 s6, s92187; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2188; CHECK-MVE-NEXT:    vcmp.f16 s4, s12189; CHECK-MVE-NEXT:    cset r0, eq2190; CHECK-MVE-NEXT:    cmp r0, #02191; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62192; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2193; CHECK-MVE-NEXT:    vmovx.f16 s8, s142194; CHECK-MVE-NEXT:    cset r0, eq2195; CHECK-MVE-NEXT:    cmp r0, #02196; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92197; CHECK-MVE-NEXT:    vins.f16 s1, s62198; CHECK-MVE-NEXT:    vmovx.f16 s6, s22199; CHECK-MVE-NEXT:    vcmp.f16 s4, s62200; CHECK-MVE-NEXT:    vmovx.f16 s6, s102201; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2202; CHECK-MVE-NEXT:    vcmp.f16 s4, s22203; CHECK-MVE-NEXT:    cset r0, eq2204; CHECK-MVE-NEXT:    cmp r0, #02205; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62206; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2207; CHECK-MVE-NEXT:    vmovx.f16 s8, s152208; CHECK-MVE-NEXT:    cset r0, eq2209; CHECK-MVE-NEXT:    cmp r0, #02210; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102211; CHECK-MVE-NEXT:    vins.f16 s2, s62212; CHECK-MVE-NEXT:    vmovx.f16 s6, s32213; CHECK-MVE-NEXT:    vcmp.f16 s4, s62214; CHECK-MVE-NEXT:    vmovx.f16 s6, s112215; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2216; CHECK-MVE-NEXT:    vcmp.f16 s4, s32217; CHECK-MVE-NEXT:    cset r0, eq2218; CHECK-MVE-NEXT:    cmp r0, #02219; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62220; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2221; CHECK-MVE-NEXT:    cset r0, eq2222; CHECK-MVE-NEXT:    cmp r0, #02223; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112224; CHECK-MVE-NEXT:    vins.f16 s3, s62225; CHECK-MVE-NEXT:    bx lr2226;2227; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:2228; CHECK-MVEFP:       @ %bb.0: @ %entry2229; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42230; CHECK-MVEFP-NEXT:    vcmp.f16 eq, q0, r02231; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32232; CHECK-MVEFP-NEXT:    bx lr2233entry:2234  %i = insertelement <8 x half> undef, half %src2, i32 02235  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2236  %c = fcmp oeq <8 x half> %sp, %src2237  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2238  ret <8 x half> %s2239}2240 2241define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2242; CHECK-MVE-LABEL: vcmp_r_one_v8f16:2243; CHECK-MVE:       @ %bb.0: @ %entry2244; CHECK-MVE-NEXT:    vmovx.f16 s6, s02245; CHECK-MVE-NEXT:    vmovx.f16 s5, s122246; CHECK-MVE-NEXT:    vcmp.f16 s4, s62247; CHECK-MVE-NEXT:    vmovx.f16 s6, s82248; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2249; CHECK-MVE-NEXT:    vcmp.f16 s4, s02250; CHECK-MVE-NEXT:    cset r0, mi2251; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2252; CHECK-MVE-NEXT:    cmp r0, #02253; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62254; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2255; CHECK-MVE-NEXT:    cset r0, mi2256; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2257; CHECK-MVE-NEXT:    cmp r0, #02258; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82259; CHECK-MVE-NEXT:    vmovx.f16 s8, s132260; CHECK-MVE-NEXT:    vins.f16 s0, s62261; CHECK-MVE-NEXT:    vmovx.f16 s6, s12262; CHECK-MVE-NEXT:    vcmp.f16 s4, s62263; CHECK-MVE-NEXT:    vmovx.f16 s6, s92264; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2265; CHECK-MVE-NEXT:    vcmp.f16 s4, s12266; CHECK-MVE-NEXT:    cset r0, mi2267; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2268; CHECK-MVE-NEXT:    cmp r0, #02269; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62270; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2271; CHECK-MVE-NEXT:    vmovx.f16 s8, s142272; CHECK-MVE-NEXT:    cset r0, mi2273; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2274; CHECK-MVE-NEXT:    cmp r0, #02275; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92276; CHECK-MVE-NEXT:    vins.f16 s1, s62277; CHECK-MVE-NEXT:    vmovx.f16 s6, s22278; CHECK-MVE-NEXT:    vcmp.f16 s4, s62279; CHECK-MVE-NEXT:    vmovx.f16 s6, s102280; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2281; CHECK-MVE-NEXT:    vcmp.f16 s4, s22282; CHECK-MVE-NEXT:    cset r0, mi2283; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2284; CHECK-MVE-NEXT:    cmp r0, #02285; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62286; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2287; CHECK-MVE-NEXT:    vmovx.f16 s8, s152288; CHECK-MVE-NEXT:    cset r0, mi2289; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2290; CHECK-MVE-NEXT:    cmp r0, #02291; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102292; CHECK-MVE-NEXT:    vins.f16 s2, s62293; CHECK-MVE-NEXT:    vmovx.f16 s6, s32294; CHECK-MVE-NEXT:    vcmp.f16 s4, s62295; CHECK-MVE-NEXT:    vmovx.f16 s6, s112296; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2297; CHECK-MVE-NEXT:    vcmp.f16 s4, s32298; CHECK-MVE-NEXT:    cset r0, mi2299; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2300; CHECK-MVE-NEXT:    cmp r0, #02301; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62302; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2303; CHECK-MVE-NEXT:    cset r0, mi2304; CHECK-MVE-NEXT:    csinc r0, r0, zr, le2305; CHECK-MVE-NEXT:    cmp r0, #02306; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112307; CHECK-MVE-NEXT:    vins.f16 s3, s62308; CHECK-MVE-NEXT:    bx lr2309;2310; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:2311; CHECK-MVEFP:       @ %bb.0: @ %entry2312; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42313; CHECK-MVEFP-NEXT:    vpt.f16 le, q0, r02314; CHECK-MVEFP-NEXT:    vcmpt.f16 ge, q0, r02315; CHECK-MVEFP-NEXT:    vpsel q0, q3, q22316; CHECK-MVEFP-NEXT:    bx lr2317entry:2318  %i = insertelement <8 x half> undef, half %src2, i32 02319  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2320  %c = fcmp one <8 x half> %sp, %src2321  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2322  ret <8 x half> %s2323}2324 2325define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2326; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:2327; CHECK-MVE:       @ %bb.0: @ %entry2328; CHECK-MVE-NEXT:    vmovx.f16 s6, s02329; CHECK-MVE-NEXT:    vmovx.f16 s5, s122330; CHECK-MVE-NEXT:    vcmp.f16 s4, s62331; CHECK-MVE-NEXT:    vmovx.f16 s6, s82332; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2333; CHECK-MVE-NEXT:    vcmp.f16 s4, s02334; CHECK-MVE-NEXT:    cset r0, gt2335; CHECK-MVE-NEXT:    cmp r0, #02336; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62337; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2338; CHECK-MVE-NEXT:    cset r0, gt2339; CHECK-MVE-NEXT:    cmp r0, #02340; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82341; CHECK-MVE-NEXT:    vmovx.f16 s8, s132342; CHECK-MVE-NEXT:    vins.f16 s0, s62343; CHECK-MVE-NEXT:    vmovx.f16 s6, s12344; CHECK-MVE-NEXT:    vcmp.f16 s4, s62345; CHECK-MVE-NEXT:    vmovx.f16 s6, s92346; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2347; CHECK-MVE-NEXT:    vcmp.f16 s4, s12348; CHECK-MVE-NEXT:    cset r0, gt2349; CHECK-MVE-NEXT:    cmp r0, #02350; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62351; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2352; CHECK-MVE-NEXT:    vmovx.f16 s8, s142353; CHECK-MVE-NEXT:    cset r0, gt2354; CHECK-MVE-NEXT:    cmp r0, #02355; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92356; CHECK-MVE-NEXT:    vins.f16 s1, s62357; CHECK-MVE-NEXT:    vmovx.f16 s6, s22358; CHECK-MVE-NEXT:    vcmp.f16 s4, s62359; CHECK-MVE-NEXT:    vmovx.f16 s6, s102360; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2361; CHECK-MVE-NEXT:    vcmp.f16 s4, s22362; CHECK-MVE-NEXT:    cset r0, gt2363; CHECK-MVE-NEXT:    cmp r0, #02364; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62365; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2366; CHECK-MVE-NEXT:    vmovx.f16 s8, s152367; CHECK-MVE-NEXT:    cset r0, gt2368; CHECK-MVE-NEXT:    cmp r0, #02369; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102370; CHECK-MVE-NEXT:    vins.f16 s2, s62371; CHECK-MVE-NEXT:    vmovx.f16 s6, s32372; CHECK-MVE-NEXT:    vcmp.f16 s4, s62373; CHECK-MVE-NEXT:    vmovx.f16 s6, s112374; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2375; CHECK-MVE-NEXT:    vcmp.f16 s4, s32376; CHECK-MVE-NEXT:    cset r0, gt2377; CHECK-MVE-NEXT:    cmp r0, #02378; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62379; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2380; CHECK-MVE-NEXT:    cset r0, gt2381; CHECK-MVE-NEXT:    cmp r0, #02382; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112383; CHECK-MVE-NEXT:    vins.f16 s3, s62384; CHECK-MVE-NEXT:    bx lr2385;2386; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:2387; CHECK-MVEFP:       @ %bb.0: @ %entry2388; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42389; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q0, r02390; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32391; CHECK-MVEFP-NEXT:    bx lr2392entry:2393  %i = insertelement <8 x half> undef, half %src2, i32 02394  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2395  %c = fcmp ogt <8 x half> %sp, %src2396  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2397  ret <8 x half> %s2398}2399 2400define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2401; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:2402; CHECK-MVE:       @ %bb.0: @ %entry2403; CHECK-MVE-NEXT:    vmovx.f16 s6, s02404; CHECK-MVE-NEXT:    vmovx.f16 s5, s122405; CHECK-MVE-NEXT:    vcmp.f16 s4, s62406; CHECK-MVE-NEXT:    vmovx.f16 s6, s82407; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2408; CHECK-MVE-NEXT:    vcmp.f16 s4, s02409; CHECK-MVE-NEXT:    cset r0, ge2410; CHECK-MVE-NEXT:    cmp r0, #02411; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62412; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2413; CHECK-MVE-NEXT:    cset r0, ge2414; CHECK-MVE-NEXT:    cmp r0, #02415; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82416; CHECK-MVE-NEXT:    vmovx.f16 s8, s132417; CHECK-MVE-NEXT:    vins.f16 s0, s62418; CHECK-MVE-NEXT:    vmovx.f16 s6, s12419; CHECK-MVE-NEXT:    vcmp.f16 s4, s62420; CHECK-MVE-NEXT:    vmovx.f16 s6, s92421; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2422; CHECK-MVE-NEXT:    vcmp.f16 s4, s12423; CHECK-MVE-NEXT:    cset r0, ge2424; CHECK-MVE-NEXT:    cmp r0, #02425; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62426; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2427; CHECK-MVE-NEXT:    vmovx.f16 s8, s142428; CHECK-MVE-NEXT:    cset r0, ge2429; CHECK-MVE-NEXT:    cmp r0, #02430; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92431; CHECK-MVE-NEXT:    vins.f16 s1, s62432; CHECK-MVE-NEXT:    vmovx.f16 s6, s22433; CHECK-MVE-NEXT:    vcmp.f16 s4, s62434; CHECK-MVE-NEXT:    vmovx.f16 s6, s102435; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2436; CHECK-MVE-NEXT:    vcmp.f16 s4, s22437; CHECK-MVE-NEXT:    cset r0, ge2438; CHECK-MVE-NEXT:    cmp r0, #02439; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62440; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2441; CHECK-MVE-NEXT:    vmovx.f16 s8, s152442; CHECK-MVE-NEXT:    cset r0, ge2443; CHECK-MVE-NEXT:    cmp r0, #02444; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102445; CHECK-MVE-NEXT:    vins.f16 s2, s62446; CHECK-MVE-NEXT:    vmovx.f16 s6, s32447; CHECK-MVE-NEXT:    vcmp.f16 s4, s62448; CHECK-MVE-NEXT:    vmovx.f16 s6, s112449; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2450; CHECK-MVE-NEXT:    vcmp.f16 s4, s32451; CHECK-MVE-NEXT:    cset r0, ge2452; CHECK-MVE-NEXT:    cmp r0, #02453; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62454; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2455; CHECK-MVE-NEXT:    cset r0, ge2456; CHECK-MVE-NEXT:    cmp r0, #02457; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112458; CHECK-MVE-NEXT:    vins.f16 s3, s62459; CHECK-MVE-NEXT:    bx lr2460;2461; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:2462; CHECK-MVEFP:       @ %bb.0: @ %entry2463; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42464; CHECK-MVEFP-NEXT:    vcmp.f16 le, q0, r02465; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32466; CHECK-MVEFP-NEXT:    bx lr2467entry:2468  %i = insertelement <8 x half> undef, half %src2, i32 02469  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2470  %c = fcmp oge <8 x half> %sp, %src2471  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2472  ret <8 x half> %s2473}2474 2475define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2476; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:2477; CHECK-MVE:       @ %bb.0: @ %entry2478; CHECK-MVE-NEXT:    vmovx.f16 s6, s02479; CHECK-MVE-NEXT:    vmovx.f16 s5, s122480; CHECK-MVE-NEXT:    vcmp.f16 s4, s62481; CHECK-MVE-NEXT:    vmovx.f16 s6, s82482; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2483; CHECK-MVE-NEXT:    vcmp.f16 s4, s02484; CHECK-MVE-NEXT:    cset r0, mi2485; CHECK-MVE-NEXT:    cmp r0, #02486; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62487; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2488; CHECK-MVE-NEXT:    cset r0, mi2489; CHECK-MVE-NEXT:    cmp r0, #02490; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82491; CHECK-MVE-NEXT:    vmovx.f16 s8, s132492; CHECK-MVE-NEXT:    vins.f16 s0, s62493; CHECK-MVE-NEXT:    vmovx.f16 s6, s12494; CHECK-MVE-NEXT:    vcmp.f16 s4, s62495; CHECK-MVE-NEXT:    vmovx.f16 s6, s92496; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2497; CHECK-MVE-NEXT:    vcmp.f16 s4, s12498; CHECK-MVE-NEXT:    cset r0, mi2499; CHECK-MVE-NEXT:    cmp r0, #02500; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62501; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2502; CHECK-MVE-NEXT:    vmovx.f16 s8, s142503; CHECK-MVE-NEXT:    cset r0, mi2504; CHECK-MVE-NEXT:    cmp r0, #02505; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92506; CHECK-MVE-NEXT:    vins.f16 s1, s62507; CHECK-MVE-NEXT:    vmovx.f16 s6, s22508; CHECK-MVE-NEXT:    vcmp.f16 s4, s62509; CHECK-MVE-NEXT:    vmovx.f16 s6, s102510; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2511; CHECK-MVE-NEXT:    vcmp.f16 s4, s22512; CHECK-MVE-NEXT:    cset r0, mi2513; CHECK-MVE-NEXT:    cmp r0, #02514; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62515; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2516; CHECK-MVE-NEXT:    vmovx.f16 s8, s152517; CHECK-MVE-NEXT:    cset r0, mi2518; CHECK-MVE-NEXT:    cmp r0, #02519; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102520; CHECK-MVE-NEXT:    vins.f16 s2, s62521; CHECK-MVE-NEXT:    vmovx.f16 s6, s32522; CHECK-MVE-NEXT:    vcmp.f16 s4, s62523; CHECK-MVE-NEXT:    vmovx.f16 s6, s112524; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2525; CHECK-MVE-NEXT:    vcmp.f16 s4, s32526; CHECK-MVE-NEXT:    cset r0, mi2527; CHECK-MVE-NEXT:    cmp r0, #02528; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62529; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2530; CHECK-MVE-NEXT:    cset r0, mi2531; CHECK-MVE-NEXT:    cmp r0, #02532; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112533; CHECK-MVE-NEXT:    vins.f16 s3, s62534; CHECK-MVE-NEXT:    bx lr2535;2536; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:2537; CHECK-MVEFP:       @ %bb.0: @ %entry2538; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42539; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q0, r02540; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32541; CHECK-MVEFP-NEXT:    bx lr2542entry:2543  %i = insertelement <8 x half> undef, half %src2, i32 02544  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2545  %c = fcmp olt <8 x half> %sp, %src2546  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2547  ret <8 x half> %s2548}2549 2550define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2551; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:2552; CHECK-MVE:       @ %bb.0: @ %entry2553; CHECK-MVE-NEXT:    vmovx.f16 s6, s02554; CHECK-MVE-NEXT:    vmovx.f16 s5, s122555; CHECK-MVE-NEXT:    vcmp.f16 s4, s62556; CHECK-MVE-NEXT:    vmovx.f16 s6, s82557; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2558; CHECK-MVE-NEXT:    vcmp.f16 s4, s02559; CHECK-MVE-NEXT:    cset r0, ls2560; CHECK-MVE-NEXT:    cmp r0, #02561; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62562; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2563; CHECK-MVE-NEXT:    cset r0, ls2564; CHECK-MVE-NEXT:    cmp r0, #02565; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82566; CHECK-MVE-NEXT:    vmovx.f16 s8, s132567; CHECK-MVE-NEXT:    vins.f16 s0, s62568; CHECK-MVE-NEXT:    vmovx.f16 s6, s12569; CHECK-MVE-NEXT:    vcmp.f16 s4, s62570; CHECK-MVE-NEXT:    vmovx.f16 s6, s92571; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2572; CHECK-MVE-NEXT:    vcmp.f16 s4, s12573; CHECK-MVE-NEXT:    cset r0, ls2574; CHECK-MVE-NEXT:    cmp r0, #02575; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62576; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2577; CHECK-MVE-NEXT:    vmovx.f16 s8, s142578; CHECK-MVE-NEXT:    cset r0, ls2579; CHECK-MVE-NEXT:    cmp r0, #02580; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92581; CHECK-MVE-NEXT:    vins.f16 s1, s62582; CHECK-MVE-NEXT:    vmovx.f16 s6, s22583; CHECK-MVE-NEXT:    vcmp.f16 s4, s62584; CHECK-MVE-NEXT:    vmovx.f16 s6, s102585; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2586; CHECK-MVE-NEXT:    vcmp.f16 s4, s22587; CHECK-MVE-NEXT:    cset r0, ls2588; CHECK-MVE-NEXT:    cmp r0, #02589; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62590; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2591; CHECK-MVE-NEXT:    vmovx.f16 s8, s152592; CHECK-MVE-NEXT:    cset r0, ls2593; CHECK-MVE-NEXT:    cmp r0, #02594; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102595; CHECK-MVE-NEXT:    vins.f16 s2, s62596; CHECK-MVE-NEXT:    vmovx.f16 s6, s32597; CHECK-MVE-NEXT:    vcmp.f16 s4, s62598; CHECK-MVE-NEXT:    vmovx.f16 s6, s112599; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2600; CHECK-MVE-NEXT:    vcmp.f16 s4, s32601; CHECK-MVE-NEXT:    cset r0, ls2602; CHECK-MVE-NEXT:    cmp r0, #02603; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62604; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2605; CHECK-MVE-NEXT:    cset r0, ls2606; CHECK-MVE-NEXT:    cmp r0, #02607; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112608; CHECK-MVE-NEXT:    vins.f16 s3, s62609; CHECK-MVE-NEXT:    bx lr2610;2611; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:2612; CHECK-MVEFP:       @ %bb.0: @ %entry2613; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42614; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q0, r02615; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32616; CHECK-MVEFP-NEXT:    bx lr2617entry:2618  %i = insertelement <8 x half> undef, half %src2, i32 02619  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2620  %c = fcmp ole <8 x half> %sp, %src2621  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2622  ret <8 x half> %s2623}2624 2625define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2626; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:2627; CHECK-MVE:       @ %bb.0: @ %entry2628; CHECK-MVE-NEXT:    vmovx.f16 s6, s02629; CHECK-MVE-NEXT:    vmovx.f16 s5, s122630; CHECK-MVE-NEXT:    vcmp.f16 s4, s62631; CHECK-MVE-NEXT:    vmovx.f16 s6, s82632; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2633; CHECK-MVE-NEXT:    vcmp.f16 s4, s02634; CHECK-MVE-NEXT:    cset r0, eq2635; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2636; CHECK-MVE-NEXT:    cmp r0, #02637; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62638; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2639; CHECK-MVE-NEXT:    cset r0, eq2640; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2641; CHECK-MVE-NEXT:    cmp r0, #02642; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82643; CHECK-MVE-NEXT:    vmovx.f16 s8, s132644; CHECK-MVE-NEXT:    vins.f16 s0, s62645; CHECK-MVE-NEXT:    vmovx.f16 s6, s12646; CHECK-MVE-NEXT:    vcmp.f16 s4, s62647; CHECK-MVE-NEXT:    vmovx.f16 s6, s92648; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2649; CHECK-MVE-NEXT:    vcmp.f16 s4, s12650; CHECK-MVE-NEXT:    cset r0, eq2651; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2652; CHECK-MVE-NEXT:    cmp r0, #02653; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62654; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2655; CHECK-MVE-NEXT:    vmovx.f16 s8, s142656; CHECK-MVE-NEXT:    cset r0, eq2657; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2658; CHECK-MVE-NEXT:    cmp r0, #02659; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92660; CHECK-MVE-NEXT:    vins.f16 s1, s62661; CHECK-MVE-NEXT:    vmovx.f16 s6, s22662; CHECK-MVE-NEXT:    vcmp.f16 s4, s62663; CHECK-MVE-NEXT:    vmovx.f16 s6, s102664; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2665; CHECK-MVE-NEXT:    vcmp.f16 s4, s22666; CHECK-MVE-NEXT:    cset r0, eq2667; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2668; CHECK-MVE-NEXT:    cmp r0, #02669; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62670; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2671; CHECK-MVE-NEXT:    vmovx.f16 s8, s152672; CHECK-MVE-NEXT:    cset r0, eq2673; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2674; CHECK-MVE-NEXT:    cmp r0, #02675; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102676; CHECK-MVE-NEXT:    vins.f16 s2, s62677; CHECK-MVE-NEXT:    vmovx.f16 s6, s32678; CHECK-MVE-NEXT:    vcmp.f16 s4, s62679; CHECK-MVE-NEXT:    vmovx.f16 s6, s112680; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2681; CHECK-MVE-NEXT:    vcmp.f16 s4, s32682; CHECK-MVE-NEXT:    cset r0, eq2683; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2684; CHECK-MVE-NEXT:    cmp r0, #02685; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62686; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2687; CHECK-MVE-NEXT:    cset r0, eq2688; CHECK-MVE-NEXT:    csinc r0, r0, zr, vc2689; CHECK-MVE-NEXT:    cmp r0, #02690; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112691; CHECK-MVE-NEXT:    vins.f16 s3, s62692; CHECK-MVE-NEXT:    bx lr2693;2694; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:2695; CHECK-MVEFP:       @ %bb.0: @ %entry2696; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42697; CHECK-MVEFP-NEXT:    vpt.f16 le, q0, r02698; CHECK-MVEFP-NEXT:    vcmpt.f16 ge, q0, r02699; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32700; CHECK-MVEFP-NEXT:    bx lr2701entry:2702  %i = insertelement <8 x half> undef, half %src2, i32 02703  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2704  %c = fcmp ueq <8 x half> %sp, %src2705  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2706  ret <8 x half> %s2707}2708 2709define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2710; CHECK-MVE-LABEL: vcmp_r_une_v8f16:2711; CHECK-MVE:       @ %bb.0: @ %entry2712; CHECK-MVE-NEXT:    vmovx.f16 s6, s02713; CHECK-MVE-NEXT:    vmovx.f16 s5, s122714; CHECK-MVE-NEXT:    vcmp.f16 s4, s62715; CHECK-MVE-NEXT:    vmovx.f16 s6, s82716; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2717; CHECK-MVE-NEXT:    vcmp.f16 s4, s02718; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62719; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2720; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82721; CHECK-MVE-NEXT:    vmovx.f16 s8, s132722; CHECK-MVE-NEXT:    vins.f16 s0, s62723; CHECK-MVE-NEXT:    vmovx.f16 s6, s12724; CHECK-MVE-NEXT:    vcmp.f16 s4, s62725; CHECK-MVE-NEXT:    vmovx.f16 s6, s92726; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2727; CHECK-MVE-NEXT:    vcmp.f16 s4, s12728; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62729; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2730; CHECK-MVE-NEXT:    vmovx.f16 s8, s142731; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92732; CHECK-MVE-NEXT:    vins.f16 s1, s62733; CHECK-MVE-NEXT:    vmovx.f16 s6, s22734; CHECK-MVE-NEXT:    vcmp.f16 s4, s62735; CHECK-MVE-NEXT:    vmovx.f16 s6, s102736; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2737; CHECK-MVE-NEXT:    vcmp.f16 s4, s22738; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62739; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2740; CHECK-MVE-NEXT:    vmovx.f16 s8, s152741; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102742; CHECK-MVE-NEXT:    vins.f16 s2, s62743; CHECK-MVE-NEXT:    vmovx.f16 s6, s32744; CHECK-MVE-NEXT:    vcmp.f16 s4, s62745; CHECK-MVE-NEXT:    vmovx.f16 s6, s112746; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2747; CHECK-MVE-NEXT:    vcmp.f16 s4, s32748; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62749; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2750; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112751; CHECK-MVE-NEXT:    vins.f16 s3, s62752; CHECK-MVE-NEXT:    bx lr2753;2754; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:2755; CHECK-MVEFP:       @ %bb.0: @ %entry2756; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42757; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, r02758; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32759; CHECK-MVEFP-NEXT:    bx lr2760entry:2761  %i = insertelement <8 x half> undef, half %src2, i32 02762  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2763  %c = fcmp une <8 x half> %sp, %src2764  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2765  ret <8 x half> %s2766}2767 2768define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2769; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:2770; CHECK-MVE:       @ %bb.0: @ %entry2771; CHECK-MVE-NEXT:    vmovx.f16 s6, s02772; CHECK-MVE-NEXT:    vmovx.f16 s5, s122773; CHECK-MVE-NEXT:    vcmp.f16 s4, s62774; CHECK-MVE-NEXT:    vmovx.f16 s6, s82775; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2776; CHECK-MVE-NEXT:    vcmp.f16 s4, s02777; CHECK-MVE-NEXT:    cset r0, hi2778; CHECK-MVE-NEXT:    cmp r0, #02779; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62780; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2781; CHECK-MVE-NEXT:    cset r0, hi2782; CHECK-MVE-NEXT:    cmp r0, #02783; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82784; CHECK-MVE-NEXT:    vmovx.f16 s8, s132785; CHECK-MVE-NEXT:    vins.f16 s0, s62786; CHECK-MVE-NEXT:    vmovx.f16 s6, s12787; CHECK-MVE-NEXT:    vcmp.f16 s4, s62788; CHECK-MVE-NEXT:    vmovx.f16 s6, s92789; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2790; CHECK-MVE-NEXT:    vcmp.f16 s4, s12791; CHECK-MVE-NEXT:    cset r0, hi2792; CHECK-MVE-NEXT:    cmp r0, #02793; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62794; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2795; CHECK-MVE-NEXT:    vmovx.f16 s8, s142796; CHECK-MVE-NEXT:    cset r0, hi2797; CHECK-MVE-NEXT:    cmp r0, #02798; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92799; CHECK-MVE-NEXT:    vins.f16 s1, s62800; CHECK-MVE-NEXT:    vmovx.f16 s6, s22801; CHECK-MVE-NEXT:    vcmp.f16 s4, s62802; CHECK-MVE-NEXT:    vmovx.f16 s6, s102803; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2804; CHECK-MVE-NEXT:    vcmp.f16 s4, s22805; CHECK-MVE-NEXT:    cset r0, hi2806; CHECK-MVE-NEXT:    cmp r0, #02807; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62808; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2809; CHECK-MVE-NEXT:    vmovx.f16 s8, s152810; CHECK-MVE-NEXT:    cset r0, hi2811; CHECK-MVE-NEXT:    cmp r0, #02812; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102813; CHECK-MVE-NEXT:    vins.f16 s2, s62814; CHECK-MVE-NEXT:    vmovx.f16 s6, s32815; CHECK-MVE-NEXT:    vcmp.f16 s4, s62816; CHECK-MVE-NEXT:    vmovx.f16 s6, s112817; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2818; CHECK-MVE-NEXT:    vcmp.f16 s4, s32819; CHECK-MVE-NEXT:    cset r0, hi2820; CHECK-MVE-NEXT:    cmp r0, #02821; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62822; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2823; CHECK-MVE-NEXT:    cset r0, hi2824; CHECK-MVE-NEXT:    cmp r0, #02825; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112826; CHECK-MVE-NEXT:    vins.f16 s3, s62827; CHECK-MVE-NEXT:    bx lr2828;2829; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:2830; CHECK-MVEFP:       @ %bb.0: @ %entry2831; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42832; CHECK-MVEFP-NEXT:    vcmp.f16 lt, q0, r02833; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32834; CHECK-MVEFP-NEXT:    bx lr2835entry:2836  %i = insertelement <8 x half> undef, half %src2, i32 02837  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2838  %c = fcmp ugt <8 x half> %sp, %src2839  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2840  ret <8 x half> %s2841}2842 2843define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2844; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:2845; CHECK-MVE:       @ %bb.0: @ %entry2846; CHECK-MVE-NEXT:    vmovx.f16 s6, s02847; CHECK-MVE-NEXT:    vmovx.f16 s5, s122848; CHECK-MVE-NEXT:    vcmp.f16 s4, s62849; CHECK-MVE-NEXT:    vmovx.f16 s6, s82850; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2851; CHECK-MVE-NEXT:    vcmp.f16 s4, s02852; CHECK-MVE-NEXT:    cset r0, pl2853; CHECK-MVE-NEXT:    cmp r0, #02854; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62855; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2856; CHECK-MVE-NEXT:    cset r0, pl2857; CHECK-MVE-NEXT:    cmp r0, #02858; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82859; CHECK-MVE-NEXT:    vmovx.f16 s8, s132860; CHECK-MVE-NEXT:    vins.f16 s0, s62861; CHECK-MVE-NEXT:    vmovx.f16 s6, s12862; CHECK-MVE-NEXT:    vcmp.f16 s4, s62863; CHECK-MVE-NEXT:    vmovx.f16 s6, s92864; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2865; CHECK-MVE-NEXT:    vcmp.f16 s4, s12866; CHECK-MVE-NEXT:    cset r0, pl2867; CHECK-MVE-NEXT:    cmp r0, #02868; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62869; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2870; CHECK-MVE-NEXT:    vmovx.f16 s8, s142871; CHECK-MVE-NEXT:    cset r0, pl2872; CHECK-MVE-NEXT:    cmp r0, #02873; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92874; CHECK-MVE-NEXT:    vins.f16 s1, s62875; CHECK-MVE-NEXT:    vmovx.f16 s6, s22876; CHECK-MVE-NEXT:    vcmp.f16 s4, s62877; CHECK-MVE-NEXT:    vmovx.f16 s6, s102878; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2879; CHECK-MVE-NEXT:    vcmp.f16 s4, s22880; CHECK-MVE-NEXT:    cset r0, pl2881; CHECK-MVE-NEXT:    cmp r0, #02882; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62883; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2884; CHECK-MVE-NEXT:    vmovx.f16 s8, s152885; CHECK-MVE-NEXT:    cset r0, pl2886; CHECK-MVE-NEXT:    cmp r0, #02887; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102888; CHECK-MVE-NEXT:    vins.f16 s2, s62889; CHECK-MVE-NEXT:    vmovx.f16 s6, s32890; CHECK-MVE-NEXT:    vcmp.f16 s4, s62891; CHECK-MVE-NEXT:    vmovx.f16 s6, s112892; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2893; CHECK-MVE-NEXT:    vcmp.f16 s4, s32894; CHECK-MVE-NEXT:    cset r0, pl2895; CHECK-MVE-NEXT:    cmp r0, #02896; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62897; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2898; CHECK-MVE-NEXT:    cset r0, pl2899; CHECK-MVE-NEXT:    cmp r0, #02900; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112901; CHECK-MVE-NEXT:    vins.f16 s3, s62902; CHECK-MVE-NEXT:    bx lr2903;2904; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:2905; CHECK-MVEFP:       @ %bb.0: @ %entry2906; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42907; CHECK-MVEFP-NEXT:    vcmp.f16 le, q0, r02908; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32909; CHECK-MVEFP-NEXT:    bx lr2910entry:2911  %i = insertelement <8 x half> undef, half %src2, i32 02912  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2913  %c = fcmp uge <8 x half> %sp, %src2914  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2915  ret <8 x half> %s2916}2917 2918define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2919; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:2920; CHECK-MVE:       @ %bb.0: @ %entry2921; CHECK-MVE-NEXT:    vmovx.f16 s6, s02922; CHECK-MVE-NEXT:    vmovx.f16 s5, s122923; CHECK-MVE-NEXT:    vcmp.f16 s4, s62924; CHECK-MVE-NEXT:    vmovx.f16 s6, s82925; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2926; CHECK-MVE-NEXT:    vcmp.f16 s4, s02927; CHECK-MVE-NEXT:    cset r0, lt2928; CHECK-MVE-NEXT:    cmp r0, #02929; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s62930; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2931; CHECK-MVE-NEXT:    cset r0, lt2932; CHECK-MVE-NEXT:    cmp r0, #02933; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s82934; CHECK-MVE-NEXT:    vmovx.f16 s8, s132935; CHECK-MVE-NEXT:    vins.f16 s0, s62936; CHECK-MVE-NEXT:    vmovx.f16 s6, s12937; CHECK-MVE-NEXT:    vcmp.f16 s4, s62938; CHECK-MVE-NEXT:    vmovx.f16 s6, s92939; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2940; CHECK-MVE-NEXT:    vcmp.f16 s4, s12941; CHECK-MVE-NEXT:    cset r0, lt2942; CHECK-MVE-NEXT:    cmp r0, #02943; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62944; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2945; CHECK-MVE-NEXT:    vmovx.f16 s8, s142946; CHECK-MVE-NEXT:    cset r0, lt2947; CHECK-MVE-NEXT:    cmp r0, #02948; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s92949; CHECK-MVE-NEXT:    vins.f16 s1, s62950; CHECK-MVE-NEXT:    vmovx.f16 s6, s22951; CHECK-MVE-NEXT:    vcmp.f16 s4, s62952; CHECK-MVE-NEXT:    vmovx.f16 s6, s102953; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2954; CHECK-MVE-NEXT:    vcmp.f16 s4, s22955; CHECK-MVE-NEXT:    cset r0, lt2956; CHECK-MVE-NEXT:    cmp r0, #02957; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62958; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2959; CHECK-MVE-NEXT:    vmovx.f16 s8, s152960; CHECK-MVE-NEXT:    cset r0, lt2961; CHECK-MVE-NEXT:    cmp r0, #02962; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s102963; CHECK-MVE-NEXT:    vins.f16 s2, s62964; CHECK-MVE-NEXT:    vmovx.f16 s6, s32965; CHECK-MVE-NEXT:    vcmp.f16 s4, s62966; CHECK-MVE-NEXT:    vmovx.f16 s6, s112967; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2968; CHECK-MVE-NEXT:    vcmp.f16 s4, s32969; CHECK-MVE-NEXT:    cset r0, lt2970; CHECK-MVE-NEXT:    cmp r0, #02971; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s62972; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr2973; CHECK-MVE-NEXT:    cset r0, lt2974; CHECK-MVE-NEXT:    cmp r0, #02975; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s112976; CHECK-MVE-NEXT:    vins.f16 s3, s62977; CHECK-MVE-NEXT:    bx lr2978;2979; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:2980; CHECK-MVEFP:       @ %bb.0: @ %entry2981; CHECK-MVEFP-NEXT:    vmov.f16 r0, s42982; CHECK-MVEFP-NEXT:    vcmp.f16 gt, q0, r02983; CHECK-MVEFP-NEXT:    vpsel q0, q2, q32984; CHECK-MVEFP-NEXT:    bx lr2985entry:2986  %i = insertelement <8 x half> undef, half %src2, i32 02987  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer2988  %c = fcmp ult <8 x half> %sp, %src2989  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b2990  ret <8 x half> %s2991}2992 2993define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {2994; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:2995; CHECK-MVE:       @ %bb.0: @ %entry2996; CHECK-MVE-NEXT:    vmovx.f16 s6, s02997; CHECK-MVE-NEXT:    vmovx.f16 s5, s122998; CHECK-MVE-NEXT:    vcmp.f16 s4, s62999; CHECK-MVE-NEXT:    vmovx.f16 s6, s83000; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3001; CHECK-MVE-NEXT:    vcmp.f16 s4, s03002; CHECK-MVE-NEXT:    cset r0, le3003; CHECK-MVE-NEXT:    cmp r0, #03004; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s63005; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3006; CHECK-MVE-NEXT:    cset r0, le3007; CHECK-MVE-NEXT:    cmp r0, #03008; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s83009; CHECK-MVE-NEXT:    vmovx.f16 s8, s133010; CHECK-MVE-NEXT:    vins.f16 s0, s63011; CHECK-MVE-NEXT:    vmovx.f16 s6, s13012; CHECK-MVE-NEXT:    vcmp.f16 s4, s63013; CHECK-MVE-NEXT:    vmovx.f16 s6, s93014; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3015; CHECK-MVE-NEXT:    vcmp.f16 s4, s13016; CHECK-MVE-NEXT:    cset r0, le3017; CHECK-MVE-NEXT:    cmp r0, #03018; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63019; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3020; CHECK-MVE-NEXT:    vmovx.f16 s8, s143021; CHECK-MVE-NEXT:    cset r0, le3022; CHECK-MVE-NEXT:    cmp r0, #03023; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s93024; CHECK-MVE-NEXT:    vins.f16 s1, s63025; CHECK-MVE-NEXT:    vmovx.f16 s6, s23026; CHECK-MVE-NEXT:    vcmp.f16 s4, s63027; CHECK-MVE-NEXT:    vmovx.f16 s6, s103028; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3029; CHECK-MVE-NEXT:    vcmp.f16 s4, s23030; CHECK-MVE-NEXT:    cset r0, le3031; CHECK-MVE-NEXT:    cmp r0, #03032; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63033; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3034; CHECK-MVE-NEXT:    vmovx.f16 s8, s153035; CHECK-MVE-NEXT:    cset r0, le3036; CHECK-MVE-NEXT:    cmp r0, #03037; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s103038; CHECK-MVE-NEXT:    vins.f16 s2, s63039; CHECK-MVE-NEXT:    vmovx.f16 s6, s33040; CHECK-MVE-NEXT:    vcmp.f16 s4, s63041; CHECK-MVE-NEXT:    vmovx.f16 s6, s113042; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3043; CHECK-MVE-NEXT:    vcmp.f16 s4, s33044; CHECK-MVE-NEXT:    cset r0, le3045; CHECK-MVE-NEXT:    cmp r0, #03046; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63047; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3048; CHECK-MVE-NEXT:    cset r0, le3049; CHECK-MVE-NEXT:    cmp r0, #03050; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s113051; CHECK-MVE-NEXT:    vins.f16 s3, s63052; CHECK-MVE-NEXT:    bx lr3053;3054; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:3055; CHECK-MVEFP:       @ %bb.0: @ %entry3056; CHECK-MVEFP-NEXT:    vmov.f16 r0, s43057; CHECK-MVEFP-NEXT:    vcmp.f16 ge, q0, r03058; CHECK-MVEFP-NEXT:    vpsel q0, q2, q33059; CHECK-MVEFP-NEXT:    bx lr3060entry:3061  %i = insertelement <8 x half> undef, half %src2, i32 03062  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer3063  %c = fcmp ule <8 x half> %sp, %src3064  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b3065  ret <8 x half> %s3066}3067 3068define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {3069; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:3070; CHECK-MVE:       @ %bb.0: @ %entry3071; CHECK-MVE-NEXT:    vmovx.f16 s6, s03072; CHECK-MVE-NEXT:    vmovx.f16 s5, s123073; CHECK-MVE-NEXT:    vcmp.f16 s4, s63074; CHECK-MVE-NEXT:    vmovx.f16 s6, s83075; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3076; CHECK-MVE-NEXT:    vcmp.f16 s4, s03077; CHECK-MVE-NEXT:    cset r0, vc3078; CHECK-MVE-NEXT:    cmp r0, #03079; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s63080; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3081; CHECK-MVE-NEXT:    cset r0, vc3082; CHECK-MVE-NEXT:    cmp r0, #03083; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s83084; CHECK-MVE-NEXT:    vmovx.f16 s8, s133085; CHECK-MVE-NEXT:    vins.f16 s0, s63086; CHECK-MVE-NEXT:    vmovx.f16 s6, s13087; CHECK-MVE-NEXT:    vcmp.f16 s4, s63088; CHECK-MVE-NEXT:    vmovx.f16 s6, s93089; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3090; CHECK-MVE-NEXT:    vcmp.f16 s4, s13091; CHECK-MVE-NEXT:    cset r0, vc3092; CHECK-MVE-NEXT:    cmp r0, #03093; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63094; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3095; CHECK-MVE-NEXT:    vmovx.f16 s8, s143096; CHECK-MVE-NEXT:    cset r0, vc3097; CHECK-MVE-NEXT:    cmp r0, #03098; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s93099; CHECK-MVE-NEXT:    vins.f16 s1, s63100; CHECK-MVE-NEXT:    vmovx.f16 s6, s23101; CHECK-MVE-NEXT:    vcmp.f16 s4, s63102; CHECK-MVE-NEXT:    vmovx.f16 s6, s103103; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3104; CHECK-MVE-NEXT:    vcmp.f16 s4, s23105; CHECK-MVE-NEXT:    cset r0, vc3106; CHECK-MVE-NEXT:    cmp r0, #03107; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63108; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3109; CHECK-MVE-NEXT:    vmovx.f16 s8, s153110; CHECK-MVE-NEXT:    cset r0, vc3111; CHECK-MVE-NEXT:    cmp r0, #03112; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s103113; CHECK-MVE-NEXT:    vins.f16 s2, s63114; CHECK-MVE-NEXT:    vmovx.f16 s6, s33115; CHECK-MVE-NEXT:    vcmp.f16 s4, s63116; CHECK-MVE-NEXT:    vmovx.f16 s6, s113117; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3118; CHECK-MVE-NEXT:    vcmp.f16 s4, s33119; CHECK-MVE-NEXT:    cset r0, vc3120; CHECK-MVE-NEXT:    cmp r0, #03121; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63122; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3123; CHECK-MVE-NEXT:    cset r0, vc3124; CHECK-MVE-NEXT:    cmp r0, #03125; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s113126; CHECK-MVE-NEXT:    vins.f16 s3, s63127; CHECK-MVE-NEXT:    bx lr3128;3129; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:3130; CHECK-MVEFP:       @ %bb.0: @ %entry3131; CHECK-MVEFP-NEXT:    vmov.f16 r0, s43132; CHECK-MVEFP-NEXT:    vpt.f16 le, q0, r03133; CHECK-MVEFP-NEXT:    vcmpt.f16 gt, q0, r03134; CHECK-MVEFP-NEXT:    vpsel q0, q3, q23135; CHECK-MVEFP-NEXT:    bx lr3136entry:3137  %i = insertelement <8 x half> undef, half %src2, i32 03138  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer3139  %c = fcmp ord <8 x half> %sp, %src3140  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b3141  ret <8 x half> %s3142}3143 3144define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {3145; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:3146; CHECK-MVE:       @ %bb.0: @ %entry3147; CHECK-MVE-NEXT:    vmovx.f16 s6, s03148; CHECK-MVE-NEXT:    vmovx.f16 s5, s123149; CHECK-MVE-NEXT:    vcmp.f16 s4, s63150; CHECK-MVE-NEXT:    vmovx.f16 s6, s83151; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3152; CHECK-MVE-NEXT:    vcmp.f16 s4, s03153; CHECK-MVE-NEXT:    cset r0, vs3154; CHECK-MVE-NEXT:    cmp r0, #03155; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s63156; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3157; CHECK-MVE-NEXT:    cset r0, vs3158; CHECK-MVE-NEXT:    cmp r0, #03159; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s83160; CHECK-MVE-NEXT:    vmovx.f16 s8, s133161; CHECK-MVE-NEXT:    vins.f16 s0, s63162; CHECK-MVE-NEXT:    vmovx.f16 s6, s13163; CHECK-MVE-NEXT:    vcmp.f16 s4, s63164; CHECK-MVE-NEXT:    vmovx.f16 s6, s93165; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3166; CHECK-MVE-NEXT:    vcmp.f16 s4, s13167; CHECK-MVE-NEXT:    cset r0, vs3168; CHECK-MVE-NEXT:    cmp r0, #03169; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63170; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3171; CHECK-MVE-NEXT:    vmovx.f16 s8, s143172; CHECK-MVE-NEXT:    cset r0, vs3173; CHECK-MVE-NEXT:    cmp r0, #03174; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s93175; CHECK-MVE-NEXT:    vins.f16 s1, s63176; CHECK-MVE-NEXT:    vmovx.f16 s6, s23177; CHECK-MVE-NEXT:    vcmp.f16 s4, s63178; CHECK-MVE-NEXT:    vmovx.f16 s6, s103179; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3180; CHECK-MVE-NEXT:    vcmp.f16 s4, s23181; CHECK-MVE-NEXT:    cset r0, vs3182; CHECK-MVE-NEXT:    cmp r0, #03183; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63184; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3185; CHECK-MVE-NEXT:    vmovx.f16 s8, s153186; CHECK-MVE-NEXT:    cset r0, vs3187; CHECK-MVE-NEXT:    cmp r0, #03188; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s103189; CHECK-MVE-NEXT:    vins.f16 s2, s63190; CHECK-MVE-NEXT:    vmovx.f16 s6, s33191; CHECK-MVE-NEXT:    vcmp.f16 s4, s63192; CHECK-MVE-NEXT:    vmovx.f16 s6, s113193; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3194; CHECK-MVE-NEXT:    vcmp.f16 s4, s33195; CHECK-MVE-NEXT:    cset r0, vs3196; CHECK-MVE-NEXT:    cmp r0, #03197; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63198; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3199; CHECK-MVE-NEXT:    cset r0, vs3200; CHECK-MVE-NEXT:    cmp r0, #03201; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s113202; CHECK-MVE-NEXT:    vins.f16 s3, s63203; CHECK-MVE-NEXT:    bx lr3204;3205; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:3206; CHECK-MVEFP:       @ %bb.0: @ %entry3207; CHECK-MVEFP-NEXT:    vmov.f16 r0, s43208; CHECK-MVEFP-NEXT:    vpt.f16 le, q0, r03209; CHECK-MVEFP-NEXT:    vcmpt.f16 gt, q0, r03210; CHECK-MVEFP-NEXT:    vpsel q0, q2, q33211; CHECK-MVEFP-NEXT:    bx lr3212entry:3213  %i = insertelement <8 x half> undef, half %src2, i32 03214  %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer3215  %c = fcmp uno <8 x half> %sp, %src3216  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b3217  ret <8 x half> %s3218}3219 3220 3221 3222define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {3223; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc:3224; CHECK-MVE:       @ %bb.0: @ %entry3225; CHECK-MVE-NEXT:    vmovx.f16 s6, s03226; CHECK-MVE-NEXT:    vmovx.f16 s5, s123227; CHECK-MVE-NEXT:    vcmp.f16 s6, s43228; CHECK-MVE-NEXT:    vmovx.f16 s6, s83229; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3230; CHECK-MVE-NEXT:    vcmp.f16 s0, s43231; CHECK-MVE-NEXT:    cset r0, eq3232; CHECK-MVE-NEXT:    cmp r0, #03233; CHECK-MVE-NEXT:    vseleq.f16 s6, s5, s63234; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3235; CHECK-MVE-NEXT:    cset r0, eq3236; CHECK-MVE-NEXT:    cmp r0, #03237; CHECK-MVE-NEXT:    vseleq.f16 s0, s12, s83238; CHECK-MVE-NEXT:    vmovx.f16 s8, s133239; CHECK-MVE-NEXT:    vins.f16 s0, s63240; CHECK-MVE-NEXT:    vmovx.f16 s6, s13241; CHECK-MVE-NEXT:    vcmp.f16 s6, s43242; CHECK-MVE-NEXT:    vmovx.f16 s6, s93243; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3244; CHECK-MVE-NEXT:    vcmp.f16 s1, s43245; CHECK-MVE-NEXT:    cset r0, eq3246; CHECK-MVE-NEXT:    cmp r0, #03247; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63248; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3249; CHECK-MVE-NEXT:    vmovx.f16 s8, s143250; CHECK-MVE-NEXT:    cset r0, eq3251; CHECK-MVE-NEXT:    cmp r0, #03252; CHECK-MVE-NEXT:    vseleq.f16 s1, s13, s93253; CHECK-MVE-NEXT:    vins.f16 s1, s63254; CHECK-MVE-NEXT:    vmovx.f16 s6, s23255; CHECK-MVE-NEXT:    vcmp.f16 s6, s43256; CHECK-MVE-NEXT:    vmovx.f16 s6, s103257; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3258; CHECK-MVE-NEXT:    vcmp.f16 s2, s43259; CHECK-MVE-NEXT:    cset r0, eq3260; CHECK-MVE-NEXT:    cmp r0, #03261; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63262; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3263; CHECK-MVE-NEXT:    vmovx.f16 s8, s153264; CHECK-MVE-NEXT:    cset r0, eq3265; CHECK-MVE-NEXT:    cmp r0, #03266; CHECK-MVE-NEXT:    vseleq.f16 s2, s14, s103267; CHECK-MVE-NEXT:    vins.f16 s2, s63268; CHECK-MVE-NEXT:    vmovx.f16 s6, s33269; CHECK-MVE-NEXT:    vcmp.f16 s6, s43270; CHECK-MVE-NEXT:    vmovx.f16 s6, s113271; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3272; CHECK-MVE-NEXT:    vcmp.f16 s3, s43273; CHECK-MVE-NEXT:    cset r0, eq3274; CHECK-MVE-NEXT:    cmp r0, #03275; CHECK-MVE-NEXT:    vseleq.f16 s6, s8, s63276; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr3277; CHECK-MVE-NEXT:    cset r0, eq3278; CHECK-MVE-NEXT:    cmp r0, #03279; CHECK-MVE-NEXT:    vseleq.f16 s3, s15, s113280; CHECK-MVE-NEXT:    vins.f16 s3, s63281; CHECK-MVE-NEXT:    bx lr3282;3283; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc:3284; CHECK-MVEFP:       @ %bb.0: @ %entry3285; CHECK-MVEFP-NEXT:    vmov.f16 r0, s43286; CHECK-MVEFP-NEXT:    vcmp.f16 eq, q0, r03287; CHECK-MVEFP-NEXT:    vpsel q0, q2, q33288; CHECK-MVEFP-NEXT:    bx lr3289entry:3290  %src2bc = bitcast half %src2 to i163291  %i = insertelement <8 x i16> undef, i16 %src2bc, i32 03292  %spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer3293  %sp = bitcast <8 x i16> %spbc to <8 x half>3294  %c = fcmp oeq <8 x half> %src, %sp3295  %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b3296  ret <8 x half> %s3297}3298