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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: vcmp_eq_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i32 eq, q0, r08; CHECK-NEXT: vpsel q0, q1, q29; CHECK-NEXT: bx lr10entry:11 %i = insertelement <4 x i32> undef, i32 %src2, i32 012 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer13 %c = icmp eq <4 x i32> %src, %sp14 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b15 ret <4 x i32> %s16}17 18define arm_aapcs_vfpcc <4 x i32> @vcmp_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {19; CHECK-LABEL: vcmp_ne_v4i32:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vcmp.i32 ne, q0, r022; CHECK-NEXT: vpsel q0, q1, q223; CHECK-NEXT: bx lr24entry:25 %i = insertelement <4 x i32> undef, i32 %src2, i32 026 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer27 %c = icmp ne <4 x i32> %src, %sp28 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b29 ret <4 x i32> %s30}31 32define arm_aapcs_vfpcc <4 x i32> @vcmp_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {33; CHECK-LABEL: vcmp_sgt_v4i32:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vcmp.s32 gt, q0, r036; CHECK-NEXT: vpsel q0, q1, q237; CHECK-NEXT: bx lr38entry:39 %i = insertelement <4 x i32> undef, i32 %src2, i32 040 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer41 %c = icmp sgt <4 x i32> %src, %sp42 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b43 ret <4 x i32> %s44}45 46define arm_aapcs_vfpcc <4 x i32> @vcmp_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {47; CHECK-LABEL: vcmp_sge_v4i32:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vcmp.s32 ge, q0, r050; CHECK-NEXT: vpsel q0, q1, q251; CHECK-NEXT: bx lr52entry:53 %i = insertelement <4 x i32> undef, i32 %src2, i32 054 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer55 %c = icmp sge <4 x i32> %src, %sp56 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b57 ret <4 x i32> %s58}59 60define arm_aapcs_vfpcc <4 x i32> @vcmp_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {61; CHECK-LABEL: vcmp_slt_v4i32:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vcmp.s32 lt, q0, r064; CHECK-NEXT: vpsel q0, q1, q265; CHECK-NEXT: bx lr66entry:67 %i = insertelement <4 x i32> undef, i32 %src2, i32 068 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer69 %c = icmp slt <4 x i32> %src, %sp70 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b71 ret <4 x i32> %s72}73 74define arm_aapcs_vfpcc <4 x i32> @vcmp_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {75; CHECK-LABEL: vcmp_sle_v4i32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vcmp.s32 le, q0, r078; CHECK-NEXT: vpsel q0, q1, q279; CHECK-NEXT: bx lr80entry:81 %i = insertelement <4 x i32> undef, i32 %src2, i32 082 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer83 %c = icmp sle <4 x i32> %src, %sp84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b85 ret <4 x i32> %s86}87 88define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {89; CHECK-LABEL: vcmp_ugt_v4i32:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vcmp.u32 hi, q0, r092; CHECK-NEXT: vpsel q0, q1, q293; CHECK-NEXT: bx lr94entry:95 %i = insertelement <4 x i32> undef, i32 %src2, i32 096 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer97 %c = icmp ugt <4 x i32> %src, %sp98 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b99 ret <4 x i32> %s100}101 102define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {103; CHECK-LABEL: vcmp_uge_v4i32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vcmp.u32 cs, q0, r0106; CHECK-NEXT: vpsel q0, q1, q2107; CHECK-NEXT: bx lr108entry:109 %i = insertelement <4 x i32> undef, i32 %src2, i32 0110 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer111 %c = icmp uge <4 x i32> %src, %sp112 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b113 ret <4 x i32> %s114}115 116define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {117; CHECK-LABEL: vcmp_ult_v4i32:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vdup.32 q3, r0120; CHECK-NEXT: vcmp.u32 hi, q3, q0121; CHECK-NEXT: vpsel q0, q1, q2122; CHECK-NEXT: bx lr123entry:124 %i = insertelement <4 x i32> undef, i32 %src2, i32 0125 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer126 %c = icmp ult <4 x i32> %src, %sp127 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b128 ret <4 x i32> %s129}130 131define arm_aapcs_vfpcc <4 x i32> @vcmp_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {132; CHECK-LABEL: vcmp_ule_v4i32:133; CHECK: @ %bb.0: @ %entry134; CHECK-NEXT: vdup.32 q3, r0135; CHECK-NEXT: vcmp.u32 cs, q3, q0136; CHECK-NEXT: vpsel q0, q1, q2137; CHECK-NEXT: bx lr138entry:139 %i = insertelement <4 x i32> undef, i32 %src2, i32 0140 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer141 %c = icmp ule <4 x i32> %src, %sp142 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b143 ret <4 x i32> %s144}145 146 147define arm_aapcs_vfpcc <8 x i16> @vcmp_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {148; CHECK-LABEL: vcmp_eq_v8i16:149; CHECK: @ %bb.0: @ %entry150; CHECK-NEXT: vcmp.i16 eq, q0, r0151; CHECK-NEXT: vpsel q0, q1, q2152; CHECK-NEXT: bx lr153entry:154 %i = insertelement <8 x i16> undef, i16 %src2, i32 0155 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer156 %c = icmp eq <8 x i16> %src, %sp157 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b158 ret <8 x i16> %s159}160 161define arm_aapcs_vfpcc <8 x i16> @vcmp_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {162; CHECK-LABEL: vcmp_ne_v8i16:163; CHECK: @ %bb.0: @ %entry164; CHECK-NEXT: vcmp.i16 ne, q0, r0165; CHECK-NEXT: vpsel q0, q1, q2166; CHECK-NEXT: bx lr167entry:168 %i = insertelement <8 x i16> undef, i16 %src2, i32 0169 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer170 %c = icmp ne <8 x i16> %src, %sp171 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b172 ret <8 x i16> %s173}174 175define arm_aapcs_vfpcc <8 x i16> @vcmp_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {176; CHECK-LABEL: vcmp_sgt_v8i16:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: vcmp.s16 gt, q0, r0179; CHECK-NEXT: vpsel q0, q1, q2180; CHECK-NEXT: bx lr181entry:182 %i = insertelement <8 x i16> undef, i16 %src2, i32 0183 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer184 %c = icmp sgt <8 x i16> %src, %sp185 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b186 ret <8 x i16> %s187}188 189define arm_aapcs_vfpcc <8 x i16> @vcmp_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {190; CHECK-LABEL: vcmp_sge_v8i16:191; CHECK: @ %bb.0: @ %entry192; CHECK-NEXT: vcmp.s16 ge, q0, r0193; CHECK-NEXT: vpsel q0, q1, q2194; CHECK-NEXT: bx lr195entry:196 %i = insertelement <8 x i16> undef, i16 %src2, i32 0197 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer198 %c = icmp sge <8 x i16> %src, %sp199 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b200 ret <8 x i16> %s201}202 203define arm_aapcs_vfpcc <8 x i16> @vcmp_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {204; CHECK-LABEL: vcmp_slt_v8i16:205; CHECK: @ %bb.0: @ %entry206; CHECK-NEXT: vcmp.s16 lt, q0, r0207; CHECK-NEXT: vpsel q0, q1, q2208; CHECK-NEXT: bx lr209entry:210 %i = insertelement <8 x i16> undef, i16 %src2, i32 0211 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer212 %c = icmp slt <8 x i16> %src, %sp213 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b214 ret <8 x i16> %s215}216 217define arm_aapcs_vfpcc <8 x i16> @vcmp_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {218; CHECK-LABEL: vcmp_sle_v8i16:219; CHECK: @ %bb.0: @ %entry220; CHECK-NEXT: vcmp.s16 le, q0, r0221; CHECK-NEXT: vpsel q0, q1, q2222; CHECK-NEXT: bx lr223entry:224 %i = insertelement <8 x i16> undef, i16 %src2, i32 0225 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer226 %c = icmp sle <8 x i16> %src, %sp227 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b228 ret <8 x i16> %s229}230 231define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {232; CHECK-LABEL: vcmp_ugt_v8i16:233; CHECK: @ %bb.0: @ %entry234; CHECK-NEXT: vcmp.u16 hi, q0, r0235; CHECK-NEXT: vpsel q0, q1, q2236; CHECK-NEXT: bx lr237entry:238 %i = insertelement <8 x i16> undef, i16 %src2, i32 0239 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer240 %c = icmp ugt <8 x i16> %src, %sp241 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b242 ret <8 x i16> %s243}244 245define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {246; CHECK-LABEL: vcmp_uge_v8i16:247; CHECK: @ %bb.0: @ %entry248; CHECK-NEXT: vcmp.u16 cs, q0, r0249; CHECK-NEXT: vpsel q0, q1, q2250; CHECK-NEXT: bx lr251entry:252 %i = insertelement <8 x i16> undef, i16 %src2, i32 0253 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer254 %c = icmp uge <8 x i16> %src, %sp255 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b256 ret <8 x i16> %s257}258 259define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {260; CHECK-LABEL: vcmp_ult_v8i16:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vdup.16 q3, r0263; CHECK-NEXT: vcmp.u16 hi, q3, q0264; CHECK-NEXT: vpsel q0, q1, q2265; CHECK-NEXT: bx lr266entry:267 %i = insertelement <8 x i16> undef, i16 %src2, i32 0268 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer269 %c = icmp ult <8 x i16> %src, %sp270 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b271 ret <8 x i16> %s272}273 274define arm_aapcs_vfpcc <8 x i16> @vcmp_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {275; CHECK-LABEL: vcmp_ule_v8i16:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vdup.16 q3, r0278; CHECK-NEXT: vcmp.u16 cs, q3, q0279; CHECK-NEXT: vpsel q0, q1, q2280; CHECK-NEXT: bx lr281entry:282 %i = insertelement <8 x i16> undef, i16 %src2, i32 0283 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer284 %c = icmp ule <8 x i16> %src, %sp285 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b286 ret <8 x i16> %s287}288 289 290define arm_aapcs_vfpcc <16 x i8> @vcmp_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {291; CHECK-LABEL: vcmp_eq_v16i8:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: vcmp.i8 eq, q0, r0294; CHECK-NEXT: vpsel q0, q1, q2295; CHECK-NEXT: bx lr296entry:297 %i = insertelement <16 x i8> undef, i8 %src2, i32 0298 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer299 %c = icmp eq <16 x i8> %src, %sp300 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b301 ret <16 x i8> %s302}303 304define arm_aapcs_vfpcc <16 x i8> @vcmp_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {305; CHECK-LABEL: vcmp_ne_v16i8:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vcmp.i8 ne, q0, r0308; CHECK-NEXT: vpsel q0, q1, q2309; CHECK-NEXT: bx lr310entry:311 %i = insertelement <16 x i8> undef, i8 %src2, i32 0312 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer313 %c = icmp ne <16 x i8> %src, %sp314 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b315 ret <16 x i8> %s316}317 318define arm_aapcs_vfpcc <16 x i8> @vcmp_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {319; CHECK-LABEL: vcmp_sgt_v16i8:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: vcmp.s8 gt, q0, r0322; CHECK-NEXT: vpsel q0, q1, q2323; CHECK-NEXT: bx lr324entry:325 %i = insertelement <16 x i8> undef, i8 %src2, i32 0326 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer327 %c = icmp sgt <16 x i8> %src, %sp328 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b329 ret <16 x i8> %s330}331 332define arm_aapcs_vfpcc <16 x i8> @vcmp_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {333; CHECK-LABEL: vcmp_sge_v16i8:334; CHECK: @ %bb.0: @ %entry335; CHECK-NEXT: vcmp.s8 ge, q0, r0336; CHECK-NEXT: vpsel q0, q1, q2337; CHECK-NEXT: bx lr338entry:339 %i = insertelement <16 x i8> undef, i8 %src2, i32 0340 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer341 %c = icmp sge <16 x i8> %src, %sp342 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b343 ret <16 x i8> %s344}345 346define arm_aapcs_vfpcc <16 x i8> @vcmp_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {347; CHECK-LABEL: vcmp_slt_v16i8:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vcmp.s8 lt, q0, r0350; CHECK-NEXT: vpsel q0, q1, q2351; CHECK-NEXT: bx lr352entry:353 %i = insertelement <16 x i8> undef, i8 %src2, i32 0354 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer355 %c = icmp slt <16 x i8> %src, %sp356 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b357 ret <16 x i8> %s358}359 360define arm_aapcs_vfpcc <16 x i8> @vcmp_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {361; CHECK-LABEL: vcmp_sle_v16i8:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vcmp.s8 le, q0, r0364; CHECK-NEXT: vpsel q0, q1, q2365; CHECK-NEXT: bx lr366entry:367 %i = insertelement <16 x i8> undef, i8 %src2, i32 0368 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer369 %c = icmp sle <16 x i8> %src, %sp370 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b371 ret <16 x i8> %s372}373 374define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {375; CHECK-LABEL: vcmp_ugt_v16i8:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vcmp.u8 hi, q0, r0378; CHECK-NEXT: vpsel q0, q1, q2379; CHECK-NEXT: bx lr380entry:381 %i = insertelement <16 x i8> undef, i8 %src2, i32 0382 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer383 %c = icmp ugt <16 x i8> %src, %sp384 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b385 ret <16 x i8> %s386}387 388define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {389; CHECK-LABEL: vcmp_uge_v16i8:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vcmp.u8 cs, q0, r0392; CHECK-NEXT: vpsel q0, q1, q2393; CHECK-NEXT: bx lr394entry:395 %i = insertelement <16 x i8> undef, i8 %src2, i32 0396 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer397 %c = icmp uge <16 x i8> %src, %sp398 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b399 ret <16 x i8> %s400}401 402define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {403; CHECK-LABEL: vcmp_ult_v16i8:404; CHECK: @ %bb.0: @ %entry405; CHECK-NEXT: vdup.8 q3, r0406; CHECK-NEXT: vcmp.u8 hi, q3, q0407; CHECK-NEXT: vpsel q0, q1, q2408; CHECK-NEXT: bx lr409entry:410 %i = insertelement <16 x i8> undef, i8 %src2, i32 0411 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer412 %c = icmp ult <16 x i8> %src, %sp413 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b414 ret <16 x i8> %s415}416 417define arm_aapcs_vfpcc <16 x i8> @vcmp_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {418; CHECK-LABEL: vcmp_ule_v16i8:419; CHECK: @ %bb.0: @ %entry420; CHECK-NEXT: vdup.8 q3, r0421; CHECK-NEXT: vcmp.u8 cs, q3, q0422; CHECK-NEXT: vpsel q0, q1, q2423; CHECK-NEXT: bx lr424entry:425 %i = insertelement <16 x i8> undef, i8 %src2, i32 0426 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer427 %c = icmp ule <16 x i8> %src, %sp428 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b429 ret <16 x i8> %s430}431 432 433define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) {434; CHECK-LABEL: vcmp_eq_v2i64:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: vmov r2, r3, d0437; CHECK-NEXT: eors r3, r1438; CHECK-NEXT: eors r2, r0439; CHECK-NEXT: orrs r2, r3440; CHECK-NEXT: mov.w r3, #0441; CHECK-NEXT: csetm r2, eq442; CHECK-NEXT: bfi r3, r2, #0, #8443; CHECK-NEXT: vmov r12, r2, d1444; CHECK-NEXT: eors r1, r2445; CHECK-NEXT: eor.w r0, r0, r12446; CHECK-NEXT: orrs r0, r1447; CHECK-NEXT: csetm r0, eq448; CHECK-NEXT: bfi r3, r0, #8, #8449; CHECK-NEXT: vmsr p0, r3450; CHECK-NEXT: vpsel q0, q1, q2451; CHECK-NEXT: bx lr452entry:453 %i = insertelement <2 x i64> undef, i64 %src2, i32 0454 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer455 %c = icmp eq <2 x i64> %src, %sp456 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b457 ret <2 x i64> %s458}459 460define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) {461; CHECK-LABEL: vcmp_eq_v2i32:462; CHECK: @ %bb.0: @ %entry463; CHECK-NEXT: vmov r2, r3, d0464; CHECK-NEXT: eors r3, r1465; CHECK-NEXT: eors r2, r0466; CHECK-NEXT: orrs r2, r3467; CHECK-NEXT: mov.w r3, #0468; CHECK-NEXT: csetm r2, eq469; CHECK-NEXT: bfi r3, r2, #0, #8470; CHECK-NEXT: vmov r12, r2, d1471; CHECK-NEXT: eors r1, r2472; CHECK-NEXT: eor.w r0, r0, r12473; CHECK-NEXT: orrs r0, r1474; CHECK-NEXT: csetm r0, eq475; CHECK-NEXT: bfi r3, r0, #8, #8476; CHECK-NEXT: vmsr p0, r3477; CHECK-NEXT: vpsel q0, q1, q2478; CHECK-NEXT: bx lr479entry:480 %i = insertelement <2 x i64> undef, i64 %src2, i32 0481 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer482 %c = icmp eq <2 x i64> %src, %sp483 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b484 ret <2 x i32> %s485}486 487define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {488; CHECK-LABEL: vcmp_multi_v2i32:489; CHECK: @ %bb.0:490; CHECK-NEXT: vmov r0, r1, d0491; CHECK-NEXT: movs r2, #0492; CHECK-NEXT: orrs r0, r1493; CHECK-NEXT: csetm r1, eq494; CHECK-NEXT: movs r0, #0495; CHECK-NEXT: bfi r2, r1, #0, #8496; CHECK-NEXT: vmov r1, r3, d1497; CHECK-NEXT: vmov.i32 q0, #0x0498; CHECK-NEXT: orrs r1, r3499; CHECK-NEXT: csetm r1, eq500; CHECK-NEXT: bfi r2, r1, #8, #8501; CHECK-NEXT: vmsr p0, r2502; CHECK-NEXT: vmov r2, s4503; CHECK-NEXT: vpsel q0, q0, q2504; CHECK-NEXT: vmov r1, s0505; CHECK-NEXT: cmp r2, #0506; CHECK-NEXT: cset r2, ne507; CHECK-NEXT: cmp r1, #0508; CHECK-NEXT: csel r12, zr, r2, eq509; CHECK-NEXT: vmov r2, s8510; CHECK-NEXT: asrs r3, r1, #31511; CHECK-NEXT: subs r1, r1, r2512; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31513; CHECK-NEXT: vmov r2, s6514; CHECK-NEXT: csel r1, zr, r12, ge515; CHECK-NEXT: rsbs r1, r1, #0516; CHECK-NEXT: bfi r0, r1, #0, #8517; CHECK-NEXT: vmov r1, s2518; CHECK-NEXT: cmp r2, #0519; CHECK-NEXT: cset r2, ne520; CHECK-NEXT: cmp r1, #0521; CHECK-NEXT: csel r12, zr, r2, eq522; CHECK-NEXT: vmov r2, s10523; CHECK-NEXT: asrs r3, r1, #31524; CHECK-NEXT: subs r1, r1, r2525; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31526; CHECK-NEXT: csel r1, zr, r12, ge527; CHECK-NEXT: rsbs r1, r1, #0528; CHECK-NEXT: bfi r0, r1, #8, #8529; CHECK-NEXT: vmsr p0, r0530; CHECK-NEXT: vpsel q0, q2, q0531; CHECK-NEXT: bx lr532 %a4 = icmp eq <2 x i64> %a, zeroinitializer533 %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c534 %a6 = icmp ne <2 x i32> %b, zeroinitializer535 %a7 = icmp slt <2 x i32> %a5, %c536 %a8 = icmp ne <2 x i32> %a5, zeroinitializer537 %a9 = and <2 x i1> %a6, %a8538 %a10 = and <2 x i1> %a7, %a9539 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5540 ret <2 x i32> %a11541}542 543; Reversed544 545define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {546; CHECK-LABEL: vcmp_r_eq_v4i32:547; CHECK: @ %bb.0: @ %entry548; CHECK-NEXT: vcmp.i32 eq, q0, r0549; CHECK-NEXT: vpsel q0, q1, q2550; CHECK-NEXT: bx lr551entry:552 %i = insertelement <4 x i32> undef, i32 %src2, i32 0553 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer554 %c = icmp eq <4 x i32> %sp, %src555 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b556 ret <4 x i32> %s557}558 559define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {560; CHECK-LABEL: vcmp_r_ne_v4i32:561; CHECK: @ %bb.0: @ %entry562; CHECK-NEXT: vcmp.i32 ne, q0, r0563; CHECK-NEXT: vpsel q0, q1, q2564; CHECK-NEXT: bx lr565entry:566 %i = insertelement <4 x i32> undef, i32 %src2, i32 0567 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer568 %c = icmp ne <4 x i32> %sp, %src569 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b570 ret <4 x i32> %s571}572 573define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {574; CHECK-LABEL: vcmp_r_sgt_v4i32:575; CHECK: @ %bb.0: @ %entry576; CHECK-NEXT: vcmp.s32 lt, q0, r0577; CHECK-NEXT: vpsel q0, q1, q2578; CHECK-NEXT: bx lr579entry:580 %i = insertelement <4 x i32> undef, i32 %src2, i32 0581 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer582 %c = icmp sgt <4 x i32> %sp, %src583 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b584 ret <4 x i32> %s585}586 587define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {588; CHECK-LABEL: vcmp_r_sge_v4i32:589; CHECK: @ %bb.0: @ %entry590; CHECK-NEXT: vcmp.s32 le, q0, r0591; CHECK-NEXT: vpsel q0, q1, q2592; CHECK-NEXT: bx lr593entry:594 %i = insertelement <4 x i32> undef, i32 %src2, i32 0595 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer596 %c = icmp sge <4 x i32> %sp, %src597 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b598 ret <4 x i32> %s599}600 601define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {602; CHECK-LABEL: vcmp_r_slt_v4i32:603; CHECK: @ %bb.0: @ %entry604; CHECK-NEXT: vcmp.s32 gt, q0, r0605; CHECK-NEXT: vpsel q0, q1, q2606; CHECK-NEXT: bx lr607entry:608 %i = insertelement <4 x i32> undef, i32 %src2, i32 0609 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer610 %c = icmp slt <4 x i32> %sp, %src611 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b612 ret <4 x i32> %s613}614 615define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {616; CHECK-LABEL: vcmp_r_sle_v4i32:617; CHECK: @ %bb.0: @ %entry618; CHECK-NEXT: vcmp.s32 ge, q0, r0619; CHECK-NEXT: vpsel q0, q1, q2620; CHECK-NEXT: bx lr621entry:622 %i = insertelement <4 x i32> undef, i32 %src2, i32 0623 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer624 %c = icmp sle <4 x i32> %sp, %src625 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b626 ret <4 x i32> %s627}628 629define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {630; CHECK-LABEL: vcmp_r_ugt_v4i32:631; CHECK: @ %bb.0: @ %entry632; CHECK-NEXT: vdup.32 q3, r0633; CHECK-NEXT: vcmp.u32 hi, q3, q0634; CHECK-NEXT: vpsel q0, q1, q2635; CHECK-NEXT: bx lr636entry:637 %i = insertelement <4 x i32> undef, i32 %src2, i32 0638 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer639 %c = icmp ugt <4 x i32> %sp, %src640 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b641 ret <4 x i32> %s642}643 644define arm_aapcs_vfpcc <4 x i32> @vcmp_r_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {645; CHECK-LABEL: vcmp_r_uge_v4i32:646; CHECK: @ %bb.0: @ %entry647; CHECK-NEXT: vdup.32 q3, r0648; CHECK-NEXT: vcmp.u32 cs, q3, q0649; CHECK-NEXT: vpsel q0, q1, q2650; CHECK-NEXT: bx lr651entry:652 %i = insertelement <4 x i32> undef, i32 %src2, i32 0653 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer654 %c = icmp uge <4 x i32> %sp, %src655 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b656 ret <4 x i32> %s657}658 659define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {660; CHECK-LABEL: vcmp_r_ult_v4i32:661; CHECK: @ %bb.0: @ %entry662; CHECK-NEXT: vcmp.u32 hi, q0, r0663; CHECK-NEXT: vpsel q0, q1, q2664; CHECK-NEXT: bx lr665entry:666 %i = insertelement <4 x i32> undef, i32 %src2, i32 0667 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer668 %c = icmp ult <4 x i32> %sp, %src669 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b670 ret <4 x i32> %s671}672 673define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {674; CHECK-LABEL: vcmp_r_ule_v4i32:675; CHECK: @ %bb.0: @ %entry676; CHECK-NEXT: vcmp.u32 cs, q0, r0677; CHECK-NEXT: vpsel q0, q1, q2678; CHECK-NEXT: bx lr679entry:680 %i = insertelement <4 x i32> undef, i32 %src2, i32 0681 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer682 %c = icmp ule <4 x i32> %sp, %src683 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b684 ret <4 x i32> %s685}686 687 688define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {689; CHECK-LABEL: vcmp_r_eq_v8i16:690; CHECK: @ %bb.0: @ %entry691; CHECK-NEXT: vcmp.i16 eq, q0, r0692; CHECK-NEXT: vpsel q0, q1, q2693; CHECK-NEXT: bx lr694entry:695 %i = insertelement <8 x i16> undef, i16 %src2, i32 0696 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer697 %c = icmp eq <8 x i16> %sp, %src698 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b699 ret <8 x i16> %s700}701 702define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {703; CHECK-LABEL: vcmp_r_ne_v8i16:704; CHECK: @ %bb.0: @ %entry705; CHECK-NEXT: vcmp.i16 ne, q0, r0706; CHECK-NEXT: vpsel q0, q1, q2707; CHECK-NEXT: bx lr708entry:709 %i = insertelement <8 x i16> undef, i16 %src2, i32 0710 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer711 %c = icmp ne <8 x i16> %sp, %src712 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b713 ret <8 x i16> %s714}715 716define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {717; CHECK-LABEL: vcmp_r_sgt_v8i16:718; CHECK: @ %bb.0: @ %entry719; CHECK-NEXT: vcmp.s16 lt, q0, r0720; CHECK-NEXT: vpsel q0, q1, q2721; CHECK-NEXT: bx lr722entry:723 %i = insertelement <8 x i16> undef, i16 %src2, i32 0724 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer725 %c = icmp sgt <8 x i16> %sp, %src726 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b727 ret <8 x i16> %s728}729 730define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {731; CHECK-LABEL: vcmp_r_sge_v8i16:732; CHECK: @ %bb.0: @ %entry733; CHECK-NEXT: vcmp.s16 le, q0, r0734; CHECK-NEXT: vpsel q0, q1, q2735; CHECK-NEXT: bx lr736entry:737 %i = insertelement <8 x i16> undef, i16 %src2, i32 0738 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer739 %c = icmp sge <8 x i16> %sp, %src740 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b741 ret <8 x i16> %s742}743 744define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {745; CHECK-LABEL: vcmp_r_slt_v8i16:746; CHECK: @ %bb.0: @ %entry747; CHECK-NEXT: vcmp.s16 gt, q0, r0748; CHECK-NEXT: vpsel q0, q1, q2749; CHECK-NEXT: bx lr750entry:751 %i = insertelement <8 x i16> undef, i16 %src2, i32 0752 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer753 %c = icmp slt <8 x i16> %sp, %src754 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b755 ret <8 x i16> %s756}757 758define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {759; CHECK-LABEL: vcmp_r_sle_v8i16:760; CHECK: @ %bb.0: @ %entry761; CHECK-NEXT: vcmp.s16 ge, q0, r0762; CHECK-NEXT: vpsel q0, q1, q2763; CHECK-NEXT: bx lr764entry:765 %i = insertelement <8 x i16> undef, i16 %src2, i32 0766 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer767 %c = icmp sle <8 x i16> %sp, %src768 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b769 ret <8 x i16> %s770}771 772define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {773; CHECK-LABEL: vcmp_r_ugt_v8i16:774; CHECK: @ %bb.0: @ %entry775; CHECK-NEXT: vdup.16 q3, r0776; CHECK-NEXT: vcmp.u16 hi, q3, q0777; CHECK-NEXT: vpsel q0, q1, q2778; CHECK-NEXT: bx lr779entry:780 %i = insertelement <8 x i16> undef, i16 %src2, i32 0781 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer782 %c = icmp ugt <8 x i16> %sp, %src783 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b784 ret <8 x i16> %s785}786 787define arm_aapcs_vfpcc <8 x i16> @vcmp_r_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {788; CHECK-LABEL: vcmp_r_uge_v8i16:789; CHECK: @ %bb.0: @ %entry790; CHECK-NEXT: vdup.16 q3, r0791; CHECK-NEXT: vcmp.u16 cs, q3, q0792; CHECK-NEXT: vpsel q0, q1, q2793; CHECK-NEXT: bx lr794entry:795 %i = insertelement <8 x i16> undef, i16 %src2, i32 0796 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer797 %c = icmp uge <8 x i16> %sp, %src798 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b799 ret <8 x i16> %s800}801 802define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {803; CHECK-LABEL: vcmp_r_ult_v8i16:804; CHECK: @ %bb.0: @ %entry805; CHECK-NEXT: vcmp.u16 hi, q0, r0806; CHECK-NEXT: vpsel q0, q1, q2807; CHECK-NEXT: bx lr808entry:809 %i = insertelement <8 x i16> undef, i16 %src2, i32 0810 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer811 %c = icmp ult <8 x i16> %sp, %src812 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b813 ret <8 x i16> %s814}815 816define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {817; CHECK-LABEL: vcmp_r_ule_v8i16:818; CHECK: @ %bb.0: @ %entry819; CHECK-NEXT: vcmp.u16 cs, q0, r0820; CHECK-NEXT: vpsel q0, q1, q2821; CHECK-NEXT: bx lr822entry:823 %i = insertelement <8 x i16> undef, i16 %src2, i32 0824 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer825 %c = icmp ule <8 x i16> %sp, %src826 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b827 ret <8 x i16> %s828}829 830 831define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {832; CHECK-LABEL: vcmp_r_eq_v16i8:833; CHECK: @ %bb.0: @ %entry834; CHECK-NEXT: vcmp.i8 eq, q0, r0835; CHECK-NEXT: vpsel q0, q1, q2836; CHECK-NEXT: bx lr837entry:838 %i = insertelement <16 x i8> undef, i8 %src2, i32 0839 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer840 %c = icmp eq <16 x i8> %sp, %src841 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b842 ret <16 x i8> %s843}844 845define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {846; CHECK-LABEL: vcmp_r_ne_v16i8:847; CHECK: @ %bb.0: @ %entry848; CHECK-NEXT: vcmp.i8 ne, q0, r0849; CHECK-NEXT: vpsel q0, q1, q2850; CHECK-NEXT: bx lr851entry:852 %i = insertelement <16 x i8> undef, i8 %src2, i32 0853 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer854 %c = icmp ne <16 x i8> %sp, %src855 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b856 ret <16 x i8> %s857}858 859define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {860; CHECK-LABEL: vcmp_r_sgt_v16i8:861; CHECK: @ %bb.0: @ %entry862; CHECK-NEXT: vcmp.s8 lt, q0, r0863; CHECK-NEXT: vpsel q0, q1, q2864; CHECK-NEXT: bx lr865entry:866 %i = insertelement <16 x i8> undef, i8 %src2, i32 0867 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer868 %c = icmp sgt <16 x i8> %sp, %src869 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b870 ret <16 x i8> %s871}872 873define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {874; CHECK-LABEL: vcmp_r_sge_v16i8:875; CHECK: @ %bb.0: @ %entry876; CHECK-NEXT: vcmp.s8 le, q0, r0877; CHECK-NEXT: vpsel q0, q1, q2878; CHECK-NEXT: bx lr879entry:880 %i = insertelement <16 x i8> undef, i8 %src2, i32 0881 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer882 %c = icmp sge <16 x i8> %sp, %src883 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b884 ret <16 x i8> %s885}886 887define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {888; CHECK-LABEL: vcmp_r_slt_v16i8:889; CHECK: @ %bb.0: @ %entry890; CHECK-NEXT: vcmp.s8 gt, q0, r0891; CHECK-NEXT: vpsel q0, q1, q2892; CHECK-NEXT: bx lr893entry:894 %i = insertelement <16 x i8> undef, i8 %src2, i32 0895 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer896 %c = icmp slt <16 x i8> %sp, %src897 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b898 ret <16 x i8> %s899}900 901define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {902; CHECK-LABEL: vcmp_r_sle_v16i8:903; CHECK: @ %bb.0: @ %entry904; CHECK-NEXT: vcmp.s8 ge, q0, r0905; CHECK-NEXT: vpsel q0, q1, q2906; CHECK-NEXT: bx lr907entry:908 %i = insertelement <16 x i8> undef, i8 %src2, i32 0909 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer910 %c = icmp sle <16 x i8> %sp, %src911 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b912 ret <16 x i8> %s913}914 915define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {916; CHECK-LABEL: vcmp_r_ugt_v16i8:917; CHECK: @ %bb.0: @ %entry918; CHECK-NEXT: vdup.8 q3, r0919; CHECK-NEXT: vcmp.u8 hi, q3, q0920; CHECK-NEXT: vpsel q0, q1, q2921; CHECK-NEXT: bx lr922entry:923 %i = insertelement <16 x i8> undef, i8 %src2, i32 0924 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer925 %c = icmp ugt <16 x i8> %sp, %src926 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b927 ret <16 x i8> %s928}929 930define arm_aapcs_vfpcc <16 x i8> @vcmp_r_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {931; CHECK-LABEL: vcmp_r_uge_v16i8:932; CHECK: @ %bb.0: @ %entry933; CHECK-NEXT: vdup.8 q3, r0934; CHECK-NEXT: vcmp.u8 cs, q3, q0935; CHECK-NEXT: vpsel q0, q1, q2936; CHECK-NEXT: bx lr937entry:938 %i = insertelement <16 x i8> undef, i8 %src2, i32 0939 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer940 %c = icmp uge <16 x i8> %sp, %src941 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b942 ret <16 x i8> %s943}944 945define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {946; CHECK-LABEL: vcmp_r_ult_v16i8:947; CHECK: @ %bb.0: @ %entry948; CHECK-NEXT: vcmp.u8 hi, q0, r0949; CHECK-NEXT: vpsel q0, q1, q2950; CHECK-NEXT: bx lr951entry:952 %i = insertelement <16 x i8> undef, i8 %src2, i32 0953 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer954 %c = icmp ult <16 x i8> %sp, %src955 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b956 ret <16 x i8> %s957}958 959define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {960; CHECK-LABEL: vcmp_r_ule_v16i8:961; CHECK: @ %bb.0: @ %entry962; CHECK-NEXT: vcmp.u8 cs, q0, r0963; CHECK-NEXT: vpsel q0, q1, q2964; CHECK-NEXT: bx lr965entry:966 %i = insertelement <16 x i8> undef, i8 %src2, i32 0967 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer968 %c = icmp ule <16 x i8> %sp, %src969 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b970 ret <16 x i8> %s971}972 973 974define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) {975; CHECK-LABEL: vcmp_r_eq_v2i64:976; CHECK: @ %bb.0: @ %entry977; CHECK-NEXT: vmov r2, r3, d0978; CHECK-NEXT: eors r3, r1979; CHECK-NEXT: eors r2, r0980; CHECK-NEXT: orrs r2, r3981; CHECK-NEXT: mov.w r3, #0982; CHECK-NEXT: csetm r2, eq983; CHECK-NEXT: bfi r3, r2, #0, #8984; CHECK-NEXT: vmov r12, r2, d1985; CHECK-NEXT: eors r1, r2986; CHECK-NEXT: eor.w r0, r0, r12987; CHECK-NEXT: orrs r0, r1988; CHECK-NEXT: csetm r0, eq989; CHECK-NEXT: bfi r3, r0, #8, #8990; CHECK-NEXT: vmsr p0, r3991; CHECK-NEXT: vpsel q0, q1, q2992; CHECK-NEXT: bx lr993entry:994 %i = insertelement <2 x i64> undef, i64 %src2, i32 0995 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer996 %c = icmp eq <2 x i64> %sp, %src997 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b998 ret <2 x i64> %s999}1000 1001define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) {1002; CHECK-LABEL: vcmp_r_eq_v2i32:1003; CHECK: @ %bb.0: @ %entry1004; CHECK-NEXT: vmov r2, r3, d01005; CHECK-NEXT: eors r3, r11006; CHECK-NEXT: eors r2, r01007; CHECK-NEXT: orrs r2, r31008; CHECK-NEXT: mov.w r3, #01009; CHECK-NEXT: csetm r2, eq1010; CHECK-NEXT: bfi r3, r2, #0, #81011; CHECK-NEXT: vmov r12, r2, d11012; CHECK-NEXT: eors r1, r21013; CHECK-NEXT: eor.w r0, r0, r121014; CHECK-NEXT: orrs r0, r11015; CHECK-NEXT: csetm r0, eq1016; CHECK-NEXT: bfi r3, r0, #8, #81017; CHECK-NEXT: vmsr p0, r31018; CHECK-NEXT: vpsel q0, q1, q21019; CHECK-NEXT: bx lr1020entry:1021 %i = insertelement <2 x i64> undef, i64 %src2, i32 01022 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer1023 %c = icmp eq <2 x i64> %sp, %src1024 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b1025 ret <2 x i32> %s1026}1027 1028define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {1029; CHECK-LABEL: vcmp_r_multi_v2i32:1030; CHECK: @ %bb.0:1031; CHECK-NEXT: vmov r0, r1, d01032; CHECK-NEXT: movs r2, #01033; CHECK-NEXT: orrs r0, r11034; CHECK-NEXT: csetm r1, eq1035; CHECK-NEXT: movs r0, #01036; CHECK-NEXT: bfi r2, r1, #0, #81037; CHECK-NEXT: vmov r1, r3, d11038; CHECK-NEXT: vmov.i32 q0, #0x01039; CHECK-NEXT: orrs r1, r31040; CHECK-NEXT: csetm r1, eq1041; CHECK-NEXT: bfi r2, r1, #8, #81042; CHECK-NEXT: vmsr p0, r21043; CHECK-NEXT: vmov r2, s41044; CHECK-NEXT: vpsel q0, q0, q21045; CHECK-NEXT: vmov r1, s01046; CHECK-NEXT: cmp r2, #01047; CHECK-NEXT: cset r2, ne1048; CHECK-NEXT: cmp r1, #01049; CHECK-NEXT: csel r12, zr, r2, eq1050; CHECK-NEXT: vmov r2, s81051; CHECK-NEXT: asrs r3, r1, #311052; CHECK-NEXT: subs r1, r1, r21053; CHECK-NEXT: sbcs.w r1, r3, r2, asr #311054; CHECK-NEXT: vmov r2, s61055; CHECK-NEXT: csel r1, zr, r12, ge1056; CHECK-NEXT: rsbs r1, r1, #01057; CHECK-NEXT: bfi r0, r1, #0, #81058; CHECK-NEXT: vmov r1, s21059; CHECK-NEXT: cmp r2, #01060; CHECK-NEXT: cset r2, ne1061; CHECK-NEXT: cmp r1, #01062; CHECK-NEXT: csel r12, zr, r2, eq1063; CHECK-NEXT: vmov r2, s101064; CHECK-NEXT: asrs r3, r1, #311065; CHECK-NEXT: subs r1, r1, r21066; CHECK-NEXT: sbcs.w r1, r3, r2, asr #311067; CHECK-NEXT: csel r1, zr, r12, ge1068; CHECK-NEXT: rsbs r1, r1, #01069; CHECK-NEXT: bfi r0, r1, #8, #81070; CHECK-NEXT: vmsr p0, r01071; CHECK-NEXT: vpsel q0, q2, q01072; CHECK-NEXT: bx lr1073 %a4 = icmp eq <2 x i64> %a, zeroinitializer1074 %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c1075 %a6 = icmp ne <2 x i32> %b, zeroinitializer1076 %a7 = icmp slt <2 x i32> %a5, %c1077 %a8 = icmp ne <2 x i32> %a5, zeroinitializer1078 %a9 = and <2 x i1> %a6, %a81079 %a10 = and <2 x i1> %a7, %a91080 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a51081 ret <2 x i32> %a111082}1083