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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcmp_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: vcmp_eqz_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcmp.i32 eq, q0, zr8; CHECK-NEXT: vpsel q0, q1, q29; CHECK-NEXT: bx lr10entry:11 %c = icmp eq <4 x i32> %src, zeroinitializer12 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b13 ret <4 x i32> %s14}15 16define arm_aapcs_vfpcc <4 x i32> @vcmp_nez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {17; CHECK-LABEL: vcmp_nez_v4i32:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vcmp.i32 ne, q0, zr20; CHECK-NEXT: vpsel q0, q1, q221; CHECK-NEXT: bx lr22entry:23 %c = icmp ne <4 x i32> %src, zeroinitializer24 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b25 ret <4 x i32> %s26}27 28define arm_aapcs_vfpcc <4 x i32> @vcmp_sgtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {29; CHECK-LABEL: vcmp_sgtz_v4i32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vcmp.s32 gt, q0, zr32; CHECK-NEXT: vpsel q0, q1, q233; CHECK-NEXT: bx lr34entry:35 %c = icmp sgt <4 x i32> %src, zeroinitializer36 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b37 ret <4 x i32> %s38}39 40define arm_aapcs_vfpcc <4 x i32> @vcmp_sgez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {41; CHECK-LABEL: vcmp_sgez_v4i32:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vcmp.s32 ge, q0, zr44; CHECK-NEXT: vpsel q0, q1, q245; CHECK-NEXT: bx lr46entry:47 %c = icmp sge <4 x i32> %src, zeroinitializer48 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b49 ret <4 x i32> %s50}51 52define arm_aapcs_vfpcc <4 x i32> @vcmp_sltz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {53; CHECK-LABEL: vcmp_sltz_v4i32:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vcmp.s32 lt, q0, zr56; CHECK-NEXT: vpsel q0, q1, q257; CHECK-NEXT: bx lr58entry:59 %c = icmp slt <4 x i32> %src, zeroinitializer60 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b61 ret <4 x i32> %s62}63 64define arm_aapcs_vfpcc <4 x i32> @vcmp_slez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {65; CHECK-LABEL: vcmp_slez_v4i32:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vcmp.s32 le, q0, zr68; CHECK-NEXT: vpsel q0, q1, q269; CHECK-NEXT: bx lr70entry:71 %c = icmp sle <4 x i32> %src, zeroinitializer72 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b73 ret <4 x i32> %s74}75 76define arm_aapcs_vfpcc <4 x i32> @vcmp_ugtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {77; CHECK-LABEL: vcmp_ugtz_v4i32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vcmp.i32 ne, q0, zr80; CHECK-NEXT: vpsel q0, q1, q281; CHECK-NEXT: bx lr82entry:83 %c = icmp ugt <4 x i32> %src, zeroinitializer84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b85 ret <4 x i32> %s86}87 88define arm_aapcs_vfpcc <4 x i32> @vcmp_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {89; CHECK-LABEL: vcmp_ugez_v4i32:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vmov q0, q192; CHECK-NEXT: bx lr93entry:94 %c = icmp uge <4 x i32> %src, zeroinitializer95 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b96 ret <4 x i32> %s97}98 99define arm_aapcs_vfpcc <4 x i32> @vcmp_ultz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {100; CHECK-LABEL: vcmp_ultz_v4i32:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: vmov q0, q2103; CHECK-NEXT: bx lr104entry:105 %c = icmp ult <4 x i32> %src, zeroinitializer106 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b107 ret <4 x i32> %s108}109 110define arm_aapcs_vfpcc <4 x i32> @vcmp_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {111; CHECK-LABEL: vcmp_ulez_v4i32:112; CHECK: @ %bb.0: @ %entry113; CHECK-NEXT: vmov.i32 q3, #0x0114; CHECK-NEXT: vcmp.u32 cs, q3, q0115; CHECK-NEXT: vpsel q0, q1, q2116; CHECK-NEXT: bx lr117entry:118 %c = icmp ule <4 x i32> %src, zeroinitializer119 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b120 ret <4 x i32> %s121}122 123 124define arm_aapcs_vfpcc <8 x i16> @vcmp_eqz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {125; CHECK-LABEL: vcmp_eqz_v8i16:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vcmp.i16 eq, q0, zr128; CHECK-NEXT: vpsel q0, q1, q2129; CHECK-NEXT: bx lr130entry:131 %c = icmp eq <8 x i16> %src, zeroinitializer132 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b133 ret <8 x i16> %s134}135 136define arm_aapcs_vfpcc <8 x i16> @vcmp_nez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {137; CHECK-LABEL: vcmp_nez_v8i16:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vcmp.i16 ne, q0, zr140; CHECK-NEXT: vpsel q0, q1, q2141; CHECK-NEXT: bx lr142entry:143 %c = icmp ne <8 x i16> %src, zeroinitializer144 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b145 ret <8 x i16> %s146}147 148define arm_aapcs_vfpcc <8 x i16> @vcmp_sgtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {149; CHECK-LABEL: vcmp_sgtz_v8i16:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vcmp.s16 gt, q0, zr152; CHECK-NEXT: vpsel q0, q1, q2153; CHECK-NEXT: bx lr154entry:155 %c = icmp sgt <8 x i16> %src, zeroinitializer156 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b157 ret <8 x i16> %s158}159 160define arm_aapcs_vfpcc <8 x i16> @vcmp_sgez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {161; CHECK-LABEL: vcmp_sgez_v8i16:162; CHECK: @ %bb.0: @ %entry163; CHECK-NEXT: vcmp.s16 ge, q0, zr164; CHECK-NEXT: vpsel q0, q1, q2165; CHECK-NEXT: bx lr166entry:167 %c = icmp sge <8 x i16> %src, zeroinitializer168 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b169 ret <8 x i16> %s170}171 172define arm_aapcs_vfpcc <8 x i16> @vcmp_sltz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {173; CHECK-LABEL: vcmp_sltz_v8i16:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vcmp.s16 lt, q0, zr176; CHECK-NEXT: vpsel q0, q1, q2177; CHECK-NEXT: bx lr178entry:179 %c = icmp slt <8 x i16> %src, zeroinitializer180 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b181 ret <8 x i16> %s182}183 184define arm_aapcs_vfpcc <8 x i16> @vcmp_slez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {185; CHECK-LABEL: vcmp_slez_v8i16:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vcmp.s16 le, q0, zr188; CHECK-NEXT: vpsel q0, q1, q2189; CHECK-NEXT: bx lr190entry:191 %c = icmp sle <8 x i16> %src, zeroinitializer192 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b193 ret <8 x i16> %s194}195 196define arm_aapcs_vfpcc <8 x i16> @vcmp_ugtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {197; CHECK-LABEL: vcmp_ugtz_v8i16:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vcmp.i16 ne, q0, zr200; CHECK-NEXT: vpsel q0, q1, q2201; CHECK-NEXT: bx lr202entry:203 %c = icmp ugt <8 x i16> %src, zeroinitializer204 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b205 ret <8 x i16> %s206}207 208define arm_aapcs_vfpcc <8 x i16> @vcmp_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {209; CHECK-LABEL: vcmp_ugez_v8i16:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmov q0, q1212; CHECK-NEXT: bx lr213entry:214 %c = icmp uge <8 x i16> %src, zeroinitializer215 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b216 ret <8 x i16> %s217}218 219define arm_aapcs_vfpcc <8 x i16> @vcmp_ultz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {220; CHECK-LABEL: vcmp_ultz_v8i16:221; CHECK: @ %bb.0: @ %entry222; CHECK-NEXT: vmov q0, q2223; CHECK-NEXT: bx lr224entry:225 %c = icmp ult <8 x i16> %src, zeroinitializer226 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b227 ret <8 x i16> %s228}229 230define arm_aapcs_vfpcc <8 x i16> @vcmp_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {231; CHECK-LABEL: vcmp_ulez_v8i16:232; CHECK: @ %bb.0: @ %entry233; CHECK-NEXT: vmov.i32 q3, #0x0234; CHECK-NEXT: vcmp.u16 cs, q3, q0235; CHECK-NEXT: vpsel q0, q1, q2236; CHECK-NEXT: bx lr237entry:238 %c = icmp ule <8 x i16> %src, zeroinitializer239 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b240 ret <8 x i16> %s241}242 243 244define arm_aapcs_vfpcc <16 x i8> @vcmp_eqz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {245; CHECK-LABEL: vcmp_eqz_v16i8:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vcmp.i8 eq, q0, zr248; CHECK-NEXT: vpsel q0, q1, q2249; CHECK-NEXT: bx lr250entry:251 %c = icmp eq <16 x i8> %src, zeroinitializer252 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b253 ret <16 x i8> %s254}255 256define arm_aapcs_vfpcc <16 x i8> @vcmp_nez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {257; CHECK-LABEL: vcmp_nez_v16i8:258; CHECK: @ %bb.0: @ %entry259; CHECK-NEXT: vcmp.i8 ne, q0, zr260; CHECK-NEXT: vpsel q0, q1, q2261; CHECK-NEXT: bx lr262entry:263 %c = icmp ne <16 x i8> %src, zeroinitializer264 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b265 ret <16 x i8> %s266}267 268define arm_aapcs_vfpcc <16 x i8> @vcmp_sgtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {269; CHECK-LABEL: vcmp_sgtz_v16i8:270; CHECK: @ %bb.0: @ %entry271; CHECK-NEXT: vcmp.s8 gt, q0, zr272; CHECK-NEXT: vpsel q0, q1, q2273; CHECK-NEXT: bx lr274entry:275 %c = icmp sgt <16 x i8> %src, zeroinitializer276 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b277 ret <16 x i8> %s278}279 280define arm_aapcs_vfpcc <16 x i8> @vcmp_sgez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {281; CHECK-LABEL: vcmp_sgez_v16i8:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: vcmp.s8 ge, q0, zr284; CHECK-NEXT: vpsel q0, q1, q2285; CHECK-NEXT: bx lr286entry:287 %c = icmp sge <16 x i8> %src, zeroinitializer288 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b289 ret <16 x i8> %s290}291 292define arm_aapcs_vfpcc <16 x i8> @vcmp_sltz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {293; CHECK-LABEL: vcmp_sltz_v16i8:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vcmp.s8 lt, q0, zr296; CHECK-NEXT: vpsel q0, q1, q2297; CHECK-NEXT: bx lr298entry:299 %c = icmp slt <16 x i8> %src, zeroinitializer300 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b301 ret <16 x i8> %s302}303 304define arm_aapcs_vfpcc <16 x i8> @vcmp_slez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {305; CHECK-LABEL: vcmp_slez_v16i8:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vcmp.s8 le, q0, zr308; CHECK-NEXT: vpsel q0, q1, q2309; CHECK-NEXT: bx lr310entry:311 %c = icmp sle <16 x i8> %src, zeroinitializer312 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b313 ret <16 x i8> %s314}315 316define arm_aapcs_vfpcc <16 x i8> @vcmp_ugtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {317; CHECK-LABEL: vcmp_ugtz_v16i8:318; CHECK: @ %bb.0: @ %entry319; CHECK-NEXT: vcmp.i8 ne, q0, zr320; CHECK-NEXT: vpsel q0, q1, q2321; CHECK-NEXT: bx lr322entry:323 %c = icmp ugt <16 x i8> %src, zeroinitializer324 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b325 ret <16 x i8> %s326}327 328define arm_aapcs_vfpcc <16 x i8> @vcmp_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {329; CHECK-LABEL: vcmp_ugez_v16i8:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vmov q0, q1332; CHECK-NEXT: bx lr333entry:334 %c = icmp uge <16 x i8> %src, zeroinitializer335 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b336 ret <16 x i8> %s337}338 339define arm_aapcs_vfpcc <16 x i8> @vcmp_ultz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {340; CHECK-LABEL: vcmp_ultz_v16i8:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: vmov q0, q2343; CHECK-NEXT: bx lr344entry:345 %c = icmp ult <16 x i8> %src, zeroinitializer346 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b347 ret <16 x i8> %s348}349 350define arm_aapcs_vfpcc <16 x i8> @vcmp_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {351; CHECK-LABEL: vcmp_ulez_v16i8:352; CHECK: @ %bb.0: @ %entry353; CHECK-NEXT: vmov.i32 q3, #0x0354; CHECK-NEXT: vcmp.u8 cs, q3, q0355; CHECK-NEXT: vpsel q0, q1, q2356; CHECK-NEXT: bx lr357entry:358 %c = icmp ule <16 x i8> %src, zeroinitializer359 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b360 ret <16 x i8> %s361}362 363 364define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {365; CHECK-LABEL: vcmp_eqz_v2i64:366; CHECK: @ %bb.0: @ %entry367; CHECK-NEXT: vmov r0, r1, d0368; CHECK-NEXT: orrs r0, r1369; CHECK-NEXT: mov.w r1, #0370; CHECK-NEXT: csetm r0, eq371; CHECK-NEXT: bfi r1, r0, #0, #8372; CHECK-NEXT: vmov r0, r2, d1373; CHECK-NEXT: orrs r0, r2374; CHECK-NEXT: csetm r0, eq375; CHECK-NEXT: bfi r1, r0, #8, #8376; CHECK-NEXT: vmsr p0, r1377; CHECK-NEXT: vpsel q0, q1, q2378; CHECK-NEXT: bx lr379entry:380 %c = icmp eq <2 x i64> %src, zeroinitializer381 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b382 ret <2 x i64> %s383}384 385define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) {386; CHECK-LABEL: vcmp_eqz_v2i32:387; CHECK: @ %bb.0: @ %entry388; CHECK-NEXT: vmov r0, r1, d0389; CHECK-NEXT: orrs r0, r1390; CHECK-NEXT: mov.w r1, #0391; CHECK-NEXT: csetm r0, eq392; CHECK-NEXT: bfi r1, r0, #0, #8393; CHECK-NEXT: vmov r0, r2, d1394; CHECK-NEXT: orrs r0, r2395; CHECK-NEXT: csetm r0, eq396; CHECK-NEXT: bfi r1, r0, #8, #8397; CHECK-NEXT: vmsr p0, r1398; CHECK-NEXT: vpsel q0, q1, q2399; CHECK-NEXT: bx lr400entry:401 %c = icmp eq <2 x i64> %src, zeroinitializer402 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b403 ret <2 x i32> %s404}405 406 407; Reversed408 409define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {410; CHECK-LABEL: vcmp_r_eqz_v4i32:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vcmp.i32 eq, q0, zr413; CHECK-NEXT: vpsel q0, q1, q2414; CHECK-NEXT: bx lr415entry:416 %c = icmp eq <4 x i32> zeroinitializer, %src417 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b418 ret <4 x i32> %s419}420 421define arm_aapcs_vfpcc <4 x i32> @vcmp_r_nez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {422; CHECK-LABEL: vcmp_r_nez_v4i32:423; CHECK: @ %bb.0: @ %entry424; CHECK-NEXT: vcmp.i32 ne, q0, zr425; CHECK-NEXT: vpsel q0, q1, q2426; CHECK-NEXT: bx lr427entry:428 %c = icmp ne <4 x i32> zeroinitializer, %src429 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b430 ret <4 x i32> %s431}432 433define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {434; CHECK-LABEL: vcmp_r_sgtz_v4i32:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: vcmp.s32 lt, q0, zr437; CHECK-NEXT: vpsel q0, q1, q2438; CHECK-NEXT: bx lr439entry:440 %c = icmp sgt <4 x i32> zeroinitializer, %src441 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b442 ret <4 x i32> %s443}444 445define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {446; CHECK-LABEL: vcmp_r_sgez_v4i32:447; CHECK: @ %bb.0: @ %entry448; CHECK-NEXT: vcmp.s32 le, q0, zr449; CHECK-NEXT: vpsel q0, q1, q2450; CHECK-NEXT: bx lr451entry:452 %c = icmp sge <4 x i32> zeroinitializer, %src453 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b454 ret <4 x i32> %s455}456 457define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sltz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {458; CHECK-LABEL: vcmp_r_sltz_v4i32:459; CHECK: @ %bb.0: @ %entry460; CHECK-NEXT: vcmp.s32 gt, q0, zr461; CHECK-NEXT: vpsel q0, q1, q2462; CHECK-NEXT: bx lr463entry:464 %c = icmp slt <4 x i32> zeroinitializer, %src465 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b466 ret <4 x i32> %s467}468 469define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {470; CHECK-LABEL: vcmp_r_slez_v4i32:471; CHECK: @ %bb.0: @ %entry472; CHECK-NEXT: vcmp.s32 ge, q0, zr473; CHECK-NEXT: vpsel q0, q1, q2474; CHECK-NEXT: bx lr475entry:476 %c = icmp sle <4 x i32> zeroinitializer, %src477 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b478 ret <4 x i32> %s479}480 481define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {482; CHECK-LABEL: vcmp_r_ugtz_v4i32:483; CHECK: @ %bb.0: @ %entry484; CHECK-NEXT: vmov q0, q2485; CHECK-NEXT: bx lr486entry:487 %c = icmp ugt <4 x i32> zeroinitializer, %src488 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b489 ret <4 x i32> %s490}491 492define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {493; CHECK-LABEL: vcmp_r_ugez_v4i32:494; CHECK: @ %bb.0: @ %entry495; CHECK-NEXT: vmov.i32 q3, #0x0496; CHECK-NEXT: vcmp.u32 cs, q3, q0497; CHECK-NEXT: vpsel q0, q1, q2498; CHECK-NEXT: bx lr499entry:500 %c = icmp uge <4 x i32> zeroinitializer, %src501 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b502 ret <4 x i32> %s503}504 505define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ultz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {506; CHECK-LABEL: vcmp_r_ultz_v4i32:507; CHECK: @ %bb.0: @ %entry508; CHECK-NEXT: vcmp.i32 ne, q0, zr509; CHECK-NEXT: vpsel q0, q1, q2510; CHECK-NEXT: bx lr511entry:512 %c = icmp ult <4 x i32> zeroinitializer, %src513 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b514 ret <4 x i32> %s515}516 517define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {518; CHECK-LABEL: vcmp_r_ulez_v4i32:519; CHECK: @ %bb.0: @ %entry520; CHECK-NEXT: vmov q0, q1521; CHECK-NEXT: bx lr522entry:523 %c = icmp ule <4 x i32> zeroinitializer, %src524 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b525 ret <4 x i32> %s526}527 528 529define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eqz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {530; CHECK-LABEL: vcmp_r_eqz_v8i16:531; CHECK: @ %bb.0: @ %entry532; CHECK-NEXT: vcmp.i16 eq, q0, zr533; CHECK-NEXT: vpsel q0, q1, q2534; CHECK-NEXT: bx lr535entry:536 %c = icmp eq <8 x i16> zeroinitializer, %src537 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b538 ret <8 x i16> %s539}540 541define arm_aapcs_vfpcc <8 x i16> @vcmp_r_nez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {542; CHECK-LABEL: vcmp_r_nez_v8i16:543; CHECK: @ %bb.0: @ %entry544; CHECK-NEXT: vcmp.i16 ne, q0, zr545; CHECK-NEXT: vpsel q0, q1, q2546; CHECK-NEXT: bx lr547entry:548 %c = icmp ne <8 x i16> zeroinitializer, %src549 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b550 ret <8 x i16> %s551}552 553define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {554; CHECK-LABEL: vcmp_r_sgtz_v8i16:555; CHECK: @ %bb.0: @ %entry556; CHECK-NEXT: vcmp.s16 lt, q0, zr557; CHECK-NEXT: vpsel q0, q1, q2558; CHECK-NEXT: bx lr559entry:560 %c = icmp sgt <8 x i16> zeroinitializer, %src561 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b562 ret <8 x i16> %s563}564 565define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {566; CHECK-LABEL: vcmp_r_sgez_v8i16:567; CHECK: @ %bb.0: @ %entry568; CHECK-NEXT: vcmp.s16 le, q0, zr569; CHECK-NEXT: vpsel q0, q1, q2570; CHECK-NEXT: bx lr571entry:572 %c = icmp sge <8 x i16> zeroinitializer, %src573 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b574 ret <8 x i16> %s575}576 577define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sltz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {578; CHECK-LABEL: vcmp_r_sltz_v8i16:579; CHECK: @ %bb.0: @ %entry580; CHECK-NEXT: vcmp.s16 gt, q0, zr581; CHECK-NEXT: vpsel q0, q1, q2582; CHECK-NEXT: bx lr583entry:584 %c = icmp slt <8 x i16> zeroinitializer, %src585 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b586 ret <8 x i16> %s587}588 589define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {590; CHECK-LABEL: vcmp_r_slez_v8i16:591; CHECK: @ %bb.0: @ %entry592; CHECK-NEXT: vcmp.s16 ge, q0, zr593; CHECK-NEXT: vpsel q0, q1, q2594; CHECK-NEXT: bx lr595entry:596 %c = icmp sle <8 x i16> zeroinitializer, %src597 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b598 ret <8 x i16> %s599}600 601define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {602; CHECK-LABEL: vcmp_r_ugtz_v8i16:603; CHECK: @ %bb.0: @ %entry604; CHECK-NEXT: vmov q0, q2605; CHECK-NEXT: bx lr606entry:607 %c = icmp ugt <8 x i16> zeroinitializer, %src608 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b609 ret <8 x i16> %s610}611 612define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {613; CHECK-LABEL: vcmp_r_ugez_v8i16:614; CHECK: @ %bb.0: @ %entry615; CHECK-NEXT: vmov.i32 q3, #0x0616; CHECK-NEXT: vcmp.u16 cs, q3, q0617; CHECK-NEXT: vpsel q0, q1, q2618; CHECK-NEXT: bx lr619entry:620 %c = icmp uge <8 x i16> zeroinitializer, %src621 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b622 ret <8 x i16> %s623}624 625define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ultz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {626; CHECK-LABEL: vcmp_r_ultz_v8i16:627; CHECK: @ %bb.0: @ %entry628; CHECK-NEXT: vcmp.i16 ne, q0, zr629; CHECK-NEXT: vpsel q0, q1, q2630; CHECK-NEXT: bx lr631entry:632 %c = icmp ult <8 x i16> zeroinitializer, %src633 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b634 ret <8 x i16> %s635}636 637define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {638; CHECK-LABEL: vcmp_r_ulez_v8i16:639; CHECK: @ %bb.0: @ %entry640; CHECK-NEXT: vmov q0, q1641; CHECK-NEXT: bx lr642entry:643 %c = icmp ule <8 x i16> zeroinitializer, %src644 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b645 ret <8 x i16> %s646}647 648 649define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eqz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {650; CHECK-LABEL: vcmp_r_eqz_v16i8:651; CHECK: @ %bb.0: @ %entry652; CHECK-NEXT: vcmp.i8 eq, q0, zr653; CHECK-NEXT: vpsel q0, q1, q2654; CHECK-NEXT: bx lr655entry:656 %c = icmp eq <16 x i8> zeroinitializer, %src657 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b658 ret <16 x i8> %s659}660 661define arm_aapcs_vfpcc <16 x i8> @vcmp_r_nez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {662; CHECK-LABEL: vcmp_r_nez_v16i8:663; CHECK: @ %bb.0: @ %entry664; CHECK-NEXT: vcmp.i8 ne, q0, zr665; CHECK-NEXT: vpsel q0, q1, q2666; CHECK-NEXT: bx lr667entry:668 %c = icmp ne <16 x i8> zeroinitializer, %src669 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b670 ret <16 x i8> %s671}672 673define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {674; CHECK-LABEL: vcmp_r_sgtz_v16i8:675; CHECK: @ %bb.0: @ %entry676; CHECK-NEXT: vcmp.s8 lt, q0, zr677; CHECK-NEXT: vpsel q0, q1, q2678; CHECK-NEXT: bx lr679entry:680 %c = icmp sgt <16 x i8> zeroinitializer, %src681 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b682 ret <16 x i8> %s683}684 685define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {686; CHECK-LABEL: vcmp_r_sgez_v16i8:687; CHECK: @ %bb.0: @ %entry688; CHECK-NEXT: vcmp.s8 le, q0, zr689; CHECK-NEXT: vpsel q0, q1, q2690; CHECK-NEXT: bx lr691entry:692 %c = icmp sge <16 x i8> zeroinitializer, %src693 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b694 ret <16 x i8> %s695}696 697define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sltz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {698; CHECK-LABEL: vcmp_r_sltz_v16i8:699; CHECK: @ %bb.0: @ %entry700; CHECK-NEXT: vcmp.s8 gt, q0, zr701; CHECK-NEXT: vpsel q0, q1, q2702; CHECK-NEXT: bx lr703entry:704 %c = icmp slt <16 x i8> zeroinitializer, %src705 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b706 ret <16 x i8> %s707}708 709define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {710; CHECK-LABEL: vcmp_r_slez_v16i8:711; CHECK: @ %bb.0: @ %entry712; CHECK-NEXT: vcmp.s8 ge, q0, zr713; CHECK-NEXT: vpsel q0, q1, q2714; CHECK-NEXT: bx lr715entry:716 %c = icmp sle <16 x i8> zeroinitializer, %src717 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b718 ret <16 x i8> %s719}720 721define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {722; CHECK-LABEL: vcmp_r_ugtz_v16i8:723; CHECK: @ %bb.0: @ %entry724; CHECK-NEXT: vmov q0, q2725; CHECK-NEXT: bx lr726entry:727 %c = icmp ugt <16 x i8> zeroinitializer, %src728 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b729 ret <16 x i8> %s730}731 732define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {733; CHECK-LABEL: vcmp_r_ugez_v16i8:734; CHECK: @ %bb.0: @ %entry735; CHECK-NEXT: vmov.i32 q3, #0x0736; CHECK-NEXT: vcmp.u8 cs, q3, q0737; CHECK-NEXT: vpsel q0, q1, q2738; CHECK-NEXT: bx lr739entry:740 %c = icmp uge <16 x i8> zeroinitializer, %src741 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b742 ret <16 x i8> %s743}744 745define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ultz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {746; CHECK-LABEL: vcmp_r_ultz_v16i8:747; CHECK: @ %bb.0: @ %entry748; CHECK-NEXT: vcmp.i8 ne, q0, zr749; CHECK-NEXT: vpsel q0, q1, q2750; CHECK-NEXT: bx lr751entry:752 %c = icmp ult <16 x i8> zeroinitializer, %src753 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b754 ret <16 x i8> %s755}756 757define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {758; CHECK-LABEL: vcmp_r_ulez_v16i8:759; CHECK: @ %bb.0: @ %entry760; CHECK-NEXT: vmov q0, q1761; CHECK-NEXT: bx lr762entry:763 %c = icmp ule <16 x i8> zeroinitializer, %src764 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b765 ret <16 x i8> %s766}767 768 769define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {770; CHECK-LABEL: vcmp_r_eqz_v2i64:771; CHECK: @ %bb.0: @ %entry772; CHECK-NEXT: vmov r0, r1, d0773; CHECK-NEXT: orrs r0, r1774; CHECK-NEXT: mov.w r1, #0775; CHECK-NEXT: csetm r0, eq776; CHECK-NEXT: bfi r1, r0, #0, #8777; CHECK-NEXT: vmov r0, r2, d1778; CHECK-NEXT: orrs r0, r2779; CHECK-NEXT: csetm r0, eq780; CHECK-NEXT: bfi r1, r0, #8, #8781; CHECK-NEXT: vmsr p0, r1782; CHECK-NEXT: vpsel q0, q1, q2783; CHECK-NEXT: bx lr784entry:785 %c = icmp eq <2 x i64> zeroinitializer, %src786 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b787 ret <2 x i64> %s788}789 790define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) {791; CHECK-LABEL: vcmp_r_eqz_v2i32:792; CHECK: @ %bb.0: @ %entry793; CHECK-NEXT: vmov r0, r1, d0794; CHECK-NEXT: orrs r0, r1795; CHECK-NEXT: mov.w r1, #0796; CHECK-NEXT: csetm r0, eq797; CHECK-NEXT: bfi r1, r0, #0, #8798; CHECK-NEXT: vmov r0, r2, d1799; CHECK-NEXT: orrs r0, r2800; CHECK-NEXT: csetm r0, eq801; CHECK-NEXT: bfi r1, r0, #8, #8802; CHECK-NEXT: vmsr p0, r1803; CHECK-NEXT: vpsel q0, q1, q2804; CHECK-NEXT: bx lr805entry:806 %c = icmp eq <2 x i64> %src, zeroinitializer807 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b808 ret <2 x i32> %s809}810