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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcreate_i32(i32 %a, i32 %b, i32 %c, i32 %d) {5; CHECK-LABEL: vcreate_i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmov q0[2], q0[0], r1, r38; CHECK-NEXT: vmov q0[3], q0[1], r0, r29; CHECK-NEXT: bx lr10entry:11 %conv = zext i32 %a to i6412 %shl = shl nuw i64 %conv, 3213 %conv1 = zext i32 %b to i6414 %or = or i64 %shl, %conv115 %0 = insertelement <2 x i64> undef, i64 %or, i64 016 %conv2 = zext i32 %c to i6417 %shl3 = shl nuw i64 %conv2, 3218 %conv4 = zext i32 %d to i6419 %or5 = or i64 %shl3, %conv420 %1 = insertelement <2 x i64> %0, i64 %or5, i64 121 %2 = bitcast <2 x i64> %1 to <4 x i32>22 ret <4 x i32> %223}24 25define arm_aapcs_vfpcc <4 x i32> @insert_0123(i32 %a, i32 %b, i32 %c, i32 %d) {26; CHECK-LABEL: insert_0123:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: vmov q0[2], q0[0], r0, r229; CHECK-NEXT: vmov q0[3], q0[1], r1, r330; CHECK-NEXT: bx lr31entry:32 %v1 = insertelement <4 x i32> undef, i32 %a, i32 033 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 134 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 235 %v4 = insertelement <4 x i32> %v3, i32 %d, i32 336 ret <4 x i32> %v437}38 39define arm_aapcs_vfpcc <4 x i32> @insert_3210(i32 %a, i32 %b, i32 %c, i32 %d) {40; CHECK-LABEL: insert_3210:41; CHECK: @ %bb.0: @ %entry42; CHECK-NEXT: vmov q0[2], q0[0], r3, r143; CHECK-NEXT: vmov q0[3], q0[1], r2, r044; CHECK-NEXT: bx lr45entry:46 %v1 = insertelement <4 x i32> undef, i32 %a, i32 347 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 248 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 149 %v4 = insertelement <4 x i32> %v3, i32 %d, i32 050 ret <4 x i32> %v451}52 53define arm_aapcs_vfpcc <4 x i32> @insert_0213(i32 %a, i32 %b, i32 %c, i32 %d) {54; CHECK-LABEL: insert_0213:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vmov q0[2], q0[0], r0, r157; CHECK-NEXT: vmov q0[3], q0[1], r2, r358; CHECK-NEXT: bx lr59entry:60 %v1 = insertelement <4 x i32> undef, i32 %a, i32 061 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 262 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 163 %v4 = insertelement <4 x i32> %v3, i32 %d, i32 364 ret <4 x i32> %v465}66 67define arm_aapcs_vfpcc <4 x i32> @insert_0220(i32 %a, i32 %b, i32 %c, i32 %d) {68; CHECK-LABEL: insert_0220:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: vmov q0[2], q0[0], r3, r271; CHECK-NEXT: bx lr72entry:73 %v1 = insertelement <4 x i32> undef, i32 %a, i32 074 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 275 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 276 %v4 = insertelement <4 x i32> %v3, i32 %d, i32 077 ret <4 x i32> %v478}79 80define arm_aapcs_vfpcc <4 x i32> @insert_321(i32 %a, i32 %b, i32 %c, i32 %d) {81; CHECK-LABEL: insert_321:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vmov.32 q0[2], r184; CHECK-NEXT: vmov q0[3], q0[1], r2, r085; CHECK-NEXT: bx lr86entry:87 %v1 = insertelement <4 x i32> undef, i32 %a, i32 388 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 289 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 190 ret <4 x i32> %v391}92 93define arm_aapcs_vfpcc <4 x i32> @insert_310(i32 %a, i32 %b, i32 %c, i32 %d) {94; CHECK-LABEL: insert_310:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: vmov.32 q0[0], r297; CHECK-NEXT: vmov q0[3], q0[1], r1, r098; CHECK-NEXT: bx lr99entry:100 %v1 = insertelement <4 x i32> undef, i32 %a, i32 3101 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 1102 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 0103 ret <4 x i32> %v3104}105 106define arm_aapcs_vfpcc <4 x i32> @insert_320(i32 %a, i32 %b, i32 %c, i32 %d) {107; CHECK-LABEL: insert_320:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmov q0[2], q0[0], r2, r1110; CHECK-NEXT: vmov.32 q0[3], r0111; CHECK-NEXT: bx lr112entry:113 %v1 = insertelement <4 x i32> undef, i32 %a, i32 3114 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 2115 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 0116 ret <4 x i32> %v3117}118 119define arm_aapcs_vfpcc <4 x i32> @insert_31(i32 %a, i32 %b, i32 %c, i32 %d) {120; CHECK-LABEL: insert_31:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmov q0[3], q0[1], r1, r0123; CHECK-NEXT: bx lr124entry:125 %v1 = insertelement <4 x i32> undef, i32 %a, i32 3126 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 1127 ret <4 x i32> %v2128}129 130define arm_aapcs_vfpcc <4 x i32> @insert_32(i32 %a, i32 %b, i32 %c, i32 %d) {131; CHECK-LABEL: insert_32:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmov.32 q0[2], r1134; CHECK-NEXT: vmov.32 q0[3], r0135; CHECK-NEXT: bx lr136entry:137 %v1 = insertelement <4 x i32> undef, i32 %a, i32 3138 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 2139 ret <4 x i32> %v2140}141 142define arm_aapcs_vfpcc <4 x i32> @insert_3(i32 %a, i32 %b, i32 %c, i32 %d) {143; CHECK-LABEL: insert_3:144; CHECK: @ %bb.0: @ %entry145; CHECK-NEXT: vmov.32 q0[3], r0146; CHECK-NEXT: bx lr147entry:148 %v1 = insertelement <4 x i32> undef, i32 %a, i32 3149 ret <4 x i32> %v1150}151 152define arm_aapcs_vfpcc <4 x i32> @insert_210(i32 %a, i32 %b, i32 %c, i32 %d) {153; CHECK-LABEL: insert_210:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmov.32 q0[1], r1156; CHECK-NEXT: vmov q0[2], q0[0], r2, r0157; CHECK-NEXT: bx lr158entry:159 %v1 = insertelement <4 x i32> undef, i32 %a, i32 2160 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 1161 %v3 = insertelement <4 x i32> %v2, i32 %c, i32 0162 ret <4 x i32> %v3163}164 165define arm_aapcs_vfpcc <4 x i32> @insert_20(i32 %a, i32 %b, i32 %c, i32 %d) {166; CHECK-LABEL: insert_20:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmov q0[2], q0[0], r1, r0169; CHECK-NEXT: bx lr170entry:171 %v1 = insertelement <4 x i32> undef, i32 %a, i32 2172 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 0173 ret <4 x i32> %v2174}175 176define arm_aapcs_vfpcc <4 x i32> @insert_21(i32 %a, i32 %b, i32 %c, i32 %d) {177; CHECK-LABEL: insert_21:178; CHECK: @ %bb.0: @ %entry179; CHECK-NEXT: vmov.32 q0[1], r1180; CHECK-NEXT: vmov.32 q0[2], r0181; CHECK-NEXT: bx lr182entry:183 %v1 = insertelement <4 x i32> undef, i32 %a, i32 2184 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 1185 ret <4 x i32> %v2186}187 188define arm_aapcs_vfpcc <4 x i32> @insert_2(i32 %a, i32 %b, i32 %c, i32 %d) {189; CHECK-LABEL: insert_2:190; CHECK: @ %bb.0: @ %entry191; CHECK-NEXT: vmov.32 q0[2], r0192; CHECK-NEXT: bx lr193entry:194 %v1 = insertelement <4 x i32> undef, i32 %a, i32 2195 ret <4 x i32> %v1196}197 198define arm_aapcs_vfpcc <4 x i32> @insert_10(i32 %a, i32 %b, i32 %c, i32 %d) {199; CHECK-LABEL: insert_10:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vmov.32 q0[0], r1202; CHECK-NEXT: vmov.32 q0[1], r0203; CHECK-NEXT: bx lr204entry:205 %v1 = insertelement <4 x i32> undef, i32 %a, i32 1206 %v2 = insertelement <4 x i32> %v1, i32 %b, i32 0207 ret <4 x i32> %v2208}209 210define arm_aapcs_vfpcc <4 x i32> @insert_1(i32 %a, i32 %b, i32 %c, i32 %d) {211; CHECK-LABEL: insert_1:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: vmov.32 q0[1], r0214; CHECK-NEXT: bx lr215entry:216 %v1 = insertelement <4 x i32> undef, i32 %a, i32 1217 ret <4 x i32> %v1218}219 220define arm_aapcs_vfpcc <4 x i32> @insert_0(i32 %a, i32 %b, i32 %c, i32 %d) {221; CHECK-LABEL: insert_0:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmov.32 q0[0], r0224; CHECK-NEXT: bx lr225entry:226 %v1 = insertelement <4 x i32> undef, i32 %a, i32 0227 ret <4 x i32> %v1228}229 230define hidden <8 x i16> @create_i16(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d, i16 zeroext %a2, i16 zeroext %b2, i16 zeroext %c2, i16 zeroext %d2) local_unnamed_addr #0 {231; CHECK-LABEL: create_i16:232; CHECK: @ %bb.0: @ %entry233; CHECK-NEXT: .save {r4, r5, r7, lr}234; CHECK-NEXT: push {r4, r5, r7, lr}235; CHECK-NEXT: movs r7, #0236; CHECK-NEXT: orr.w r0, r1, r0, lsl #16237; CHECK-NEXT: lsll r2, r7, #16238; CHECK-NEXT: ldr r4, [sp, #24]239; CHECK-NEXT: orr.w r1, r0, r7240; CHECK-NEXT: ldrd r0, r7, [sp, #16]241; CHECK-NEXT: movs r5, #0242; CHECK-NEXT: lsll r4, r5, #16243; CHECK-NEXT: orr.w r0, r7, r0, lsl #16244; CHECK-NEXT: orr.w r12, r0, r5245; CHECK-NEXT: orr.w r0, r2, r3246; CHECK-NEXT: ldr r2, [sp, #28]247; CHECK-NEXT: mov r3, r12248; CHECK-NEXT: orrs r2, r4249; CHECK-NEXT: pop {r4, r5, r7, pc}250entry:251 %conv = zext i16 %a to i64252 %shl = shl nuw i64 %conv, 48253 %conv1 = zext i16 %b to i64254 %shl2 = shl nuw nsw i64 %conv1, 32255 %or = or i64 %shl2, %shl256 %conv3 = zext i16 %c to i64257 %shl4 = shl nuw nsw i64 %conv3, 16258 %or5 = or i64 %or, %shl4259 %conv6 = zext i16 %d to i64260 %or7 = or i64 %or5, %conv6261 %0 = insertelement <2 x i64> undef, i64 %or7, i64 0262 %conv8 = zext i16 %a2 to i64263 %shl9 = shl nuw i64 %conv8, 48264 %conv10 = zext i16 %b2 to i64265 %shl11 = shl nuw nsw i64 %conv10, 32266 %or12 = or i64 %shl11, %shl9267 %conv13 = zext i16 %c2 to i64268 %shl14 = shl nuw nsw i64 %conv13, 16269 %or15 = or i64 %or12, %shl14270 %conv16 = zext i16 %d2 to i64271 %or17 = or i64 %or15, %conv16272 %1 = insertelement <2 x i64> %0, i64 %or17, i64 1273 %2 = bitcast <2 x i64> %1 to <8 x i16>274 ret <8 x i16> %2275}276 277define arm_aapcs_vfpcc <8 x i16> @insert_01234567(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) {278; CHECK-LABEL: insert_01234567:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vmov.16 q0[0], r0281; CHECK-NEXT: ldrh.w r0, [sp]282; CHECK-NEXT: vmov.16 q0[1], r1283; CHECK-NEXT: vmov.16 q0[2], r2284; CHECK-NEXT: vmov.16 q0[3], r3285; CHECK-NEXT: vmov.16 q0[4], r0286; CHECK-NEXT: ldrh.w r0, [sp, #4]287; CHECK-NEXT: vmov.16 q0[5], r0288; CHECK-NEXT: ldrh.w r0, [sp, #8]289; CHECK-NEXT: vmov.16 q0[6], r0290; CHECK-NEXT: ldrh.w r0, [sp, #12]291; CHECK-NEXT: vmov.16 q0[7], r0292; CHECK-NEXT: bx lr293entry:294 %v1 = insertelement <8 x i16> undef, i16 %a0, i32 0295 %v2 = insertelement <8 x i16> %v1, i16 %a1, i32 1296 %v3 = insertelement <8 x i16> %v2, i16 %a2, i32 2297 %v4 = insertelement <8 x i16> %v3, i16 %a3, i32 3298 %v5 = insertelement <8 x i16> %v4, i16 %a4, i32 4299 %v6 = insertelement <8 x i16> %v5, i16 %a5, i32 5300 %v7 = insertelement <8 x i16> %v6, i16 %a6, i32 6301 %v8 = insertelement <8 x i16> %v7, i16 %a7, i32 7302 ret <8 x i16> %v8303}304 305define hidden <16 x i8> @create_i8(i8 zeroext %a1, i8 zeroext %b1, i8 zeroext %c1, i8 zeroext %d1, i8 zeroext %a2, i8 zeroext %b2, i8 zeroext %c2, i8 zeroext %d2, i8 zeroext %a3, i8 zeroext %b3, i8 zeroext %c3, i8 zeroext %d3, i8 zeroext %a4, i8 zeroext %b4, i8 zeroext %c4, i8 zeroext %d4) local_unnamed_addr #0 {306; CHECK-LABEL: create_i8:307; CHECK: @ %bb.0: @ %entry308; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}309; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}310; CHECK-NEXT: ldr r4, [sp, #40]311; CHECK-NEXT: mov.w r11, #0312; CHECK-NEXT: ldr r6, [sp, #36]313; CHECK-NEXT: movs r7, #0314; CHECK-NEXT: lsll r4, r11, #16315; CHECK-NEXT: mov r10, r1316; CHECK-NEXT: lsll r6, r7, #24317; CHECK-NEXT: mov r8, r3318; CHECK-NEXT: orr.w r1, r6, r4319; CHECK-NEXT: ldr r6, [sp, #44]320; CHECK-NEXT: movs r3, #0321; CHECK-NEXT: ldr r4, [sp, #72]322; CHECK-NEXT: lsll r6, r3, #8323; CHECK-NEXT: movs r5, #0324; CHECK-NEXT: orrs r1, r6325; CHECK-NEXT: ldr r6, [sp, #48]326; CHECK-NEXT: lsll r4, r5, #16327; CHECK-NEXT: mov.w r9, #0328; CHECK-NEXT: orr.w r12, r1, r6329; CHECK-NEXT: ldr r6, [sp, #68]330; CHECK-NEXT: movs r1, #0331; CHECK-NEXT: lsll r6, r1, #24332; CHECK-NEXT: orrs r6, r4333; CHECK-NEXT: ldr r4, [sp, #76]334; CHECK-NEXT: lsll r4, r9, #8335; CHECK-NEXT: orrs r6, r4336; CHECK-NEXT: ldr r4, [sp, #80]337; CHECK-NEXT: orr.w lr, r6, r4338; CHECK-NEXT: lsl.w r4, r10, #16339; CHECK-NEXT: orr.w r0, r4, r0, lsl #22340; CHECK-NEXT: orr.w r0, r0, r2, lsl #8341; CHECK-NEXT: add r0, r8342; CHECK-NEXT: orrs r0, r7343; CHECK-NEXT: orr.w r0, r0, r11344; CHECK-NEXT: orr.w r2, r0, r3345; CHECK-NEXT: ldr r0, [sp, #56]346; CHECK-NEXT: ldr r3, [sp, #52]347; CHECK-NEXT: lsls r0, r0, #16348; CHECK-NEXT: orr.w r0, r0, r3, lsl #22349; CHECK-NEXT: ldr r3, [sp, #60]350; CHECK-NEXT: orr.w r0, r0, r3, lsl #8351; CHECK-NEXT: ldr r3, [sp, #64]352; CHECK-NEXT: add r0, r3353; CHECK-NEXT: orrs r0, r1354; CHECK-NEXT: mov r1, r2355; CHECK-NEXT: orrs r0, r5356; CHECK-NEXT: mov r2, lr357; CHECK-NEXT: orr.w r3, r0, r9358; CHECK-NEXT: mov r0, r12359; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}360entry:361 %conv = zext i8 %a1 to i64362 %shl = shl nuw nsw i64 %conv, 54363 %conv1 = zext i8 %b1 to i64364 %shl2 = shl nuw nsw i64 %conv1, 48365 %or = or i64 %shl2, %shl366 %conv3 = zext i8 %c1 to i64367 %shl4 = shl nuw nsw i64 %conv3, 40368 %or5 = or i64 %or, %shl4369 %conv6 = zext i8 %d1 to i64370 %shl7 = shl nuw nsw i64 %conv6, 32371 %or8 = or i64 %or5, %shl7372 %conv9 = zext i8 %a2 to i64373 %shl10 = shl nuw nsw i64 %conv9, 24374 %or11 = or i64 %or8, %shl10375 %conv12 = zext i8 %b2 to i64376 %shl13 = shl nuw nsw i64 %conv12, 16377 %or14 = or i64 %or11, %shl13378 %conv15 = zext i8 %c2 to i64379 %shl16 = shl nuw nsw i64 %conv15, 8380 %or17 = or i64 %or14, %shl16381 %conv18 = zext i8 %d2 to i64382 %or19 = or i64 %or17, %conv18383 %0 = insertelement <2 x i64> undef, i64 %or19, i64 0384 %conv20 = zext i8 %a3 to i64385 %shl21 = shl nuw nsw i64 %conv20, 54386 %conv22 = zext i8 %b3 to i64387 %shl23 = shl nuw nsw i64 %conv22, 48388 %or24 = or i64 %shl23, %shl21389 %conv25 = zext i8 %c3 to i64390 %shl26 = shl nuw nsw i64 %conv25, 40391 %or27 = or i64 %or24, %shl26392 %conv28 = zext i8 %d3 to i64393 %shl29 = shl nuw nsw i64 %conv28, 32394 %or30 = or i64 %or27, %shl29395 %conv31 = zext i8 %a4 to i64396 %shl32 = shl nuw nsw i64 %conv31, 24397 %or33 = or i64 %or30, %shl32398 %conv34 = zext i8 %b4 to i64399 %shl35 = shl nuw nsw i64 %conv34, 16400 %or36 = or i64 %or33, %shl35401 %conv37 = zext i8 %c4 to i64402 %shl38 = shl nuw nsw i64 %conv37, 8403 %or39 = or i64 %or36, %shl38404 %conv40 = zext i8 %d4 to i64405 %or41 = or i64 %or39, %conv40406 %1 = insertelement <2 x i64> %0, i64 %or41, i64 1407 %2 = bitcast <2 x i64> %1 to <16 x i8>408 ret <16 x i8> %2409}410 411define arm_aapcs_vfpcc <16 x i8> @insert_0123456789101112131415(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) {412; CHECK-LABEL: insert_0123456789101112131415:413; CHECK: @ %bb.0: @ %entry414; CHECK-NEXT: vmov.8 q0[0], r0415; CHECK-NEXT: ldrb.w r0, [sp]416; CHECK-NEXT: vmov.8 q0[1], r1417; CHECK-NEXT: vmov.8 q0[2], r2418; CHECK-NEXT: vmov.8 q0[3], r3419; CHECK-NEXT: vmov.8 q0[4], r0420; CHECK-NEXT: ldrb.w r0, [sp, #4]421; CHECK-NEXT: vmov.8 q0[5], r0422; CHECK-NEXT: ldrb.w r0, [sp, #8]423; CHECK-NEXT: vmov.8 q0[6], r0424; CHECK-NEXT: ldrb.w r0, [sp, #12]425; CHECK-NEXT: vmov.8 q0[7], r0426; CHECK-NEXT: ldrb.w r0, [sp, #16]427; CHECK-NEXT: vmov.8 q0[8], r0428; CHECK-NEXT: ldrb.w r0, [sp, #20]429; CHECK-NEXT: vmov.8 q0[9], r0430; CHECK-NEXT: ldrb.w r0, [sp, #24]431; CHECK-NEXT: vmov.8 q0[10], r0432; CHECK-NEXT: ldrb.w r0, [sp, #28]433; CHECK-NEXT: vmov.8 q0[11], r0434; CHECK-NEXT: ldrb.w r0, [sp, #32]435; CHECK-NEXT: vmov.8 q0[12], r0436; CHECK-NEXT: ldrb.w r0, [sp, #36]437; CHECK-NEXT: vmov.8 q0[13], r0438; CHECK-NEXT: ldrb.w r0, [sp, #40]439; CHECK-NEXT: vmov.8 q0[14], r0440; CHECK-NEXT: ldrb.w r0, [sp, #44]441; CHECK-NEXT: vmov.8 q0[15], r0442; CHECK-NEXT: bx lr443entry:444 %v1 = insertelement <16 x i8> undef, i8 %a0, i32 0445 %v2 = insertelement <16 x i8> %v1, i8 %a1, i32 1446 %v3 = insertelement <16 x i8> %v2, i8 %a2, i32 2447 %v4 = insertelement <16 x i8> %v3, i8 %a3, i32 3448 %v5 = insertelement <16 x i8> %v4, i8 %a4, i32 4449 %v6 = insertelement <16 x i8> %v5, i8 %a5, i32 5450 %v7 = insertelement <16 x i8> %v6, i8 %a6, i32 6451 %v8 = insertelement <16 x i8> %v7, i8 %a7, i32 7452 %v9 = insertelement <16 x i8> %v8, i8 %a8, i32 8453 %v10 = insertelement <16 x i8> %v9, i8 %a9, i32 9454 %v11 = insertelement <16 x i8> %v10, i8 %a10, i32 10455 %v12 = insertelement <16 x i8> %v11, i8 %a11, i32 11456 %v13 = insertelement <16 x i8> %v12, i8 %a12, i32 12457 %v14 = insertelement <16 x i8> %v13, i8 %a13, i32 13458 %v15 = insertelement <16 x i8> %v14, i8 %a14, i32 14459 %v16 = insertelement <16 x i8> %v15, i8 %a15, i32 15460 ret <16 x i8> %v16461}462