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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s3 4define void @vctp8(i32 %arg, ptr %in, ptr %out) {5; CHECK-LABEL: vctp8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldrw.u32 q1, [r1]8; CHECK-NEXT: vctp.8 r09; CHECK-NEXT: vmov.i32 q0, #0x010; CHECK-NEXT: vpst11; CHECK-NEXT: vmovt q0, q112; CHECK-NEXT: vstrw.32 q0, [r2]13; CHECK-NEXT: bx lr14 %pred = call <16 x i1> @llvm.arm.mve.vctp8(i32 %arg)15 %ld = load <16 x i8>, ptr %in16 %res = select <16 x i1> %pred, <16 x i8> %ld, <16 x i8> zeroinitializer17 store <16 x i8> %res, ptr %out18 ret void19}20 21define void @vctp16(i32 %arg, ptr %in, ptr %out) {22; CHECK-LABEL: vctp16:23; CHECK: @ %bb.0:24; CHECK-NEXT: vldrw.u32 q1, [r1]25; CHECK-NEXT: vctp.16 r026; CHECK-NEXT: vmov.i32 q0, #0x027; CHECK-NEXT: vpst28; CHECK-NEXT: vmovt q0, q129; CHECK-NEXT: vstrw.32 q0, [r2]30; CHECK-NEXT: bx lr31 %pred = call <8 x i1> @llvm.arm.mve.vctp16(i32 %arg)32 %ld = load <8 x i16>, ptr %in33 %res = select <8 x i1> %pred, <8 x i16> %ld, <8 x i16> zeroinitializer34 store <8 x i16> %res, ptr %out35 ret void36}37 38define void @vctp32(i32 %arg, ptr %in, ptr %out) {39; CHECK-LABEL: vctp32:40; CHECK: @ %bb.0:41; CHECK-NEXT: vldrw.u32 q1, [r1]42; CHECK-NEXT: vctp.32 r043; CHECK-NEXT: vmov.i32 q0, #0x044; CHECK-NEXT: vpst45; CHECK-NEXT: vmovt q0, q146; CHECK-NEXT: vstrw.32 q0, [r2]47; CHECK-NEXT: bx lr48 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %arg)49 %ld = load <4 x i32>, ptr %in50 %res = select <4 x i1> %pred, <4 x i32> %ld, <4 x i32> zeroinitializer51 store <4 x i32> %res, ptr %out52 ret void53}54 55define void @vctp64(i32 %arg, ptr %in, ptr %out) {56; CHECK-LABEL: vctp64:57; CHECK: @ %bb.0:58; CHECK-NEXT: vldrw.u32 q1, [r1]59; CHECK-NEXT: vctp.64 r060; CHECK-NEXT: vmov.i32 q0, #0x061; CHECK-NEXT: vpst62; CHECK-NEXT: vmovt q0, q163; CHECK-NEXT: vstrw.32 q0, [r2]64; CHECK-NEXT: bx lr65 %pred = call <2 x i1> @llvm.arm.mve.vctp64(i32 %arg)66 %ld = load <2 x i64>, ptr %in67 %res = select <2 x i1> %pred, <2 x i64> %ld, <2 x i64> zeroinitializer68 store <2 x i64> %res, ptr %out69 ret void70}71 72define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(i32 %n, <4 x i32> %a, <4 x i32> %b) {73; CHECK-LABEL: vcmp_ult_v4i32:74; CHECK: @ %bb.0: @ %entry75; CHECK-NEXT: vctp.32 r076; CHECK-NEXT: vpst77; CHECK-NEXT: vmovt q1, q078; CHECK-NEXT: vmov q0, q179; CHECK-NEXT: bx lr80entry:81 %i = insertelement <4 x i32> undef, i32 %n, i32 082 %ns = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer83 %c = icmp ult <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %ns84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b85 ret <4 x i32> %s86}87 88define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(i32 %n, <4 x i32> %a, <4 x i32> %b) {89; CHECK-LABEL: vcmp_uge_v4i32:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vctp.32 r092; CHECK-NEXT: vpst93; CHECK-NEXT: vmovt q1, q094; CHECK-NEXT: vmov q0, q195; CHECK-NEXT: bx lr96entry:97 %i = insertelement <4 x i32> undef, i32 %n, i32 098 %ns = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer99 %c = icmp uge <4 x i32> %ns, <i32 0, i32 1, i32 2, i32 3>100 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b101 ret <4 x i32> %s102}103 104define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32_undef(i32 %n, <4 x i32> %a, <4 x i32> %b) {105; CHECK-LABEL: vcmp_ult_v4i32_undef:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vctp.32 r0108; CHECK-NEXT: vpst109; CHECK-NEXT: vmovt q1, q0110; CHECK-NEXT: vmov q0, q1111; CHECK-NEXT: bx lr112entry:113 %i = insertelement <4 x i32> undef, i32 %n, i32 0114 %ns = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer115 %c = icmp ult <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>, %ns116 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b117 ret <4 x i32> %s118}119 120 121define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(i16 %n, <8 x i16> %a, <8 x i16> %b) {122; CHECK-LABEL: vcmp_ult_v8i16:123; CHECK: @ %bb.0: @ %entry124; CHECK-NEXT: uxth r0, r0125; CHECK-NEXT: vctp.16 r0126; CHECK-NEXT: vpst127; CHECK-NEXT: vmovt q1, q0128; CHECK-NEXT: vmov q0, q1129; CHECK-NEXT: bx lr130entry:131 %i = insertelement <8 x i16> undef, i16 %n, i32 0132 %ns = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer133 %c = icmp ult <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, %ns134 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b135 ret <8 x i16> %s136}137 138define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(i16 %n, <8 x i16> %a, <8 x i16> %b) {139; CHECK-LABEL: vcmp_uge_v8i16:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: uxth r0, r0142; CHECK-NEXT: vctp.16 r0143; CHECK-NEXT: vpst144; CHECK-NEXT: vmovt q1, q0145; CHECK-NEXT: vmov q0, q1146; CHECK-NEXT: bx lr147entry:148 %i = insertelement <8 x i16> undef, i16 %n, i32 0149 %ns = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer150 %c = icmp uge <8 x i16> %ns, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>151 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b152 ret <8 x i16> %s153}154 155 156define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(i8 %n, <16 x i8> %a, <16 x i8> %b) {157; CHECK-LABEL: vcmp_ult_v16i8:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: uxtb r0, r0160; CHECK-NEXT: vctp.8 r0161; CHECK-NEXT: vpst162; CHECK-NEXT: vmovt q1, q0163; CHECK-NEXT: vmov q0, q1164; CHECK-NEXT: bx lr165entry:166 %i = insertelement <16 x i8> undef, i8 %n, i32 0167 %ns = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer168 %c = icmp ult <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, %ns169 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b170 ret <16 x i8> %s171}172 173define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(i8 %n, <16 x i8> %a, <16 x i8> %b) {174; CHECK-LABEL: vcmp_uge_v16i8:175; CHECK: @ %bb.0: @ %entry176; CHECK-NEXT: uxtb r0, r0177; CHECK-NEXT: vctp.8 r0178; CHECK-NEXT: vpst179; CHECK-NEXT: vmovt q1, q0180; CHECK-NEXT: vmov q0, q1181; CHECK-NEXT: bx lr182entry:183 %i = insertelement <16 x i8> undef, i8 %n, i32 0184 %ns = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer185 %c = icmp uge <16 x i8> %ns, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>186 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b187 ret <16 x i8> %s188}189 190 191define arm_aapcs_vfpcc <2 x i64> @vcmp_ult_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {192; CHECK-LABEL: vcmp_ult_v2i64:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vctp.64 r0195; CHECK-NEXT: vpst196; CHECK-NEXT: vmovt q1, q0197; CHECK-NEXT: vmov q0, q1198; CHECK-NEXT: bx lr199entry:200 %i = insertelement <2 x i64> undef, i64 %n, i32 0201 %ns = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer202 %c = icmp ult <2 x i64> <i64 0, i64 1>, %ns203 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b204 ret <2 x i64> %s205}206 207define arm_aapcs_vfpcc <2 x i64> @vcmp_uge_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {208; CHECK-LABEL: vcmp_uge_v2i64:209; CHECK: @ %bb.0: @ %entry210; CHECK-NEXT: vctp.64 r0211; CHECK-NEXT: vpst212; CHECK-NEXT: vmovt q1, q0213; CHECK-NEXT: vmov q0, q1214; CHECK-NEXT: bx lr215entry:216 %i = insertelement <2 x i64> undef, i64 %n, i32 0217 %ns = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer218 %c = icmp uge <2 x i64> %ns, <i64 0, i64 1>219 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b220 ret <2 x i64> %s221}222 223 224declare <16 x i1> @llvm.arm.mve.vctp8(i32)225declare <8 x i1> @llvm.arm.mve.vctp16(i32)226declare <4 x i1> @llvm.arm.mve.vctp32(i32)227declare <2 x i1> @llvm.arm.mve.vctp64(i32)228