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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - -mattr=+mve.fp | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_1(<4 x float> %0) {5; CHECK-LABEL: vcvt_i32_1:6; CHECK: @ %bb.0:7; CHECK-NEXT: vcvt.s32.f32 q0, q0, #18; CHECK-NEXT: bx lr9 %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>10 %3 = fptosi <4 x float> %2 to <4 x i32>11 ret <4 x i32> %312}13 14define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_2(<4 x float> %0) {15; CHECK-LABEL: vcvt_i32_2:16; CHECK: @ %bb.0:17; CHECK-NEXT: vcvt.s32.f32 q0, q0, #218; CHECK-NEXT: bx lr19 %2 = fmul fast <4 x float> %0, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>20 %3 = fptosi <4 x float> %2 to <4 x i32>21 ret <4 x i32> %322}23 24define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_3(<4 x float> %0) {25; CHECK-LABEL: vcvt_i32_3:26; CHECK: @ %bb.0:27; CHECK-NEXT: vcvt.s32.f32 q0, q0, #328; CHECK-NEXT: bx lr29 %2 = fmul fast <4 x float> %0, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>30 %3 = fptosi <4 x float> %2 to <4 x i32>31 ret <4 x i32> %332}33 34define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_4(<4 x float> %0) {35; CHECK-LABEL: vcvt_i32_4:36; CHECK: @ %bb.0:37; CHECK-NEXT: vcvt.s32.f32 q0, q0, #438; CHECK-NEXT: bx lr39 %2 = fmul fast <4 x float> %0, <float 1.600000e+01, float 1.600000e+01, float 1.600000e+01, float 1.600000e+01>40 %3 = fptosi <4 x float> %2 to <4 x i32>41 ret <4 x i32> %342}43 44define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_5(<4 x float> %0) {45; CHECK-LABEL: vcvt_i32_5:46; CHECK: @ %bb.0:47; CHECK-NEXT: vcvt.s32.f32 q0, q0, #548; CHECK-NEXT: bx lr49 %2 = fmul fast <4 x float> %0, <float 3.200000e+01, float 3.200000e+01, float 3.200000e+01, float 3.200000e+01>50 %3 = fptosi <4 x float> %2 to <4 x i32>51 ret <4 x i32> %352}53 54define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_6(<4 x float> %0) {55; CHECK-LABEL: vcvt_i32_6:56; CHECK: @ %bb.0:57; CHECK-NEXT: vcvt.s32.f32 q0, q0, #658; CHECK-NEXT: bx lr59 %2 = fmul fast <4 x float> %0, <float 6.400000e+01, float 6.400000e+01, float 6.400000e+01, float 6.400000e+01>60 %3 = fptosi <4 x float> %2 to <4 x i32>61 ret <4 x i32> %362}63 64define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_7(<4 x float> %0) {65; CHECK-LABEL: vcvt_i32_7:66; CHECK: @ %bb.0:67; CHECK-NEXT: vcvt.s32.f32 q0, q0, #768; CHECK-NEXT: bx lr69 %2 = fmul fast <4 x float> %0, <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>70 %3 = fptosi <4 x float> %2 to <4 x i32>71 ret <4 x i32> %372}73 74define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_8(<4 x float> %0) {75; CHECK-LABEL: vcvt_i32_8:76; CHECK: @ %bb.0:77; CHECK-NEXT: vcvt.s32.f32 q0, q0, #878; CHECK-NEXT: bx lr79 %2 = fmul fast <4 x float> %0, <float 2.560000e+02, float 2.560000e+02, float 2.560000e+02, float 2.560000e+02>80 %3 = fptosi <4 x float> %2 to <4 x i32>81 ret <4 x i32> %382}83 84define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_9(<4 x float> %0) {85; CHECK-LABEL: vcvt_i32_9:86; CHECK: @ %bb.0:87; CHECK-NEXT: vcvt.s32.f32 q0, q0, #988; CHECK-NEXT: bx lr89 %2 = fmul fast <4 x float> %0, <float 5.120000e+02, float 5.120000e+02, float 5.120000e+02, float 5.120000e+02>90 %3 = fptosi <4 x float> %2 to <4 x i32>91 ret <4 x i32> %392}93 94define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_10(<4 x float> %0) {95; CHECK-LABEL: vcvt_i32_10:96; CHECK: @ %bb.0:97; CHECK-NEXT: vcvt.s32.f32 q0, q0, #1098; CHECK-NEXT: bx lr99 %2 = fmul fast <4 x float> %0, <float 1.024000e+03, float 1.024000e+03, float 1.024000e+03, float 1.024000e+03>100 %3 = fptosi <4 x float> %2 to <4 x i32>101 ret <4 x i32> %3102}103 104define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_11(<4 x float> %0) {105; CHECK-LABEL: vcvt_i32_11:106; CHECK: @ %bb.0:107; CHECK-NEXT: vcvt.s32.f32 q0, q0, #11108; CHECK-NEXT: bx lr109 %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>110 %3 = fptosi <4 x float> %2 to <4 x i32>111 ret <4 x i32> %3112}113 114define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_12(<4 x float> %0) {115; CHECK-LABEL: vcvt_i32_12:116; CHECK: @ %bb.0:117; CHECK-NEXT: vcvt.s32.f32 q0, q0, #12118; CHECK-NEXT: bx lr119 %2 = fmul fast <4 x float> %0, <float 4.096000e+03, float 4.096000e+03, float 4.096000e+03, float 4.096000e+03>120 %3 = fptosi <4 x float> %2 to <4 x i32>121 ret <4 x i32> %3122}123 124define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_13(<4 x float> %0) {125; CHECK-LABEL: vcvt_i32_13:126; CHECK: @ %bb.0:127; CHECK-NEXT: vcvt.s32.f32 q0, q0, #13128; CHECK-NEXT: bx lr129 %2 = fmul fast <4 x float> %0, <float 8.192000e+03, float 8.192000e+03, float 8.192000e+03, float 8.192000e+03>130 %3 = fptosi <4 x float> %2 to <4 x i32>131 ret <4 x i32> %3132}133 134define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_14(<4 x float> %0) {135; CHECK-LABEL: vcvt_i32_14:136; CHECK: @ %bb.0:137; CHECK-NEXT: vcvt.s32.f32 q0, q0, #14138; CHECK-NEXT: bx lr139 %2 = fmul fast <4 x float> %0, <float 1.638400e+04, float 1.638400e+04, float 1.638400e+04, float 1.638400e+04>140 %3 = fptosi <4 x float> %2 to <4 x i32>141 ret <4 x i32> %3142}143 144define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_15(<4 x float> %0) {145; CHECK-LABEL: vcvt_i32_15:146; CHECK: @ %bb.0:147; CHECK-NEXT: vcvt.s32.f32 q0, q0, #15148; CHECK-NEXT: bx lr149 %2 = fmul fast <4 x float> %0, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>150 %3 = fptosi <4 x float> %2 to <4 x i32>151 ret <4 x i32> %3152}153 154define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_16(<4 x float> %0) {155; CHECK-LABEL: vcvt_i32_16:156; CHECK: @ %bb.0:157; CHECK-NEXT: vcvt.s32.f32 q0, q0, #16158; CHECK-NEXT: bx lr159 %2 = fmul fast <4 x float> %0, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>160 %3 = fptosi <4 x float> %2 to <4 x i32>161 ret <4 x i32> %3162}163 164define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_17(<4 x float> %0) {165; CHECK-LABEL: vcvt_i32_17:166; CHECK: @ %bb.0:167; CHECK-NEXT: vcvt.s32.f32 q0, q0, #17168; CHECK-NEXT: bx lr169 %2 = fmul fast <4 x float> %0, <float 1.310720e+05, float 1.310720e+05, float 1.310720e+05, float 1.310720e+05>170 %3 = fptosi <4 x float> %2 to <4 x i32>171 ret <4 x i32> %3172}173 174define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_18(<4 x float> %0) {175; CHECK-LABEL: vcvt_i32_18:176; CHECK: @ %bb.0:177; CHECK-NEXT: vcvt.s32.f32 q0, q0, #18178; CHECK-NEXT: bx lr179 %2 = fmul fast <4 x float> %0, <float 2.621440e+05, float 2.621440e+05, float 2.621440e+05, float 2.621440e+05>180 %3 = fptosi <4 x float> %2 to <4 x i32>181 ret <4 x i32> %3182}183 184define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_19(<4 x float> %0) {185; CHECK-LABEL: vcvt_i32_19:186; CHECK: @ %bb.0:187; CHECK-NEXT: vcvt.s32.f32 q0, q0, #19188; CHECK-NEXT: bx lr189 %2 = fmul fast <4 x float> %0, <float 5.242880e+05, float 5.242880e+05, float 5.242880e+05, float 5.242880e+05>190 %3 = fptosi <4 x float> %2 to <4 x i32>191 ret <4 x i32> %3192}193 194define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_20(<4 x float> %0) {195; CHECK-LABEL: vcvt_i32_20:196; CHECK: @ %bb.0:197; CHECK-NEXT: vcvt.s32.f32 q0, q0, #20198; CHECK-NEXT: bx lr199 %2 = fmul fast <4 x float> %0, <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>200 %3 = fptosi <4 x float> %2 to <4 x i32>201 ret <4 x i32> %3202}203 204define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_21(<4 x float> %0) {205; CHECK-LABEL: vcvt_i32_21:206; CHECK: @ %bb.0:207; CHECK-NEXT: vcvt.s32.f32 q0, q0, #21208; CHECK-NEXT: bx lr209 %2 = fmul fast <4 x float> %0, <float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000>210 %3 = fptosi <4 x float> %2 to <4 x i32>211 ret <4 x i32> %3212}213 214define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_22(<4 x float> %0) {215; CHECK-LABEL: vcvt_i32_22:216; CHECK: @ %bb.0:217; CHECK-NEXT: vcvt.s32.f32 q0, q0, #22218; CHECK-NEXT: bx lr219 %2 = fmul fast <4 x float> %0, <float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000>220 %3 = fptosi <4 x float> %2 to <4 x i32>221 ret <4 x i32> %3222}223 224define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_23(<4 x float> %0) {225; CHECK-LABEL: vcvt_i32_23:226; CHECK: @ %bb.0:227; CHECK-NEXT: vcvt.s32.f32 q0, q0, #23228; CHECK-NEXT: bx lr229 %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>230 %3 = fptosi <4 x float> %2 to <4 x i32>231 ret <4 x i32> %3232}233 234define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_24(<4 x float> %0) {235; CHECK-LABEL: vcvt_i32_24:236; CHECK: @ %bb.0:237; CHECK-NEXT: vcvt.s32.f32 q0, q0, #24238; CHECK-NEXT: bx lr239 %2 = fmul fast <4 x float> %0, <float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000>240 %3 = fptosi <4 x float> %2 to <4 x i32>241 ret <4 x i32> %3242}243 244define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_25(<4 x float> %0) {245; CHECK-LABEL: vcvt_i32_25:246; CHECK: @ %bb.0:247; CHECK-NEXT: vcvt.s32.f32 q0, q0, #25248; CHECK-NEXT: bx lr249 %2 = fmul fast <4 x float> %0, <float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000>250 %3 = fptosi <4 x float> %2 to <4 x i32>251 ret <4 x i32> %3252}253 254define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_26(<4 x float> %0) {255; CHECK-LABEL: vcvt_i32_26:256; CHECK: @ %bb.0:257; CHECK-NEXT: vcvt.s32.f32 q0, q0, #26258; CHECK-NEXT: bx lr259 %2 = fmul fast <4 x float> %0, <float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000>260 %3 = fptosi <4 x float> %2 to <4 x i32>261 ret <4 x i32> %3262}263 264define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_27(<4 x float> %0) {265; CHECK-LABEL: vcvt_i32_27:266; CHECK: @ %bb.0:267; CHECK-NEXT: vcvt.s32.f32 q0, q0, #27268; CHECK-NEXT: bx lr269 %2 = fmul fast <4 x float> %0, <float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000>270 %3 = fptosi <4 x float> %2 to <4 x i32>271 ret <4 x i32> %3272}273 274define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_28(<4 x float> %0) {275; CHECK-LABEL: vcvt_i32_28:276; CHECK: @ %bb.0:277; CHECK-NEXT: vcvt.s32.f32 q0, q0, #28278; CHECK-NEXT: bx lr279 %2 = fmul fast <4 x float> %0, <float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000>280 %3 = fptosi <4 x float> %2 to <4 x i32>281 ret <4 x i32> %3282}283 284define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_29(<4 x float> %0) {285; CHECK-LABEL: vcvt_i32_29:286; CHECK: @ %bb.0:287; CHECK-NEXT: vcvt.s32.f32 q0, q0, #29288; CHECK-NEXT: bx lr289 %2 = fmul fast <4 x float> %0, <float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000>290 %3 = fptosi <4 x float> %2 to <4 x i32>291 ret <4 x i32> %3292}293 294define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_30(<4 x float> %0) {295; CHECK-LABEL: vcvt_i32_30:296; CHECK: @ %bb.0:297; CHECK-NEXT: vcvt.s32.f32 q0, q0, #30298; CHECK-NEXT: bx lr299 %2 = fmul fast <4 x float> %0, <float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000>300 %3 = fptosi <4 x float> %2 to <4 x i32>301 ret <4 x i32> %3302}303 304define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_31(<4 x float> %0) {305; CHECK-LABEL: vcvt_i32_31:306; CHECK: @ %bb.0:307; CHECK-NEXT: vcvt.s32.f32 q0, q0, #31308; CHECK-NEXT: bx lr309 %2 = fmul fast <4 x float> %0, <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>310 %3 = fptosi <4 x float> %2 to <4 x i32>311 ret <4 x i32> %3312}313 314define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_32(<4 x float> %0) {315; CHECK-LABEL: vcvt_i32_32:316; CHECK: @ %bb.0:317; CHECK-NEXT: vcvt.s32.f32 q0, q0, #32318; CHECK-NEXT: bx lr319 %2 = fmul <4 x float> %0, <float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000>320 %3 = fptosi <4 x float> %2 to <4 x i32>321 ret <4 x i32> %3322}323 324define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_33(<4 x float> %0) {325; CHECK-LABEL: vcvt_i32_33:326; CHECK: @ %bb.0:327; CHECK-NEXT: vmov.i32 q1, #0x50000000328; CHECK-NEXT: vmul.f32 q0, q0, q1329; CHECK-NEXT: vcvt.s32.f32 q0, q0330; CHECK-NEXT: bx lr331 %2 = fmul <4 x float> %0, <float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000>332 %3 = fptosi <4 x float> %2 to <4 x i32>333 ret <4 x i32> %3334}335 336define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_1(<8 x half> %0) {337; CHECK-LABEL: vcvt_i16_1:338; CHECK: @ %bb.0:339; CHECK-NEXT: vcvt.s16.f16 q0, q0, #1340; CHECK-NEXT: bx lr341 %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>342 %3 = fptosi <8 x half> %2 to <8 x i16>343 ret <8 x i16> %3344}345 346define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_2(<8 x half> %0) {347; CHECK-LABEL: vcvt_i16_2:348; CHECK: @ %bb.0:349; CHECK-NEXT: vcvt.s16.f16 q0, q0, #2350; CHECK-NEXT: bx lr351 %2 = fmul fast <8 x half> %0, <half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400>352 %3 = fptosi <8 x half> %2 to <8 x i16>353 ret <8 x i16> %3354}355 356define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_3(<8 x half> %0) {357; CHECK-LABEL: vcvt_i16_3:358; CHECK: @ %bb.0:359; CHECK-NEXT: vcvt.s16.f16 q0, q0, #3360; CHECK-NEXT: bx lr361 %2 = fmul fast <8 x half> %0, <half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800>362 %3 = fptosi <8 x half> %2 to <8 x i16>363 ret <8 x i16> %3364}365 366define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_4(<8 x half> %0) {367; CHECK-LABEL: vcvt_i16_4:368; CHECK: @ %bb.0:369; CHECK-NEXT: vcvt.s16.f16 q0, q0, #4370; CHECK-NEXT: bx lr371 %2 = fmul fast <8 x half> %0, <half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00>372 %3 = fptosi <8 x half> %2 to <8 x i16>373 ret <8 x i16> %3374}375 376define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_5(<8 x half> %0) {377; CHECK-LABEL: vcvt_i16_5:378; CHECK: @ %bb.0:379; CHECK-NEXT: vcvt.s16.f16 q0, q0, #5380; CHECK-NEXT: bx lr381 %2 = fmul fast <8 x half> %0, <half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000>382 %3 = fptosi <8 x half> %2 to <8 x i16>383 ret <8 x i16> %3384}385 386define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_6(<8 x half> %0) {387; CHECK-LABEL: vcvt_i16_6:388; CHECK: @ %bb.0:389; CHECK-NEXT: vcvt.s16.f16 q0, q0, #6390; CHECK-NEXT: bx lr391 %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>392 %3 = fptosi <8 x half> %2 to <8 x i16>393 ret <8 x i16> %3394}395 396define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_7(<8 x half> %0) {397; CHECK-LABEL: vcvt_i16_7:398; CHECK: @ %bb.0:399; CHECK-NEXT: vcvt.s16.f16 q0, q0, #7400; CHECK-NEXT: bx lr401 %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>402 %3 = fptosi <8 x half> %2 to <8 x i16>403 ret <8 x i16> %3404}405 406define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_8(<8 x half> %0) {407; CHECK-LABEL: vcvt_i16_8:408; CHECK: @ %bb.0:409; CHECK-NEXT: vcvt.s16.f16 q0, q0, #8410; CHECK-NEXT: bx lr411 %2 = fmul fast <8 x half> %0, <half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00>412 %3 = fptosi <8 x half> %2 to <8 x i16>413 ret <8 x i16> %3414}415 416define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_9(<8 x half> %0) {417; CHECK-LABEL: vcvt_i16_9:418; CHECK: @ %bb.0:419; CHECK-NEXT: vcvt.s16.f16 q0, q0, #9420; CHECK-NEXT: bx lr421 %2 = fmul fast <8 x half> %0, <half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000>422 %3 = fptosi <8 x half> %2 to <8 x i16>423 ret <8 x i16> %3424}425 426define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_10(<8 x half> %0) {427; CHECK-LABEL: vcvt_i16_10:428; CHECK: @ %bb.0:429; CHECK-NEXT: vcvt.s16.f16 q0, q0, #10430; CHECK-NEXT: bx lr431 %2 = fmul fast <8 x half> %0, <half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400>432 %3 = fptosi <8 x half> %2 to <8 x i16>433 ret <8 x i16> %3434}435 436define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_11(<8 x half> %0) {437; CHECK-LABEL: vcvt_i16_11:438; CHECK: @ %bb.0:439; CHECK-NEXT: vcvt.s16.f16 q0, q0, #11440; CHECK-NEXT: bx lr441 %2 = fmul fast <8 x half> %0, <half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800>442 %3 = fptosi <8 x half> %2 to <8 x i16>443 ret <8 x i16> %3444}445 446define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_12(<8 x half> %0) {447; CHECK-LABEL: vcvt_i16_12:448; CHECK: @ %bb.0:449; CHECK-NEXT: vcvt.s16.f16 q0, q0, #12450; CHECK-NEXT: bx lr451 %2 = fmul fast <8 x half> %0, <half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00>452 %3 = fptosi <8 x half> %2 to <8 x i16>453 ret <8 x i16> %3454}455 456define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_13(<8 x half> %0) {457; CHECK-LABEL: vcvt_i16_13:458; CHECK: @ %bb.0:459; CHECK-NEXT: vcvt.s16.f16 q0, q0, #13460; CHECK-NEXT: bx lr461 %2 = fmul fast <8 x half> %0, <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>462 %3 = fptosi <8 x half> %2 to <8 x i16>463 ret <8 x i16> %3464}465 466define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_14(<8 x half> %0) {467; CHECK-LABEL: vcvt_i16_14:468; CHECK: @ %bb.0:469; CHECK-NEXT: vcvt.s16.f16 q0, q0, #14470; CHECK-NEXT: bx lr471 %2 = fmul fast <8 x half> %0, <half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400>472 %3 = fptosi <8 x half> %2 to <8 x i16>473 ret <8 x i16> %3474}475 476define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_15(<8 x half> %0) {477; CHECK-LABEL: vcvt_i16_15:478; CHECK: @ %bb.0:479; CHECK-NEXT: vcvt.s16.f16 q0, q0, #15480; CHECK-NEXT: bx lr481 %2 = fmul fast <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>482 %3 = fptosi <8 x half> %2 to <8 x i16>483 ret <8 x i16> %3484}485 486define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_1(<4 x float> %0) {487; CHECK-LABEL: vcvt_u32_1:488; CHECK: @ %bb.0:489; CHECK-NEXT: vcvt.u32.f32 q0, q0, #1490; CHECK-NEXT: bx lr491 %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>492 %3 = fptoui <4 x float> %2 to <4 x i32>493 ret <4 x i32> %3494}495 496define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_2(<4 x float> %0) {497; CHECK-LABEL: vcvt_u32_2:498; CHECK: @ %bb.0:499; CHECK-NEXT: vcvt.u32.f32 q0, q0, #2500; CHECK-NEXT: bx lr501 %2 = fmul fast <4 x float> %0, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>502 %3 = fptoui <4 x float> %2 to <4 x i32>503 ret <4 x i32> %3504}505 506define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_3(<4 x float> %0) {507; CHECK-LABEL: vcvt_u32_3:508; CHECK: @ %bb.0:509; CHECK-NEXT: vcvt.u32.f32 q0, q0, #3510; CHECK-NEXT: bx lr511 %2 = fmul fast <4 x float> %0, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>512 %3 = fptoui <4 x float> %2 to <4 x i32>513 ret <4 x i32> %3514}515 516define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_4(<4 x float> %0) {517; CHECK-LABEL: vcvt_u32_4:518; CHECK: @ %bb.0:519; CHECK-NEXT: vcvt.u32.f32 q0, q0, #4520; CHECK-NEXT: bx lr521 %2 = fmul fast <4 x float> %0, <float 1.600000e+01, float 1.600000e+01, float 1.600000e+01, float 1.600000e+01>522 %3 = fptoui <4 x float> %2 to <4 x i32>523 ret <4 x i32> %3524}525 526define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_5(<4 x float> %0) {527; CHECK-LABEL: vcvt_u32_5:528; CHECK: @ %bb.0:529; CHECK-NEXT: vcvt.u32.f32 q0, q0, #5530; CHECK-NEXT: bx lr531 %2 = fmul fast <4 x float> %0, <float 3.200000e+01, float 3.200000e+01, float 3.200000e+01, float 3.200000e+01>532 %3 = fptoui <4 x float> %2 to <4 x i32>533 ret <4 x i32> %3534}535 536define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_6(<4 x float> %0) {537; CHECK-LABEL: vcvt_u32_6:538; CHECK: @ %bb.0:539; CHECK-NEXT: vcvt.u32.f32 q0, q0, #6540; CHECK-NEXT: bx lr541 %2 = fmul fast <4 x float> %0, <float 6.400000e+01, float 6.400000e+01, float 6.400000e+01, float 6.400000e+01>542 %3 = fptoui <4 x float> %2 to <4 x i32>543 ret <4 x i32> %3544}545 546define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_7(<4 x float> %0) {547; CHECK-LABEL: vcvt_u32_7:548; CHECK: @ %bb.0:549; CHECK-NEXT: vcvt.u32.f32 q0, q0, #7550; CHECK-NEXT: bx lr551 %2 = fmul fast <4 x float> %0, <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>552 %3 = fptoui <4 x float> %2 to <4 x i32>553 ret <4 x i32> %3554}555 556define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_8(<4 x float> %0) {557; CHECK-LABEL: vcvt_u32_8:558; CHECK: @ %bb.0:559; CHECK-NEXT: vcvt.u32.f32 q0, q0, #8560; CHECK-NEXT: bx lr561 %2 = fmul fast <4 x float> %0, <float 2.560000e+02, float 2.560000e+02, float 2.560000e+02, float 2.560000e+02>562 %3 = fptoui <4 x float> %2 to <4 x i32>563 ret <4 x i32> %3564}565 566define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_9(<4 x float> %0) {567; CHECK-LABEL: vcvt_u32_9:568; CHECK: @ %bb.0:569; CHECK-NEXT: vcvt.u32.f32 q0, q0, #9570; CHECK-NEXT: bx lr571 %2 = fmul fast <4 x float> %0, <float 5.120000e+02, float 5.120000e+02, float 5.120000e+02, float 5.120000e+02>572 %3 = fptoui <4 x float> %2 to <4 x i32>573 ret <4 x i32> %3574}575 576define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_10(<4 x float> %0) {577; CHECK-LABEL: vcvt_u32_10:578; CHECK: @ %bb.0:579; CHECK-NEXT: vcvt.u32.f32 q0, q0, #10580; CHECK-NEXT: bx lr581 %2 = fmul fast <4 x float> %0, <float 1.024000e+03, float 1.024000e+03, float 1.024000e+03, float 1.024000e+03>582 %3 = fptoui <4 x float> %2 to <4 x i32>583 ret <4 x i32> %3584}585 586define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_11(<4 x float> %0) {587; CHECK-LABEL: vcvt_u32_11:588; CHECK: @ %bb.0:589; CHECK-NEXT: vcvt.u32.f32 q0, q0, #11590; CHECK-NEXT: bx lr591 %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>592 %3 = fptoui <4 x float> %2 to <4 x i32>593 ret <4 x i32> %3594}595 596define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_12(<4 x float> %0) {597; CHECK-LABEL: vcvt_u32_12:598; CHECK: @ %bb.0:599; CHECK-NEXT: vcvt.u32.f32 q0, q0, #12600; CHECK-NEXT: bx lr601 %2 = fmul fast <4 x float> %0, <float 4.096000e+03, float 4.096000e+03, float 4.096000e+03, float 4.096000e+03>602 %3 = fptoui <4 x float> %2 to <4 x i32>603 ret <4 x i32> %3604}605 606define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_13(<4 x float> %0) {607; CHECK-LABEL: vcvt_u32_13:608; CHECK: @ %bb.0:609; CHECK-NEXT: vcvt.u32.f32 q0, q0, #13610; CHECK-NEXT: bx lr611 %2 = fmul fast <4 x float> %0, <float 8.192000e+03, float 8.192000e+03, float 8.192000e+03, float 8.192000e+03>612 %3 = fptoui <4 x float> %2 to <4 x i32>613 ret <4 x i32> %3614}615 616define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_14(<4 x float> %0) {617; CHECK-LABEL: vcvt_u32_14:618; CHECK: @ %bb.0:619; CHECK-NEXT: vcvt.u32.f32 q0, q0, #14620; CHECK-NEXT: bx lr621 %2 = fmul fast <4 x float> %0, <float 1.638400e+04, float 1.638400e+04, float 1.638400e+04, float 1.638400e+04>622 %3 = fptoui <4 x float> %2 to <4 x i32>623 ret <4 x i32> %3624}625 626define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_15(<4 x float> %0) {627; CHECK-LABEL: vcvt_u32_15:628; CHECK: @ %bb.0:629; CHECK-NEXT: vcvt.u32.f32 q0, q0, #15630; CHECK-NEXT: bx lr631 %2 = fmul fast <4 x float> %0, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>632 %3 = fptoui <4 x float> %2 to <4 x i32>633 ret <4 x i32> %3634}635 636define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_16(<4 x float> %0) {637; CHECK-LABEL: vcvt_u32_16:638; CHECK: @ %bb.0:639; CHECK-NEXT: vcvt.u32.f32 q0, q0, #16640; CHECK-NEXT: bx lr641 %2 = fmul fast <4 x float> %0, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>642 %3 = fptoui <4 x float> %2 to <4 x i32>643 ret <4 x i32> %3644}645 646define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_17(<4 x float> %0) {647; CHECK-LABEL: vcvt_u32_17:648; CHECK: @ %bb.0:649; CHECK-NEXT: vcvt.u32.f32 q0, q0, #17650; CHECK-NEXT: bx lr651 %2 = fmul fast <4 x float> %0, <float 1.310720e+05, float 1.310720e+05, float 1.310720e+05, float 1.310720e+05>652 %3 = fptoui <4 x float> %2 to <4 x i32>653 ret <4 x i32> %3654}655 656define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_18(<4 x float> %0) {657; CHECK-LABEL: vcvt_u32_18:658; CHECK: @ %bb.0:659; CHECK-NEXT: vcvt.u32.f32 q0, q0, #18660; CHECK-NEXT: bx lr661 %2 = fmul fast <4 x float> %0, <float 2.621440e+05, float 2.621440e+05, float 2.621440e+05, float 2.621440e+05>662 %3 = fptoui <4 x float> %2 to <4 x i32>663 ret <4 x i32> %3664}665 666define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_19(<4 x float> %0) {667; CHECK-LABEL: vcvt_u32_19:668; CHECK: @ %bb.0:669; CHECK-NEXT: vcvt.u32.f32 q0, q0, #19670; CHECK-NEXT: bx lr671 %2 = fmul fast <4 x float> %0, <float 5.242880e+05, float 5.242880e+05, float 5.242880e+05, float 5.242880e+05>672 %3 = fptoui <4 x float> %2 to <4 x i32>673 ret <4 x i32> %3674}675 676define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_20(<4 x float> %0) {677; CHECK-LABEL: vcvt_u32_20:678; CHECK: @ %bb.0:679; CHECK-NEXT: vcvt.u32.f32 q0, q0, #20680; CHECK-NEXT: bx lr681 %2 = fmul fast <4 x float> %0, <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>682 %3 = fptoui <4 x float> %2 to <4 x i32>683 ret <4 x i32> %3684}685 686define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_21(<4 x float> %0) {687; CHECK-LABEL: vcvt_u32_21:688; CHECK: @ %bb.0:689; CHECK-NEXT: vcvt.u32.f32 q0, q0, #21690; CHECK-NEXT: bx lr691 %2 = fmul fast <4 x float> %0, <float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000>692 %3 = fptoui <4 x float> %2 to <4 x i32>693 ret <4 x i32> %3694}695 696define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_22(<4 x float> %0) {697; CHECK-LABEL: vcvt_u32_22:698; CHECK: @ %bb.0:699; CHECK-NEXT: vcvt.u32.f32 q0, q0, #22700; CHECK-NEXT: bx lr701 %2 = fmul fast <4 x float> %0, <float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000>702 %3 = fptoui <4 x float> %2 to <4 x i32>703 ret <4 x i32> %3704}705 706define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_23(<4 x float> %0) {707; CHECK-LABEL: vcvt_u32_23:708; CHECK: @ %bb.0:709; CHECK-NEXT: vcvt.u32.f32 q0, q0, #23710; CHECK-NEXT: bx lr711 %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>712 %3 = fptoui <4 x float> %2 to <4 x i32>713 ret <4 x i32> %3714}715 716define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_24(<4 x float> %0) {717; CHECK-LABEL: vcvt_u32_24:718; CHECK: @ %bb.0:719; CHECK-NEXT: vcvt.u32.f32 q0, q0, #24720; CHECK-NEXT: bx lr721 %2 = fmul fast <4 x float> %0, <float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000>722 %3 = fptoui <4 x float> %2 to <4 x i32>723 ret <4 x i32> %3724}725 726define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_25(<4 x float> %0) {727; CHECK-LABEL: vcvt_u32_25:728; CHECK: @ %bb.0:729; CHECK-NEXT: vcvt.u32.f32 q0, q0, #25730; CHECK-NEXT: bx lr731 %2 = fmul fast <4 x float> %0, <float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000>732 %3 = fptoui <4 x float> %2 to <4 x i32>733 ret <4 x i32> %3734}735 736define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_26(<4 x float> %0) {737; CHECK-LABEL: vcvt_u32_26:738; CHECK: @ %bb.0:739; CHECK-NEXT: vcvt.u32.f32 q0, q0, #26740; CHECK-NEXT: bx lr741 %2 = fmul fast <4 x float> %0, <float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000>742 %3 = fptoui <4 x float> %2 to <4 x i32>743 ret <4 x i32> %3744}745 746define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_27(<4 x float> %0) {747; CHECK-LABEL: vcvt_u32_27:748; CHECK: @ %bb.0:749; CHECK-NEXT: vcvt.u32.f32 q0, q0, #27750; CHECK-NEXT: bx lr751 %2 = fmul fast <4 x float> %0, <float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000>752 %3 = fptoui <4 x float> %2 to <4 x i32>753 ret <4 x i32> %3754}755 756define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_28(<4 x float> %0) {757; CHECK-LABEL: vcvt_u32_28:758; CHECK: @ %bb.0:759; CHECK-NEXT: vcvt.u32.f32 q0, q0, #28760; CHECK-NEXT: bx lr761 %2 = fmul fast <4 x float> %0, <float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000>762 %3 = fptoui <4 x float> %2 to <4 x i32>763 ret <4 x i32> %3764}765 766define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_29(<4 x float> %0) {767; CHECK-LABEL: vcvt_u32_29:768; CHECK: @ %bb.0:769; CHECK-NEXT: vcvt.u32.f32 q0, q0, #29770; CHECK-NEXT: bx lr771 %2 = fmul fast <4 x float> %0, <float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000>772 %3 = fptoui <4 x float> %2 to <4 x i32>773 ret <4 x i32> %3774}775 776define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_30(<4 x float> %0) {777; CHECK-LABEL: vcvt_u32_30:778; CHECK: @ %bb.0:779; CHECK-NEXT: vcvt.u32.f32 q0, q0, #30780; CHECK-NEXT: bx lr781 %2 = fmul fast <4 x float> %0, <float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000>782 %3 = fptoui <4 x float> %2 to <4 x i32>783 ret <4 x i32> %3784}785 786define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_31(<4 x float> %0) {787; CHECK-LABEL: vcvt_u32_31:788; CHECK: @ %bb.0:789; CHECK-NEXT: vcvt.u32.f32 q0, q0, #31790; CHECK-NEXT: bx lr791 %2 = fmul fast <4 x float> %0, <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>792 %3 = fptoui <4 x float> %2 to <4 x i32>793 ret <4 x i32> %3794}795 796define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_32(<4 x float> %0) {797; CHECK-LABEL: vcvt_u32_32:798; CHECK: @ %bb.0:799; CHECK-NEXT: vcvt.u32.f32 q0, q0, #32800; CHECK-NEXT: bx lr801 %2 = fmul <4 x float> %0, <float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000>802 %3 = fptoui <4 x float> %2 to <4 x i32>803 ret <4 x i32> %3804}805 806define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_33(<4 x float> %0) {807; CHECK-LABEL: vcvt_u32_33:808; CHECK: @ %bb.0:809; CHECK-NEXT: vmov.i32 q1, #0x50000000810; CHECK-NEXT: vmul.f32 q0, q0, q1811; CHECK-NEXT: vcvt.u32.f32 q0, q0812; CHECK-NEXT: bx lr813 %2 = fmul <4 x float> %0, <float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000>814 %3 = fptoui <4 x float> %2 to <4 x i32>815 ret <4 x i32> %3816}817 818define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_1(<8 x half> %0) {819; CHECK-LABEL: vcvt_u16_1:820; CHECK: @ %bb.0:821; CHECK-NEXT: vcvt.u16.f16 q0, q0, #1822; CHECK-NEXT: bx lr823 %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>824 %3 = fptoui <8 x half> %2 to <8 x i16>825 ret <8 x i16> %3826}827 828define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_2(<8 x half> %0) {829; CHECK-LABEL: vcvt_u16_2:830; CHECK: @ %bb.0:831; CHECK-NEXT: vcvt.u16.f16 q0, q0, #2832; CHECK-NEXT: bx lr833 %2 = fmul fast <8 x half> %0, <half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400>834 %3 = fptoui <8 x half> %2 to <8 x i16>835 ret <8 x i16> %3836}837 838define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_3(<8 x half> %0) {839; CHECK-LABEL: vcvt_u16_3:840; CHECK: @ %bb.0:841; CHECK-NEXT: vcvt.u16.f16 q0, q0, #3842; CHECK-NEXT: bx lr843 %2 = fmul fast <8 x half> %0, <half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800>844 %3 = fptoui <8 x half> %2 to <8 x i16>845 ret <8 x i16> %3846}847 848define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_4(<8 x half> %0) {849; CHECK-LABEL: vcvt_u16_4:850; CHECK: @ %bb.0:851; CHECK-NEXT: vcvt.u16.f16 q0, q0, #4852; CHECK-NEXT: bx lr853 %2 = fmul fast <8 x half> %0, <half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00>854 %3 = fptoui <8 x half> %2 to <8 x i16>855 ret <8 x i16> %3856}857 858define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_5(<8 x half> %0) {859; CHECK-LABEL: vcvt_u16_5:860; CHECK: @ %bb.0:861; CHECK-NEXT: vcvt.u16.f16 q0, q0, #5862; CHECK-NEXT: bx lr863 %2 = fmul fast <8 x half> %0, <half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000>864 %3 = fptoui <8 x half> %2 to <8 x i16>865 ret <8 x i16> %3866}867 868define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_6(<8 x half> %0) {869; CHECK-LABEL: vcvt_u16_6:870; CHECK: @ %bb.0:871; CHECK-NEXT: vcvt.u16.f16 q0, q0, #6872; CHECK-NEXT: bx lr873 %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>874 %3 = fptoui <8 x half> %2 to <8 x i16>875 ret <8 x i16> %3876}877 878define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_7(<8 x half> %0) {879; CHECK-LABEL: vcvt_u16_7:880; CHECK: @ %bb.0:881; CHECK-NEXT: vcvt.u16.f16 q0, q0, #7882; CHECK-NEXT: bx lr883 %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>884 %3 = fptoui <8 x half> %2 to <8 x i16>885 ret <8 x i16> %3886}887 888define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_8(<8 x half> %0) {889; CHECK-LABEL: vcvt_u16_8:890; CHECK: @ %bb.0:891; CHECK-NEXT: vcvt.u16.f16 q0, q0, #8892; CHECK-NEXT: bx lr893 %2 = fmul fast <8 x half> %0, <half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00>894 %3 = fptoui <8 x half> %2 to <8 x i16>895 ret <8 x i16> %3896}897 898define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_9(<8 x half> %0) {899; CHECK-LABEL: vcvt_u16_9:900; CHECK: @ %bb.0:901; CHECK-NEXT: vcvt.u16.f16 q0, q0, #9902; CHECK-NEXT: bx lr903 %2 = fmul fast <8 x half> %0, <half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000>904 %3 = fptoui <8 x half> %2 to <8 x i16>905 ret <8 x i16> %3906}907 908define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_10(<8 x half> %0) {909; CHECK-LABEL: vcvt_u16_10:910; CHECK: @ %bb.0:911; CHECK-NEXT: vcvt.u16.f16 q0, q0, #10912; CHECK-NEXT: bx lr913 %2 = fmul fast <8 x half> %0, <half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400>914 %3 = fptoui <8 x half> %2 to <8 x i16>915 ret <8 x i16> %3916}917 918define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_11(<8 x half> %0) {919; CHECK-LABEL: vcvt_u16_11:920; CHECK: @ %bb.0:921; CHECK-NEXT: vcvt.u16.f16 q0, q0, #11922; CHECK-NEXT: bx lr923 %2 = fmul fast <8 x half> %0, <half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800>924 %3 = fptoui <8 x half> %2 to <8 x i16>925 ret <8 x i16> %3926}927 928define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_12(<8 x half> %0) {929; CHECK-LABEL: vcvt_u16_12:930; CHECK: @ %bb.0:931; CHECK-NEXT: vcvt.u16.f16 q0, q0, #12932; CHECK-NEXT: bx lr933 %2 = fmul fast <8 x half> %0, <half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00>934 %3 = fptoui <8 x half> %2 to <8 x i16>935 ret <8 x i16> %3936}937 938define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_13(<8 x half> %0) {939; CHECK-LABEL: vcvt_u16_13:940; CHECK: @ %bb.0:941; CHECK-NEXT: vcvt.u16.f16 q0, q0, #13942; CHECK-NEXT: bx lr943 %2 = fmul fast <8 x half> %0, <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>944 %3 = fptoui <8 x half> %2 to <8 x i16>945 ret <8 x i16> %3946}947 948define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_14(<8 x half> %0) {949; CHECK-LABEL: vcvt_u16_14:950; CHECK: @ %bb.0:951; CHECK-NEXT: vcvt.u16.f16 q0, q0, #14952; CHECK-NEXT: bx lr953 %2 = fmul fast <8 x half> %0, <half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400>954 %3 = fptoui <8 x half> %2 to <8 x i16>955 ret <8 x i16> %3956}957 958define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_15(<8 x half> %0) {959; CHECK-LABEL: vcvt_u16_15:960; CHECK: @ %bb.0:961; CHECK-NEXT: vcvt.u16.f16 q0, q0, #15962; CHECK-NEXT: bx lr963 %2 = fmul fast <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>964 %3 = fptoui <8 x half> %2 to <8 x i16>965 ret <8 x i16> %3966}967 968define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_inf(<8 x half> %0) {969; CHECK-LABEL: vcvt_u16_inf:970; CHECK: @ %bb.0:971; CHECK-NEXT: vmov.i16 q1, #0x7800972; CHECK-NEXT: vmul.f16 q0, q0, q1973; CHECK-NEXT: vcvt.u16.f16 q0, q0974; CHECK-NEXT: bx lr975 %2 = fmul <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>976 %3 = fptoui <8 x half> %2 to <8 x i16>977 ret <8 x i16> %3978}979 980define arm_aapcs_vfpcc <8 x i16> @vcvt_s16_inf(<8 x half> %0) {981; CHECK-LABEL: vcvt_s16_inf:982; CHECK: @ %bb.0:983; CHECK-NEXT: vcvt.s16.f16 q0, q0, #15984; CHECK-NEXT: bx lr985 %2 = fmul <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>986 %3 = fptosi <8 x half> %2 to <8 x i16>987 ret <8 x i16> %3988}989 990 991define arm_aapcs_vfpcc <4 x i32> @vcvt_bad_imm(<4 x float> %0) {992; CHECK-LABEL: vcvt_bad_imm:993; CHECK: @ %bb.0:994; CHECK-NEXT: movw r0, #2048995; CHECK-NEXT: movt r0, #15104996; CHECK-NEXT: vmul.f32 q0, q0, r0997; CHECK-NEXT: vcvt.s32.f32 q0, q0998; CHECK-NEXT: bx lr999 %2 = fmul <4 x float> %0, <float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000>1000 %3 = fptosi <4 x float> %2 to <4 x i32>1001 ret <4 x i32> %31002}1003 1004define arm_aapcs_vfpcc <4 x i32> @vcvt_negative(<4 x float> %0) {1005; CHECK-LABEL: vcvt_negative:1006; CHECK: @ %bb.0:1007; CHECK-NEXT: vmov.i32 q1, #0xb80000001008; CHECK-NEXT: vmul.f32 q0, q0, q11009; CHECK-NEXT: vcvt.s32.f32 q0, q01010; CHECK-NEXT: bx lr1011 %2 = fmul <4 x float> %0, <float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000>1012 %3 = fptosi <4 x float> %2 to <4 x i32>1013 ret <4 x i32> %31014}1015 1016define arm_aapcs_vfpcc <4 x i32> @vcvt_negative2(<4 x float> %0) {1017; CHECK-LABEL: vcvt_negative2:1018; CHECK: @ %bb.0:1019; CHECK-NEXT: vmov.i32 q1, #0xb00000001020; CHECK-NEXT: vmul.f32 q0, q0, q11021; CHECK-NEXT: vcvt.s32.f32 q0, q01022; CHECK-NEXT: bx lr1023 %2 = fmul <4 x float> %0, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>1024 %3 = fptosi <4 x float> %2 to <4 x i32>1025 ret <4 x i32> %31026}1027 1028 1029 1030define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_1(<8 x half> %0) {1031; CHECK-LABEL: vcvt_sat_s16_1:1032; CHECK: @ %bb.0:1033; CHECK-NEXT: vcvt.s16.f16 q0, q0, #11034; CHECK-NEXT: bx lr1035 %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>1036 %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)1037 ret <8 x i16> %31038}1039 1040define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_1(<8 x half> %0) {1041; CHECK-LABEL: vcvt_sat_u16_1:1042; CHECK: @ %bb.0:1043; CHECK-NEXT: vcvt.u16.f16 q0, q0, #11044; CHECK-NEXT: bx lr1045 %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>1046 %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)1047 ret <8 x i16> %31048}1049 1050define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_6(<8 x half> %0) {1051; CHECK-LABEL: vcvt_sat_s16_6:1052; CHECK: @ %bb.0:1053; CHECK-NEXT: vcvt.s16.f16 q0, q0, #61054; CHECK-NEXT: bx lr1055 %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>1056 %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)1057 ret <8 x i16> %31058}1059 1060define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_7(<8 x half> %0) {1061; CHECK-LABEL: vcvt_sat_u16_7:1062; CHECK: @ %bb.0:1063; CHECK-NEXT: vcvt.u16.f16 q0, q0, #71064; CHECK-NEXT: bx lr1065 %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>1066 %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)1067 ret <8 x i16> %31068}1069 1070 1071define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_s32_1(<4 x float> %0) {1072; CHECK-LABEL: vcvt_sat_s32_1:1073; CHECK: @ %bb.0:1074; CHECK-NEXT: vcvt.s32.f32 q0, q0, #11075; CHECK-NEXT: bx lr1076 %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>1077 %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)1078 ret <4 x i32> %31079}1080 1081define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_1(<4 x float> %0) {1082; CHECK-LABEL: vcvt_sat_u32_1:1083; CHECK: @ %bb.0:1084; CHECK-NEXT: vcvt.u32.f32 q0, q0, #11085; CHECK-NEXT: bx lr1086 %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>1087 %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)1088 ret <4 x i32> %31089}1090 1091define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_11(<4 x float> %0) {1092; CHECK-LABEL: vcvt_sat_u32_11:1093; CHECK: @ %bb.0:1094; CHECK-NEXT: vcvt.s32.f32 q0, q0, #111095; CHECK-NEXT: bx lr1096 %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>1097 %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)1098 ret <4 x i32> %31099}1100 1101define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7(<4 x float> %0) {1102; CHECK-LABEL: vcvt_sat_u32_7:1103; CHECK: @ %bb.0:1104; CHECK-NEXT: vcvt.u32.f32 q0, q0, #231105; CHECK-NEXT: bx lr1106 %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>1107 %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)1108 ret <4 x i32> %31109}1110 1111define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7_24(<4 x float> %0) {1112; CHECK-LABEL: vcvt_sat_u32_7_24:1113; CHECK: @ %bb.0:1114; CHECK-NEXT: vmov.i32 q1, #0xffffff1115; CHECK-NEXT: vcvt.u32.f32 q0, q0, #231116; CHECK-NEXT: vmin.u32 q0, q0, q11117; CHECK-NEXT: bx lr1118 %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>1119 %3 = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %2)1120 %4 = zext <4 x i24> %3 to <4 x i32>1121 ret <4 x i32> %41122}1123 1124declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)1125declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)1126declare <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float>)1127declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>)1128declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>)1129