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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP4 5define arm_aapcs_vfpcc <4 x float> @fpext_4(<4 x half> %src1) {6; CHECK-LABEL: fpext_4:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vcvtt.f32.f16 s3, s19; CHECK-NEXT: vcvtb.f32.f16 s2, s110; CHECK-NEXT: vcvtt.f32.f16 s1, s011; CHECK-NEXT: vcvtb.f32.f16 s0, s012; CHECK-NEXT: bx lr13entry:14 %out = fpext <4 x half> %src1 to <4 x float>15 ret <4 x float> %out16}17 18define arm_aapcs_vfpcc <8 x float> @fpext_8(<8 x half> %src1) {19; CHECK-LABEL: fpext_8:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vcvtt.f32.f16 s11, s122; CHECK-NEXT: vcvtb.f32.f16 s10, s123; CHECK-NEXT: vcvtt.f32.f16 s9, s024; CHECK-NEXT: vcvtb.f32.f16 s8, s025; CHECK-NEXT: vcvtt.f32.f16 s7, s326; CHECK-NEXT: vcvtb.f32.f16 s6, s327; CHECK-NEXT: vcvtt.f32.f16 s5, s228; CHECK-NEXT: vcvtb.f32.f16 s4, s229; CHECK-NEXT: vmov q0, q230; CHECK-NEXT: bx lr31entry:32 %out = fpext <8 x half> %src1 to <8 x float>33 ret <8 x float> %out34}35 36 37define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {38; CHECK-LABEL: fptrunc_4:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vcvtb.f16.f32 s0, s041; CHECK-NEXT: vcvtt.f16.f32 s0, s142; CHECK-NEXT: vcvtb.f16.f32 s1, s243; CHECK-NEXT: vcvtt.f16.f32 s1, s344; CHECK-NEXT: bx lr45entry:46 %out = fptrunc <4 x float> %src1 to <4 x half>47 ret <4 x half> %out48}49 50define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) {51; CHECK-LABEL: fptrunc_8:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: vcvtb.f16.f32 s0, s054; CHECK-NEXT: vcvtt.f16.f32 s0, s155; CHECK-NEXT: vcvtb.f16.f32 s1, s256; CHECK-NEXT: vcvtb.f16.f32 s2, s457; CHECK-NEXT: vcvtt.f16.f32 s1, s358; CHECK-NEXT: vcvtb.f16.f32 s3, s659; CHECK-NEXT: vcvtt.f16.f32 s2, s560; CHECK-NEXT: vcvtt.f16.f32 s3, s761; CHECK-NEXT: bx lr62entry:63 %out = fptrunc <8 x float> %src1 to <8 x half>64 ret <8 x half> %out65}66 67 68define arm_aapcs_vfpcc <8 x half> @shuffle_trunc1(<4 x float> %src1, <4 x float> %src2) {69; CHECK-MVE-LABEL: shuffle_trunc1:70; CHECK-MVE: @ %bb.0: @ %entry71; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s072; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s173; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s274; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s375; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s476; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s577; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s678; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s779; CHECK-MVE-NEXT: bx lr80;81; CHECK-MVEFP-LABEL: shuffle_trunc1:82; CHECK-MVEFP: @ %bb.0: @ %entry83; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q084; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q185; CHECK-MVEFP-NEXT: bx lr86entry:87 %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>88 %out = fptrunc <8 x float> %strided.vec to <8 x half>89 ret <8 x half> %out90}91 92define arm_aapcs_vfpcc <8 x half> @shuffle_trunc2(<4 x float> %src1, <4 x float> %src2) {93; CHECK-MVE-LABEL: shuffle_trunc2:94; CHECK-MVE: @ %bb.0: @ %entry95; CHECK-MVE-NEXT: vmov q2, q096; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s497; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s598; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s699; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s7100; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8101; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9102; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10103; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11104; CHECK-MVE-NEXT: bx lr105;106; CHECK-MVEFP-LABEL: shuffle_trunc2:107; CHECK-MVEFP: @ %bb.0: @ %entry108; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1109; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q0110; CHECK-MVEFP-NEXT: vmov q0, q1111; CHECK-MVEFP-NEXT: bx lr112entry:113 %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>114 %out = fptrunc <8 x float> %strided.vec to <8 x half>115 ret <8 x half> %out116}117 118define arm_aapcs_vfpcc <16 x half> @shuffle_trunc3(<8 x float> %src1, <8 x float> %src2) {119; CHECK-MVE-LABEL: shuffle_trunc3:120; CHECK-MVE: @ %bb.0: @ %entry121; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0122; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s1123; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2124; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s3125; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s4126; CHECK-MVE-NEXT: vcvtb.f16.f32 s5, s5127; CHECK-MVE-NEXT: vcvtb.f16.f32 s6, s6128; CHECK-MVE-NEXT: vcvtb.f16.f32 s7, s7129; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8130; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9131; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10132; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11133; CHECK-MVE-NEXT: vcvtt.f16.f32 s4, s12134; CHECK-MVE-NEXT: vcvtt.f16.f32 s5, s13135; CHECK-MVE-NEXT: vcvtt.f16.f32 s6, s14136; CHECK-MVE-NEXT: vcvtt.f16.f32 s7, s15137; CHECK-MVE-NEXT: bx lr138;139; CHECK-MVEFP-LABEL: shuffle_trunc3:140; CHECK-MVEFP: @ %bb.0: @ %entry141; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0142; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1143; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q2144; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q3145; CHECK-MVEFP-NEXT: bx lr146entry:147 %strided.vec = shufflevector <8 x float> %src1, <8 x float> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>148 %out = fptrunc <16 x float> %strided.vec to <16 x half>149 ret <16 x half> %out150}151 152define arm_aapcs_vfpcc <16 x half> @shuffle_trunc4(<8 x float> %src1, <8 x float> %src2) {153; CHECK-MVE-LABEL: shuffle_trunc4:154; CHECK-MVE: @ %bb.0: @ %entry155; CHECK-MVE-NEXT: .vsave {d8, d9}156; CHECK-MVE-NEXT: vpush {d8, d9}157; CHECK-MVE-NEXT: vmov q4, q0158; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s8159; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s9160; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s10161; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s11162; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s12163; CHECK-MVE-NEXT: vcvtb.f16.f32 s9, s13164; CHECK-MVE-NEXT: vcvtb.f16.f32 s10, s14165; CHECK-MVE-NEXT: vcvtb.f16.f32 s11, s15166; CHECK-MVE-NEXT: vcvtt.f16.f32 s8, s4167; CHECK-MVE-NEXT: vcvtt.f16.f32 s9, s5168; CHECK-MVE-NEXT: vcvtt.f16.f32 s10, s6169; CHECK-MVE-NEXT: vcvtt.f16.f32 s11, s7170; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s16171; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s17172; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s18173; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s19174; CHECK-MVE-NEXT: vmov q1, q2175; CHECK-MVE-NEXT: vpop {d8, d9}176; CHECK-MVE-NEXT: bx lr177;178; CHECK-MVEFP-LABEL: shuffle_trunc4:179; CHECK-MVEFP: @ %bb.0: @ %entry180; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q2, q2181; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q3, q3182; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q2, q0183; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q3, q1184; CHECK-MVEFP-NEXT: vmov q0, q2185; CHECK-MVEFP-NEXT: vmov q1, q3186; CHECK-MVEFP-NEXT: bx lr187entry:188 %strided.vec = shufflevector <8 x float> %src1, <8 x float> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>189 %out = fptrunc <16 x float> %strided.vec to <16 x half>190 ret <16 x half> %out191}192 193define arm_aapcs_vfpcc <8 x half> @shuffle_trunc5(<4 x float> %src1, <4 x float> %src2) {194; CHECK-MVE-LABEL: shuffle_trunc5:195; CHECK-MVE: @ %bb.0: @ %entry196; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0197; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s1198; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2199; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s3200; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s4201; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s5202; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s6203; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7204; CHECK-MVE-NEXT: bx lr205;206; CHECK-MVEFP-LABEL: shuffle_trunc5:207; CHECK-MVEFP: @ %bb.0: @ %entry208; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0209; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q1210; CHECK-MVEFP-NEXT: bx lr211entry:212 %out1 = fptrunc <4 x float> %src1 to <4 x half>213 %out2 = fptrunc <4 x float> %src2 to <4 x half>214 %s = shufflevector <4 x half> %out1, <4 x half> %out2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>215 ret <8 x half> %s216}217 218define arm_aapcs_vfpcc <8 x half> @shuffle_trunc6(<4 x float> %src1, <4 x float> %src2) {219; CHECK-MVE-LABEL: shuffle_trunc6:220; CHECK-MVE: @ %bb.0: @ %entry221; CHECK-MVE-NEXT: vmov q2, q0222; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s4223; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s5224; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s6225; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s7226; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8227; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9228; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10229; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11230; CHECK-MVE-NEXT: bx lr231;232; CHECK-MVEFP-LABEL: shuffle_trunc6:233; CHECK-MVEFP: @ %bb.0: @ %entry234; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1235; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q0236; CHECK-MVEFP-NEXT: vmov q0, q1237; CHECK-MVEFP-NEXT: bx lr238entry:239 %out1 = fptrunc <4 x float> %src1 to <4 x half>240 %out2 = fptrunc <4 x float> %src2 to <4 x half>241 %s = shufflevector <4 x half> %out1, <4 x half> %out2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>242 ret <8 x half> %s243}244 245define arm_aapcs_vfpcc <16 x half> @shuffle_trunc7(<8 x float> %src1, <8 x float> %src2) {246; CHECK-MVE-LABEL: shuffle_trunc7:247; CHECK-MVE: @ %bb.0: @ %entry248; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0249; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s1250; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2251; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s3252; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s4253; CHECK-MVE-NEXT: vcvtb.f16.f32 s5, s5254; CHECK-MVE-NEXT: vcvtb.f16.f32 s6, s6255; CHECK-MVE-NEXT: vcvtb.f16.f32 s7, s7256; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8257; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9258; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10259; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11260; CHECK-MVE-NEXT: vcvtt.f16.f32 s4, s12261; CHECK-MVE-NEXT: vcvtt.f16.f32 s5, s13262; CHECK-MVE-NEXT: vcvtt.f16.f32 s6, s14263; CHECK-MVE-NEXT: vcvtt.f16.f32 s7, s15264; CHECK-MVE-NEXT: bx lr265;266; CHECK-MVEFP-LABEL: shuffle_trunc7:267; CHECK-MVEFP: @ %bb.0: @ %entry268; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0269; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1270; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q2271; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q3272; CHECK-MVEFP-NEXT: bx lr273entry:274 %out1 = fptrunc <8 x float> %src1 to <8 x half>275 %out2 = fptrunc <8 x float> %src2 to <8 x half>276 %s = shufflevector <8 x half> %out1, <8 x half> %out2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>277 ret <16 x half> %s278}279 280define arm_aapcs_vfpcc <16 x half> @shuffle_trunc8(<8 x float> %src1, <8 x float> %src2) {281; CHECK-MVE-LABEL: shuffle_trunc8:282; CHECK-MVE: @ %bb.0: @ %entry283; CHECK-MVE-NEXT: .vsave {d8, d9}284; CHECK-MVE-NEXT: vpush {d8, d9}285; CHECK-MVE-NEXT: vmov q4, q0286; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s8287; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s9288; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s10289; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s11290; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s12291; CHECK-MVE-NEXT: vcvtb.f16.f32 s9, s13292; CHECK-MVE-NEXT: vcvtb.f16.f32 s10, s14293; CHECK-MVE-NEXT: vcvtb.f16.f32 s11, s15294; CHECK-MVE-NEXT: vcvtt.f16.f32 s8, s4295; CHECK-MVE-NEXT: vcvtt.f16.f32 s9, s5296; CHECK-MVE-NEXT: vcvtt.f16.f32 s10, s6297; CHECK-MVE-NEXT: vcvtt.f16.f32 s11, s7298; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s16299; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s17300; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s18301; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s19302; CHECK-MVE-NEXT: vmov q1, q2303; CHECK-MVE-NEXT: vpop {d8, d9}304; CHECK-MVE-NEXT: bx lr305;306; CHECK-MVEFP-LABEL: shuffle_trunc8:307; CHECK-MVEFP: @ %bb.0: @ %entry308; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q2, q2309; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q3, q3310; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q2, q0311; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q3, q1312; CHECK-MVEFP-NEXT: vmov q0, q2313; CHECK-MVEFP-NEXT: vmov q1, q3314; CHECK-MVEFP-NEXT: bx lr315entry:316 %out1 = fptrunc <8 x float> %src1 to <8 x half>317 %out2 = fptrunc <8 x float> %src2 to <8 x half>318 %s = shufflevector <8 x half> %out1, <8 x half> %out2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>319 ret <16 x half> %s320}321 322 323 324 325define arm_aapcs_vfpcc <4 x float> @load_ext_4(ptr %src) {326; CHECK-MVE-LABEL: load_ext_4:327; CHECK-MVE: @ %bb.0: @ %entry328; CHECK-MVE-NEXT: ldrd r0, r1, [r0]329; CHECK-MVE-NEXT: vmov.32 q0[0], r0330; CHECK-MVE-NEXT: vmov q1, q0331; CHECK-MVE-NEXT: vcvtt.f32.f16 s1, s0332; CHECK-MVE-NEXT: vmov.32 q1[1], r1333; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0334; CHECK-MVE-NEXT: vcvtt.f32.f16 s3, s5335; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s5336; CHECK-MVE-NEXT: bx lr337;338; CHECK-MVEFP-LABEL: load_ext_4:339; CHECK-MVEFP: @ %bb.0: @ %entry340; CHECK-MVEFP-NEXT: vldrh.u32 q0, [r0]341; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q0, q0342; CHECK-MVEFP-NEXT: bx lr343entry:344 %wide.load = load <4 x half>, ptr %src, align 4345 %e = fpext <4 x half> %wide.load to <4 x float>346 ret <4 x float> %e347}348 349define arm_aapcs_vfpcc <8 x float> @load_ext_8(ptr %src) {350; CHECK-MVE-LABEL: load_ext_8:351; CHECK-MVE: @ %bb.0: @ %entry352; CHECK-MVE-NEXT: vldrw.u32 q2, [r0]353; CHECK-MVE-NEXT: vcvtt.f32.f16 s3, s9354; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s9355; CHECK-MVE-NEXT: vcvtt.f32.f16 s1, s8356; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s8357; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s11358; CHECK-MVE-NEXT: vcvtb.f32.f16 s6, s11359; CHECK-MVE-NEXT: vcvtt.f32.f16 s5, s10360; CHECK-MVE-NEXT: vcvtb.f32.f16 s4, s10361; CHECK-MVE-NEXT: bx lr362;363; CHECK-MVEFP-LABEL: load_ext_8:364; CHECK-MVEFP: @ %bb.0: @ %entry365; CHECK-MVEFP-NEXT: vldrh.u32 q0, [r0]366; CHECK-MVEFP-NEXT: vldrh.u32 q1, [r0, #8]367; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q0, q0368; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q1, q1369; CHECK-MVEFP-NEXT: bx lr370entry:371 %wide.load = load <8 x half>, ptr %src, align 4372 %e = fpext <8 x half> %wide.load to <8 x float>373 ret <8 x float> %e374}375 376define arm_aapcs_vfpcc <16 x float> @load_ext_16(ptr %src) {377; CHECK-MVE-LABEL: load_ext_16:378; CHECK-MVE: @ %bb.0: @ %entry379; CHECK-MVE-NEXT: .vsave {d8, d9}380; CHECK-MVE-NEXT: vpush {d8, d9}381; CHECK-MVE-NEXT: vldrw.u32 q2, [r0], #16382; CHECK-MVE-NEXT: vldrw.u32 q4, [r0]383; CHECK-MVE-NEXT: vcvtt.f32.f16 s3, s9384; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s9385; CHECK-MVE-NEXT: vcvtt.f32.f16 s1, s8386; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s8387; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s11388; CHECK-MVE-NEXT: vcvtb.f32.f16 s6, s11389; CHECK-MVE-NEXT: vcvtt.f32.f16 s5, s10390; CHECK-MVE-NEXT: vcvtb.f32.f16 s4, s10391; CHECK-MVE-NEXT: vcvtt.f32.f16 s11, s17392; CHECK-MVE-NEXT: vcvtb.f32.f16 s10, s17393; CHECK-MVE-NEXT: vcvtt.f32.f16 s9, s16394; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s16395; CHECK-MVE-NEXT: vcvtt.f32.f16 s15, s19396; CHECK-MVE-NEXT: vcvtb.f32.f16 s14, s19397; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s18398; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s18399; CHECK-MVE-NEXT: vpop {d8, d9}400; CHECK-MVE-NEXT: bx lr401;402; CHECK-MVEFP-LABEL: load_ext_16:403; CHECK-MVEFP: @ %bb.0: @ %entry404; CHECK-MVEFP-NEXT: vldrh.u32 q0, [r0]405; CHECK-MVEFP-NEXT: vldrh.u32 q1, [r0, #8]406; CHECK-MVEFP-NEXT: vldrh.u32 q2, [r0, #16]407; CHECK-MVEFP-NEXT: vldrh.u32 q3, [r0, #24]408; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q0, q0409; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q1, q1410; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q2, q2411; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q3, q3412; CHECK-MVEFP-NEXT: bx lr413entry:414 %wide.load = load <16 x half>, ptr %src, align 4415 %e = fpext <16 x half> %wide.load to <16 x float>416 ret <16 x float> %e417}418 419define arm_aapcs_vfpcc <4 x float> @load_shuffleext_8(ptr %src) {420; CHECK-MVE-LABEL: load_shuffleext_8:421; CHECK-MVE: @ %bb.0: @ %entry422; CHECK-MVE-NEXT: vldrw.u32 q0, [r0]423; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3424; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2425; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1426; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0427; CHECK-MVE-NEXT: bx lr428;429; CHECK-MVEFP-LABEL: load_shuffleext_8:430; CHECK-MVEFP: @ %bb.0: @ %entry431; CHECK-MVEFP-NEXT: vldrw.u32 q0, [r0]432; CHECK-MVEFP-NEXT: vcvtb.f32.f16 q0, q0433; CHECK-MVEFP-NEXT: bx lr434entry:435 %wide.load = load <8 x half>, ptr %src, align 4436 %sh = shufflevector <8 x half> %wide.load, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>437 %e = fpext <4 x half> %sh to <4 x float>438 ret <4 x float> %e439}440 441define arm_aapcs_vfpcc <8 x float> @load_shuffleext_16(ptr %src) {442; CHECK-LABEL: load_shuffleext_16:443; CHECK: @ %bb.0: @ %entry444; CHECK-NEXT: vld20.16 {q2, q3}, [r0]445; CHECK-NEXT: vld21.16 {q2, q3}, [r0]446; CHECK-NEXT: vcvtt.f32.f16 s3, s9447; CHECK-NEXT: vcvtb.f32.f16 s2, s9448; CHECK-NEXT: vcvtt.f32.f16 s1, s8449; CHECK-NEXT: vcvtb.f32.f16 s0, s8450; CHECK-NEXT: vcvtt.f32.f16 s7, s11451; CHECK-NEXT: vcvtb.f32.f16 s6, s11452; CHECK-NEXT: vcvtt.f32.f16 s5, s10453; CHECK-NEXT: vcvtb.f32.f16 s4, s10454; CHECK-NEXT: bx lr455entry:456 %wide.load = load <16 x half>, ptr %src, align 4457 %sh = shufflevector <16 x half> %wide.load, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>458 %e = fpext <8 x half> %sh to <8 x float>459 ret <8 x float> %e460}461 462 463 464 465define arm_aapcs_vfpcc void @store_trunc_4(ptr %src, <4 x float> %val) {466; CHECK-MVE-LABEL: store_trunc_4:467; CHECK-MVE: @ %bb.0: @ %entry468; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0469; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s1470; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s2471; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s3472; CHECK-MVE-NEXT: vmov r1, r2, d0473; CHECK-MVE-NEXT: strd r1, r2, [r0]474; CHECK-MVE-NEXT: bx lr475;476; CHECK-MVEFP-LABEL: store_trunc_4:477; CHECK-MVEFP: @ %bb.0: @ %entry478; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0479; CHECK-MVEFP-NEXT: vstrh.32 q0, [r0]480; CHECK-MVEFP-NEXT: bx lr481entry:482 %e = fptrunc <4 x float> %val to <4 x half>483 store <4 x half> %e, ptr %src, align 4484 ret void485}486 487define arm_aapcs_vfpcc void @store_trunc_8(ptr %src, <8 x float> %val) {488; CHECK-MVE-LABEL: store_trunc_8:489; CHECK-MVE: @ %bb.0: @ %entry490; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0491; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s1492; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s2493; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s4494; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s3495; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s6496; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s5497; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7498; CHECK-MVE-NEXT: vstrw.32 q0, [r0]499; CHECK-MVE-NEXT: bx lr500;501; CHECK-MVEFP-LABEL: store_trunc_8:502; CHECK-MVEFP: @ %bb.0: @ %entry503; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1504; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0505; CHECK-MVEFP-NEXT: vstrh.32 q1, [r0, #8]506; CHECK-MVEFP-NEXT: vstrh.32 q0, [r0]507; CHECK-MVEFP-NEXT: bx lr508entry:509 %e = fptrunc <8 x float> %val to <8 x half>510 store <8 x half> %e, ptr %src, align 4511 ret void512}513 514define arm_aapcs_vfpcc void @store_trunc_16(ptr %src, <16 x float> %val) {515; CHECK-MVE-LABEL: store_trunc_16:516; CHECK-MVE: @ %bb.0: @ %entry517; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0518; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s1519; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s2520; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s4521; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s3522; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s6523; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s5524; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7525; CHECK-MVE-NEXT: vstrb.8 q0, [r0], #16526; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s8527; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s10528; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s12529; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s14530; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s9531; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s11532; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s13533; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s15534; CHECK-MVE-NEXT: vstrw.32 q0, [r0]535; CHECK-MVE-NEXT: bx lr536;537; CHECK-MVEFP-LABEL: store_trunc_16:538; CHECK-MVEFP: @ %bb.0: @ %entry539; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q3, q3540; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q2, q2541; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1542; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0543; CHECK-MVEFP-NEXT: vstrh.32 q3, [r0, #24]544; CHECK-MVEFP-NEXT: vstrh.32 q2, [r0, #16]545; CHECK-MVEFP-NEXT: vstrh.32 q1, [r0, #8]546; CHECK-MVEFP-NEXT: vstrh.32 q0, [r0]547; CHECK-MVEFP-NEXT: bx lr548entry:549 %e = fptrunc <16 x float> %val to <16 x half>550 store <16 x half> %e, ptr %src, align 4551 ret void552}553 554define arm_aapcs_vfpcc void @store_shuffletrunc_8(ptr %src, <4 x float> %val1, <4 x float> %val2) {555; CHECK-MVE-LABEL: store_shuffletrunc_8:556; CHECK-MVE: @ %bb.0: @ %entry557; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0558; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s1559; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2560; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s3561; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s4562; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s5563; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s6564; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7565; CHECK-MVE-NEXT: vstrw.32 q0, [r0]566; CHECK-MVE-NEXT: bx lr567;568; CHECK-MVEFP-LABEL: store_shuffletrunc_8:569; CHECK-MVEFP: @ %bb.0: @ %entry570; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0571; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q1572; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]573; CHECK-MVEFP-NEXT: bx lr574entry:575 %strided.vec = shufflevector <4 x float> %val1, <4 x float> %val2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>576 %out = fptrunc <8 x float> %strided.vec to <8 x half>577 store <8 x half> %out, ptr %src, align 4578 ret void579}580 581define arm_aapcs_vfpcc void @store_shuffletrunc_16(ptr %src, <8 x float> %val1, <8 x float> %val2) {582; CHECK-MVE-LABEL: store_shuffletrunc_16:583; CHECK-MVE: @ %bb.0: @ %entry584; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0585; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s1586; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2587; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s3588; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8589; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9590; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10591; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11592; CHECK-MVE-NEXT: vstrb.8 q0, [r0], #16593; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s4594; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s5595; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s6596; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s7597; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s12598; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s13599; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s14600; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s15601; CHECK-MVE-NEXT: vstrw.32 q0, [r0]602; CHECK-MVE-NEXT: bx lr603;604; CHECK-MVEFP-LABEL: store_shuffletrunc_16:605; CHECK-MVEFP: @ %bb.0: @ %entry606; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1607; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0608; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q3609; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q2610; CHECK-MVEFP-NEXT: vstrw.32 q1, [r0, #16]611; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]612; CHECK-MVEFP-NEXT: bx lr613entry:614 %strided.vec = shufflevector <8 x float> %val1, <8 x float> %val2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>615 %out = fptrunc <16 x float> %strided.vec to <16 x half>616 store <16 x half> %out, ptr %src, align 4617 ret void618}619