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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE4; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE5 6define arm_aapcs_vfpcc <4 x i32> @vdup_i32(i32 %src) {7; CHECK-LE-LABEL: vdup_i32:8; CHECK-LE: @ %bb.0: @ %entry9; CHECK-LE-NEXT: vdup.32 q0, r010; CHECK-LE-NEXT: bx lr11;12; CHECK-BE-LABEL: vdup_i32:13; CHECK-BE: @ %bb.0: @ %entry14; CHECK-BE-NEXT: vdup.32 q1, r015; CHECK-BE-NEXT: vrev64.32 q0, q116; CHECK-BE-NEXT: bx lr17entry:18 %0 = insertelement <4 x i32> undef, i32 %src, i32 019 %out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer20 ret <4 x i32> %out21}22 23define arm_aapcs_vfpcc <8 x i16> @vdup_i16(i16 %src) {24; CHECK-LE-LABEL: vdup_i16:25; CHECK-LE: @ %bb.0: @ %entry26; CHECK-LE-NEXT: vdup.16 q0, r027; CHECK-LE-NEXT: bx lr28;29; CHECK-BE-LABEL: vdup_i16:30; CHECK-BE: @ %bb.0: @ %entry31; CHECK-BE-NEXT: vdup.16 q1, r032; CHECK-BE-NEXT: vrev64.16 q0, q133; CHECK-BE-NEXT: bx lr34entry:35 %0 = insertelement <8 x i16> undef, i16 %src, i32 036 %out = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer37 ret <8 x i16> %out38}39 40define arm_aapcs_vfpcc <16 x i8> @vdup_i8(i8 %src) {41; CHECK-LE-LABEL: vdup_i8:42; CHECK-LE: @ %bb.0: @ %entry43; CHECK-LE-NEXT: vdup.8 q0, r044; CHECK-LE-NEXT: bx lr45;46; CHECK-BE-LABEL: vdup_i8:47; CHECK-BE: @ %bb.0: @ %entry48; CHECK-BE-NEXT: vdup.8 q1, r049; CHECK-BE-NEXT: vrev64.8 q0, q150; CHECK-BE-NEXT: bx lr51entry:52 %0 = insertelement <16 x i8> undef, i8 %src, i32 053 %out = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer54 ret <16 x i8> %out55}56 57define arm_aapcs_vfpcc <2 x i64> @vdup_i64(i64 %src) {58; CHECK-LE-LABEL: vdup_i64:59; CHECK-LE: @ %bb.0: @ %entry60; CHECK-LE-NEXT: vmov q0[2], q0[0], r0, r061; CHECK-LE-NEXT: vmov q0[3], q0[1], r1, r162; CHECK-LE-NEXT: bx lr63;64; CHECK-BE-LABEL: vdup_i64:65; CHECK-BE: @ %bb.0: @ %entry66; CHECK-BE-NEXT: vmov q1[2], q1[0], r0, r067; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r168; CHECK-BE-NEXT: vrev64.32 q0, q169; CHECK-BE-NEXT: bx lr70entry:71 %0 = insertelement <2 x i64> undef, i64 %src, i32 072 %out = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> zeroinitializer73 ret <2 x i64> %out74}75 76define arm_aapcs_vfpcc <4 x float> @vdup_f32_1(float %src) {77; CHECK-LE-LABEL: vdup_f32_1:78; CHECK-LE: @ %bb.0: @ %entry79; CHECK-LE-NEXT: vmov r0, s080; CHECK-LE-NEXT: vdup.32 q0, r081; CHECK-LE-NEXT: bx lr82;83; CHECK-BE-LABEL: vdup_f32_1:84; CHECK-BE: @ %bb.0: @ %entry85; CHECK-BE-NEXT: vmov r0, s086; CHECK-BE-NEXT: vdup.32 q1, r087; CHECK-BE-NEXT: vrev64.32 q0, q188; CHECK-BE-NEXT: bx lr89entry:90 %0 = insertelement <4 x float> undef, float %src, i32 091 %out = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer92 ret <4 x float> %out93}94 95define arm_aapcs_vfpcc <4 x float> @vdup_f32_2(float %src1, float %src2) {96; CHECK-LE-LABEL: vdup_f32_2:97; CHECK-LE: @ %bb.0: @ %entry98; CHECK-LE-NEXT: vadd.f32 s0, s0, s199; CHECK-LE-NEXT: vmov r0, s0100; CHECK-LE-NEXT: vdup.32 q0, r0101; CHECK-LE-NEXT: bx lr102;103; CHECK-BE-LABEL: vdup_f32_2:104; CHECK-BE: @ %bb.0: @ %entry105; CHECK-BE-NEXT: vadd.f32 s0, s0, s1106; CHECK-BE-NEXT: vmov r0, s0107; CHECK-BE-NEXT: vdup.32 q1, r0108; CHECK-BE-NEXT: vrev64.32 q0, q1109; CHECK-BE-NEXT: bx lr110entry:111 %0 = fadd float %src1, %src2112 %1 = insertelement <4 x float> undef, float %0, i32 0113 %out = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer114 ret <4 x float> %out115}116 117define arm_aapcs_vfpcc <4 x float> @vdup_f32_1bc(float %src) {118; CHECK-LE-LABEL: vdup_f32_1bc:119; CHECK-LE: @ %bb.0: @ %entry120; CHECK-LE-NEXT: vmov r0, s0121; CHECK-LE-NEXT: vdup.32 q0, r0122; CHECK-LE-NEXT: bx lr123;124; CHECK-BE-LABEL: vdup_f32_1bc:125; CHECK-BE: @ %bb.0: @ %entry126; CHECK-BE-NEXT: vmov r0, s0127; CHECK-BE-NEXT: vdup.32 q1, r0128; CHECK-BE-NEXT: vrev64.32 q0, q1129; CHECK-BE-NEXT: bx lr130entry:131 %srcbc = bitcast float %src to i32132 %0 = insertelement <4 x i32> undef, i32 %srcbc, i32 0133 %out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer134 %outbc = bitcast <4 x i32> %out to <4 x float>135 ret <4 x float> %outbc136}137 138define arm_aapcs_vfpcc <4 x float> @vdup_f32_2bc(float %src1, float %src2) {139; CHECK-LE-LABEL: vdup_f32_2bc:140; CHECK-LE: @ %bb.0: @ %entry141; CHECK-LE-NEXT: vadd.f32 s0, s0, s1142; CHECK-LE-NEXT: vmov r0, s0143; CHECK-LE-NEXT: vdup.32 q0, r0144; CHECK-LE-NEXT: bx lr145;146; CHECK-BE-LABEL: vdup_f32_2bc:147; CHECK-BE: @ %bb.0: @ %entry148; CHECK-BE-NEXT: vadd.f32 s0, s0, s1149; CHECK-BE-NEXT: vmov r0, s0150; CHECK-BE-NEXT: vdup.32 q1, r0151; CHECK-BE-NEXT: vrev64.32 q0, q1152; CHECK-BE-NEXT: bx lr153entry:154 %0 = fadd float %src1, %src2155 %bc = bitcast float %0 to i32156 %1 = insertelement <4 x i32> undef, i32 %bc, i32 0157 %out = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer158 %outbc = bitcast <4 x i32> %out to <4 x float>159 ret <4 x float> %outbc160}161 162define arm_aapcs_vfpcc <8 x half> @vdup_f16(half %0, half %1) {163; CHECK-LE-LABEL: vdup_f16:164; CHECK-LE: @ %bb.0: @ %entry165; CHECK-LE-NEXT: vadd.f16 s0, s0, s1166; CHECK-LE-NEXT: vmov.f16 r0, s0167; CHECK-LE-NEXT: vdup.16 q0, r0168; CHECK-LE-NEXT: bx lr169;170; CHECK-BE-LABEL: vdup_f16:171; CHECK-BE: @ %bb.0: @ %entry172; CHECK-BE-NEXT: vadd.f16 s0, s0, s1173; CHECK-BE-NEXT: vmov.f16 r0, s0174; CHECK-BE-NEXT: vdup.16 q1, r0175; CHECK-BE-NEXT: vrev64.16 q0, q1176; CHECK-BE-NEXT: bx lr177entry:178 %2 = fadd half %0, %1179 %3 = insertelement <8 x half> undef, half %2, i32 0180 %out = shufflevector <8 x half> %3, <8 x half> undef, <8 x i32> zeroinitializer181 ret <8 x half> %out182}183 184define arm_aapcs_vfpcc <8 x half> @vdup_f16_bc(half %0, half %1) {185; CHECK-LE-LABEL: vdup_f16_bc:186; CHECK-LE: @ %bb.0: @ %entry187; CHECK-LE-NEXT: vadd.f16 s0, s0, s1188; CHECK-LE-NEXT: vmov.f16 r0, s0189; CHECK-LE-NEXT: vdup.16 q0, r0190; CHECK-LE-NEXT: bx lr191;192; CHECK-BE-LABEL: vdup_f16_bc:193; CHECK-BE: @ %bb.0: @ %entry194; CHECK-BE-NEXT: vadd.f16 s0, s0, s1195; CHECK-BE-NEXT: vmov.f16 r0, s0196; CHECK-BE-NEXT: vdup.16 q1, r0197; CHECK-BE-NEXT: vrev64.16 q0, q1198; CHECK-BE-NEXT: bx lr199entry:200 %2 = fadd half %0, %1201 %bc = bitcast half %2 to i16202 %3 = insertelement <8 x i16> undef, i16 %bc, i32 0203 %out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer204 %outbc = bitcast <8 x i16> %out to <8 x half>205 ret <8 x half> %outbc206}207 208define arm_aapcs_vfpcc <2 x double> @vdup_f64(double %src) {209; CHECK-LABEL: vdup_f64:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmov.f32 s2, s0212; CHECK-NEXT: vmov.f32 s3, s1213; CHECK-NEXT: bx lr214entry:215 %0 = insertelement <2 x double> undef, double %src, i32 0216 %out = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer217 ret <2 x double> %out218}219 220 221 222define arm_aapcs_vfpcc <4 x i32> @vduplane_i32(<4 x i32> %src) {223; CHECK-LE-LABEL: vduplane_i32:224; CHECK-LE: @ %bb.0: @ %entry225; CHECK-LE-NEXT: vmov r0, s3226; CHECK-LE-NEXT: vdup.32 q0, r0227; CHECK-LE-NEXT: bx lr228;229; CHECK-BE-LABEL: vduplane_i32:230; CHECK-BE: @ %bb.0: @ %entry231; CHECK-BE-NEXT: vrev64.32 q1, q0232; CHECK-BE-NEXT: vmov r0, s7233; CHECK-BE-NEXT: vdup.32 q1, r0234; CHECK-BE-NEXT: vrev64.32 q0, q1235; CHECK-BE-NEXT: bx lr236entry:237 %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>238 ret <4 x i32> %out239}240 241define arm_aapcs_vfpcc <8 x i16> @vduplane_i16(<8 x i16> %src) {242; CHECK-LE-LABEL: vduplane_i16:243; CHECK-LE: @ %bb.0: @ %entry244; CHECK-LE-NEXT: vmov.u16 r0, q0[3]245; CHECK-LE-NEXT: vdup.16 q0, r0246; CHECK-LE-NEXT: bx lr247;248; CHECK-BE-LABEL: vduplane_i16:249; CHECK-BE: @ %bb.0: @ %entry250; CHECK-BE-NEXT: vrev64.16 q1, q0251; CHECK-BE-NEXT: vmov.u16 r0, q1[3]252; CHECK-BE-NEXT: vdup.16 q1, r0253; CHECK-BE-NEXT: vrev64.16 q0, q1254; CHECK-BE-NEXT: bx lr255entry:256 %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>257 ret <8 x i16> %out258}259 260define arm_aapcs_vfpcc <16 x i8> @vduplane_i8(<16 x i8> %src) {261; CHECK-LE-LABEL: vduplane_i8:262; CHECK-LE: @ %bb.0: @ %entry263; CHECK-LE-NEXT: vmov.u8 r0, q0[3]264; CHECK-LE-NEXT: vdup.8 q0, r0265; CHECK-LE-NEXT: bx lr266;267; CHECK-BE-LABEL: vduplane_i8:268; CHECK-BE: @ %bb.0: @ %entry269; CHECK-BE-NEXT: vrev64.8 q1, q0270; CHECK-BE-NEXT: vmov.u8 r0, q1[3]271; CHECK-BE-NEXT: vdup.8 q1, r0272; CHECK-BE-NEXT: vrev64.8 q0, q1273; CHECK-BE-NEXT: bx lr274entry:275 %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>276 ret <16 x i8> %out277}278 279define arm_aapcs_vfpcc <2 x i64> @vduplane_i64(<2 x i64> %src) {280; CHECK-LABEL: vduplane_i64:281; CHECK: @ %bb.0: @ %entry282; CHECK-NEXT: vmov.f32 s0, s2283; CHECK-NEXT: vmov.f32 s1, s3284; CHECK-NEXT: bx lr285entry:286 %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 1>287 ret <2 x i64> %out288}289 290define arm_aapcs_vfpcc <4 x float> @vduplane_f32(<4 x float> %src) {291; CHECK-LE-LABEL: vduplane_f32:292; CHECK-LE: @ %bb.0: @ %entry293; CHECK-LE-NEXT: vmov r0, s3294; CHECK-LE-NEXT: vdup.32 q0, r0295; CHECK-LE-NEXT: bx lr296;297; CHECK-BE-LABEL: vduplane_f32:298; CHECK-BE: @ %bb.0: @ %entry299; CHECK-BE-NEXT: vrev64.32 q1, q0300; CHECK-BE-NEXT: vmov r0, s7301; CHECK-BE-NEXT: vdup.32 q1, r0302; CHECK-BE-NEXT: vrev64.32 q0, q1303; CHECK-BE-NEXT: bx lr304entry:305 %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>306 ret <4 x float> %out307}308 309define arm_aapcs_vfpcc <8 x half> @vduplane_f16(<8 x half> %src) {310; CHECK-LE-LABEL: vduplane_f16:311; CHECK-LE: @ %bb.0: @ %entry312; CHECK-LE-NEXT: vmov.u16 r0, q0[3]313; CHECK-LE-NEXT: vdup.16 q0, r0314; CHECK-LE-NEXT: bx lr315;316; CHECK-BE-LABEL: vduplane_f16:317; CHECK-BE: @ %bb.0: @ %entry318; CHECK-BE-NEXT: vrev64.16 q1, q0319; CHECK-BE-NEXT: vmov.u16 r0, q1[3]320; CHECK-BE-NEXT: vdup.16 q1, r0321; CHECK-BE-NEXT: vrev64.16 q0, q1322; CHECK-BE-NEXT: bx lr323entry:324 %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>325 ret <8 x half> %out326}327 328define arm_aapcs_vfpcc <2 x double> @vduplane_f64(<2 x double> %src) {329; CHECK-LABEL: vduplane_f64:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vmov.f32 s0, s2332; CHECK-NEXT: vmov.f32 s1, s3333; CHECK-NEXT: bx lr334entry:335 %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 1, i32 1>336 ret <2 x double> %out337}338 339 340define arm_aapcs_vfpcc float @vdup_f32_extract(float %src) {341; CHECK-LABEL: vdup_f32_extract:342; CHECK: @ %bb.0: @ %entry343; CHECK-NEXT: bx lr344entry:345 %srcbc = bitcast float %src to i32346 %0 = insertelement <4 x i32> undef, i32 %srcbc, i32 0347 %out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer348 %outbc = bitcast <4 x i32> %out to <4 x float>349 %ext = extractelement <4 x float> %outbc, i32 2350 ret float %ext351}352 353define arm_aapcs_vfpcc half @vdup_f16_extract(half %0, half %1) {354; CHECK-LABEL: vdup_f16_extract:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: vadd.f16 s0, s0, s1357; CHECK-NEXT: bx lr358entry:359 %2 = fadd half %0, %1360 %bc = bitcast half %2 to i16361 %3 = insertelement <8 x i16> undef, i16 %bc, i32 0362 %out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer363 %outbc = bitcast <8 x i16> %out to <8 x half>364 %ext = extractelement <8 x half> %outbc, i32 2365 ret half %ext366}367 368 369define arm_aapcs_vfpcc <8 x i16> @bitcast_i64_v8i16(i64 %a) {370; CHECK-LE-LABEL: bitcast_i64_v8i16:371; CHECK-LE: @ %bb.0:372; CHECK-LE-NEXT: .pad #8373; CHECK-LE-NEXT: sub sp, #8374; CHECK-LE-NEXT: str r0, [sp]375; CHECK-LE-NEXT: mov r0, sp376; CHECK-LE-NEXT: vldrh.u32 q0, [r0]377; CHECK-LE-NEXT: vmov r0, s0378; CHECK-LE-NEXT: vdup.16 q0, r0379; CHECK-LE-NEXT: add sp, #8380; CHECK-LE-NEXT: bx lr381;382; CHECK-BE-LABEL: bitcast_i64_v8i16:383; CHECK-BE: @ %bb.0:384; CHECK-BE-NEXT: .pad #8385; CHECK-BE-NEXT: sub sp, #8386; CHECK-BE-NEXT: strd r0, r1, [sp]387; CHECK-BE-NEXT: mov r0, sp388; CHECK-BE-NEXT: vldrh.u32 q0, [r0]389; CHECK-BE-NEXT: vmov r0, s0390; CHECK-BE-NEXT: vdup.16 q1, r0391; CHECK-BE-NEXT: vrev64.16 q0, q1392; CHECK-BE-NEXT: add sp, #8393; CHECK-BE-NEXT: bx lr394 %b = bitcast i64 %a to <4 x i16>395 %r = shufflevector <4 x i16> %b, <4 x i16> poison, <8 x i32> zeroinitializer396 ret <8 x i16> %r397}398 399define arm_aapcs_vfpcc <8 x i16> @bitcast_i128_v8i16(i128 %a) {400; CHECK-LE-LABEL: bitcast_i128_v8i16:401; CHECK-LE: @ %bb.0:402; CHECK-LE-NEXT: vdup.16 q0, r0403; CHECK-LE-NEXT: bx lr404;405; CHECK-BE-LABEL: bitcast_i128_v8i16:406; CHECK-BE: @ %bb.0:407; CHECK-BE-NEXT: vmov.32 q0[0], r0408; CHECK-BE-NEXT: vrev32.16 q0, q0409; CHECK-BE-NEXT: vmov.u16 r0, q0[0]410; CHECK-BE-NEXT: vdup.16 q1, r0411; CHECK-BE-NEXT: vrev64.16 q0, q1412; CHECK-BE-NEXT: bx lr413 %b = bitcast i128 %a to <8 x i16>414 %r = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer415 ret <8 x i16> %r416}417 418define arm_aapcs_vfpcc <8 x i16> @bitcast_i64_v8i16_lane1(i64 %a) {419; CHECK-LE-LABEL: bitcast_i64_v8i16_lane1:420; CHECK-LE: @ %bb.0:421; CHECK-LE-NEXT: .pad #8422; CHECK-LE-NEXT: sub sp, #8423; CHECK-LE-NEXT: str r0, [sp]424; CHECK-LE-NEXT: mov r0, sp425; CHECK-LE-NEXT: vldrh.u32 q0, [r0]426; CHECK-LE-NEXT: vmov r0, s1427; CHECK-LE-NEXT: vdup.16 q0, r0428; CHECK-LE-NEXT: add sp, #8429; CHECK-LE-NEXT: bx lr430;431; CHECK-BE-LABEL: bitcast_i64_v8i16_lane1:432; CHECK-BE: @ %bb.0:433; CHECK-BE-NEXT: .pad #8434; CHECK-BE-NEXT: sub sp, #8435; CHECK-BE-NEXT: strd r0, r1, [sp]436; CHECK-BE-NEXT: mov r0, sp437; CHECK-BE-NEXT: vldrh.u32 q0, [r0]438; CHECK-BE-NEXT: vmov r0, s1439; CHECK-BE-NEXT: vdup.16 q1, r0440; CHECK-BE-NEXT: vrev64.16 q0, q1441; CHECK-BE-NEXT: add sp, #8442; CHECK-BE-NEXT: bx lr443 %b = bitcast i64 %a to <4 x i16>444 %r = shufflevector <4 x i16> %b, <4 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>445 ret <8 x i16> %r446}447 448define arm_aapcs_vfpcc <8 x i16> @bitcast_f64_v8i16(double %a) {449; CHECK-LE-LABEL: bitcast_f64_v8i16:450; CHECK-LE: @ %bb.0:451; CHECK-LE-NEXT: vmov.u16 r0, q0[0]452; CHECK-LE-NEXT: vdup.16 q0, r0453; CHECK-LE-NEXT: bx lr454;455; CHECK-BE-LABEL: bitcast_f64_v8i16:456; CHECK-BE: @ %bb.0:457; CHECK-BE-NEXT: vrev64.16 q1, q0458; CHECK-BE-NEXT: vmov.u16 r0, q1[0]459; CHECK-BE-NEXT: vdup.16 q1, r0460; CHECK-BE-NEXT: vrev64.16 q0, q1461; CHECK-BE-NEXT: bx lr462 %b = bitcast double %a to <4 x i16>463 %r = shufflevector <4 x i16> %b, <4 x i16> poison, <8 x i32> zeroinitializer464 ret <8 x i16> %r465}466 467define arm_aapcs_vfpcc <8 x half> @bitcast_i64_v8f16(i64 %a) {468; CHECK-LE-LABEL: bitcast_i64_v8f16:469; CHECK-LE: @ %bb.0:470; CHECK-LE-NEXT: vmov.32 q0[0], r0471; CHECK-LE-NEXT: vmov.u16 r0, q0[0]472; CHECK-LE-NEXT: vdup.16 q0, r0473; CHECK-LE-NEXT: bx lr474;475; CHECK-BE-LABEL: bitcast_i64_v8f16:476; CHECK-BE: @ %bb.0:477; CHECK-BE-NEXT: vmov.32 q0[0], r0478; CHECK-BE-NEXT: vrev32.16 q0, q0479; CHECK-BE-NEXT: vmov.u16 r0, q0[0]480; CHECK-BE-NEXT: vdup.16 q1, r0481; CHECK-BE-NEXT: vrev64.16 q0, q1482; CHECK-BE-NEXT: bx lr483 %b = bitcast i64 %a to <4 x half>484 %r = shufflevector <4 x half> %b, <4 x half> poison, <8 x i32> zeroinitializer485 ret <8 x half> %r486}487 488define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_v2f64(i64 %a) {489; CHECK-LE-LABEL: bitcast_i64_v2f64:490; CHECK-LE: @ %bb.0:491; CHECK-LE-NEXT: vmov q0[2], q0[0], r0, r0492; CHECK-LE-NEXT: vmov q0[3], q0[1], r1, r1493; CHECK-LE-NEXT: bx lr494;495; CHECK-BE-LABEL: bitcast_i64_v2f64:496; CHECK-BE: @ %bb.0:497; CHECK-BE-NEXT: vmov q1[2], q1[0], r0, r0498; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r1499; CHECK-BE-NEXT: vrev64.32 q0, q1500; CHECK-BE-NEXT: bx lr501 %b = bitcast i64 %a to <1 x i64>502 %r = shufflevector <1 x i64> %b, <1 x i64> poison, <2 x i32> zeroinitializer503 ret <2 x i64> %r504}505 506define arm_aapcs_vfpcc <2 x i64> @bitcast_v2f64_v2i64(<2 x double> %a) {507; CHECK-LABEL: bitcast_v2f64_v2i64:508; CHECK: @ %bb.0:509; CHECK-NEXT: vmov.f32 s2, s0510; CHECK-NEXT: vmov.f32 s3, s1511; CHECK-NEXT: bx lr512 %b = bitcast <2 x double> %a to <2 x i64>513 %r = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer514 ret <2 x i64> %r515}516 517define arm_aapcs_vfpcc <2 x i64> @bitcast_v8i16_v2i64(<8 x i16> %a) {518; CHECK-LABEL: bitcast_v8i16_v2i64:519; CHECK: @ %bb.0:520; CHECK-NEXT: vmov.f32 s2, s0521; CHECK-NEXT: vmov.f32 s3, s1522; CHECK-NEXT: bx lr523 %b = bitcast <8 x i16> %a to <2 x i64>524 %r = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer525 ret <2 x i64> %r526}527 528define arm_aapcs_vfpcc <8 x i16> @bitcast_v2f64_v8i16(<2 x i64> %a) {529; CHECK-LE-LABEL: bitcast_v2f64_v8i16:530; CHECK-LE: @ %bb.0:531; CHECK-LE-NEXT: vmov.u16 r0, q0[0]532; CHECK-LE-NEXT: vdup.16 q0, r0533; CHECK-LE-NEXT: bx lr534;535; CHECK-BE-LABEL: bitcast_v2f64_v8i16:536; CHECK-BE: @ %bb.0:537; CHECK-BE-NEXT: vrev64.16 q1, q0538; CHECK-BE-NEXT: vmov.u16 r0, q1[0]539; CHECK-BE-NEXT: vdup.16 q1, r0540; CHECK-BE-NEXT: vrev64.16 q0, q1541; CHECK-BE-NEXT: bx lr542 %b = bitcast <2 x i64> %a to <8 x i16>543 %r = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer544 ret <8 x i16> %r545}546 547define arm_aapcs_vfpcc <8 x i16> @other_max_case(i32 %blockSize) {548; CHECK-LE-LABEL: other_max_case:549; CHECK-LE: @ %bb.0:550; CHECK-LE-NEXT: vdup.16 q0, r0551; CHECK-LE-NEXT: bx lr552;553; CHECK-BE-LABEL: other_max_case:554; CHECK-BE: @ %bb.0:555; CHECK-BE-NEXT: vmov.32 q0[0], r0556; CHECK-BE-NEXT: vrev32.16 q0, q0557; CHECK-BE-NEXT: vmov.u16 r0, q0[0]558; CHECK-BE-NEXT: vdup.16 q1, r0559; CHECK-BE-NEXT: vrev64.16 q0, q1560; CHECK-BE-NEXT: bx lr561 %vec.blockSize = bitcast i32 %blockSize to <2 x i16>562 %.splat2 = shufflevector <2 x i16> %vec.blockSize, <2 x i16> poison, <8 x i32> zeroinitializer563 ret <8 x i16> %.splat2564}565