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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x) {5; CHECK-LABEL: add_v4i32_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vaddv.u32 r0, q08; CHECK-NEXT: bx lr9entry:10 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %x)11 ret i32 %z12}13 14define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x) {15; CHECK-LABEL: add_v4i32_v4i64_zext:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vaddlv.u32 r0, r1, q018; CHECK-NEXT: bx lr19entry:20 %xx = zext <4 x i32> %x to <4 x i64>21 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)22 ret i64 %z23}24 25define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x) {26; CHECK-LABEL: add_v4i32_v4i64_sext:27; CHECK: @ %bb.0: @ %entry28; CHECK-NEXT: vaddlv.s32 r0, r1, q029; CHECK-NEXT: bx lr30entry:31 %xx = sext <4 x i32> %x to <4 x i64>32 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)33 ret i64 %z34}35 36define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x) {37; CHECK-LABEL: add_v2i32_v2i64_zext:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: vmov.i64 q1, #0xffffffff40; CHECK-NEXT: vand q0, q0, q141; CHECK-NEXT: vmov r0, r1, d142; CHECK-NEXT: vmov r2, r3, d043; CHECK-NEXT: adds r0, r0, r244; CHECK-NEXT: adcs r1, r345; CHECK-NEXT: bx lr46entry:47 %xx = zext <2 x i32> %x to <2 x i64>48 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)49 ret i64 %z50}51 52define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x) {53; CHECK-LABEL: add_v2i32_v2i64_sext:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vmov r0, s056; CHECK-NEXT: vmov r2, s257; CHECK-NEXT: asrs r1, r0, #3158; CHECK-NEXT: adds r0, r0, r259; CHECK-NEXT: adc.w r1, r1, r2, asr #3160; CHECK-NEXT: bx lr61entry:62 %xx = sext <2 x i32> %x to <2 x i64>63 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)64 ret i64 %z65}66 67define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x) {68; CHECK-LABEL: add_v8i16_v8i32_zext:69; CHECK: @ %bb.0: @ %entry70; CHECK-NEXT: vaddv.u16 r0, q071; CHECK-NEXT: bx lr72entry:73 %xx = zext <8 x i16> %x to <8 x i32>74 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)75 ret i32 %z76}77 78define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x) {79; CHECK-LABEL: add_v8i16_v8i32_sext:80; CHECK: @ %bb.0: @ %entry81; CHECK-NEXT: vaddv.s16 r0, q082; CHECK-NEXT: bx lr83entry:84 %xx = sext <8 x i16> %x to <8 x i32>85 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)86 ret i32 %z87}88 89define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x) {90; CHECK-LABEL: add_v4i16_v4i32_zext:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmovlb.u16 q0, q093; CHECK-NEXT: vaddv.u32 r0, q094; CHECK-NEXT: bx lr95entry:96 %xx = zext <4 x i16> %x to <4 x i32>97 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)98 ret i32 %z99}100 101define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x) {102; CHECK-LABEL: add_v4i16_v4i32_sext:103; CHECK: @ %bb.0: @ %entry104; CHECK-NEXT: vmovlb.s16 q0, q0105; CHECK-NEXT: vaddv.u32 r0, q0106; CHECK-NEXT: bx lr107entry:108 %xx = sext <4 x i16> %x to <4 x i32>109 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)110 ret i32 %z111}112 113define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x) {114; CHECK-LABEL: add_v8i16_v8i16:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vaddv.u16 r0, q0117; CHECK-NEXT: uxth r0, r0118; CHECK-NEXT: bx lr119entry:120 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %x)121 ret i16 %z122}123 124define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_zext(<8 x i16> %x) {125; CHECK-LABEL: add_v8i16_v8i64_zext:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vmov.u16 r0, q0[1]128; CHECK-NEXT: vmov.u16 r1, q0[0]129; CHECK-NEXT: vmov q2[2], q2[0], r1, r0130; CHECK-NEXT: vmov.i64 q1, #0xffff131; CHECK-NEXT: vand q2, q2, q1132; CHECK-NEXT: vmov.u16 r3, q0[2]133; CHECK-NEXT: vmov r0, s10134; CHECK-NEXT: vmov r1, r2, d4135; CHECK-NEXT: add r0, r1136; CHECK-NEXT: vmov.u16 r1, q0[3]137; CHECK-NEXT: vmov q2[2], q2[0], r3, r1138; CHECK-NEXT: vmov.u16 r3, q0[4]139; CHECK-NEXT: vand q2, q2, q1140; CHECK-NEXT: vmov r1, s8141; CHECK-NEXT: add r0, r1142; CHECK-NEXT: vmov r1, s10143; CHECK-NEXT: add r0, r1144; CHECK-NEXT: vmov.u16 r1, q0[5]145; CHECK-NEXT: vmov q2[2], q2[0], r3, r1146; CHECK-NEXT: vand q2, q2, q1147; CHECK-NEXT: vmov r1, s8148; CHECK-NEXT: add r0, r1149; CHECK-NEXT: vmov r1, r3, d5150; CHECK-NEXT: adds r0, r0, r1151; CHECK-NEXT: adc.w r1, r2, r3152; CHECK-NEXT: vmov.u16 r2, q0[7]153; CHECK-NEXT: vmov.u16 r3, q0[6]154; CHECK-NEXT: vmov q0[2], q0[0], r3, r2155; CHECK-NEXT: vand q0, q0, q1156; CHECK-NEXT: vmov r2, r3, d0157; CHECK-NEXT: adds r0, r0, r2158; CHECK-NEXT: adcs r1, r3159; CHECK-NEXT: vmov r2, r3, d1160; CHECK-NEXT: adds r0, r0, r2161; CHECK-NEXT: adcs r1, r3162; CHECK-NEXT: bx lr163entry:164 %xx = zext <8 x i16> %x to <8 x i64>165 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)166 ret i64 %z167}168 169define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x) {170; CHECK-LABEL: add_v8i16_v8i64_sext:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vmov.s16 r0, q0[0]173; CHECK-NEXT: vmov.s16 r2, q0[1]174; CHECK-NEXT: asrs r1, r0, #31175; CHECK-NEXT: adds r0, r0, r2176; CHECK-NEXT: adc.w r1, r1, r2, asr #31177; CHECK-NEXT: vmov.s16 r2, q0[2]178; CHECK-NEXT: adds r0, r0, r2179; CHECK-NEXT: adc.w r1, r1, r2, asr #31180; CHECK-NEXT: vmov.s16 r2, q0[3]181; CHECK-NEXT: adds r0, r0, r2182; CHECK-NEXT: adc.w r1, r1, r2, asr #31183; CHECK-NEXT: vmov.s16 r2, q0[4]184; CHECK-NEXT: adds r0, r0, r2185; CHECK-NEXT: adc.w r1, r1, r2, asr #31186; CHECK-NEXT: vmov.s16 r2, q0[5]187; CHECK-NEXT: adds r0, r0, r2188; CHECK-NEXT: adc.w r1, r1, r2, asr #31189; CHECK-NEXT: vmov.s16 r2, q0[6]190; CHECK-NEXT: adds r0, r0, r2191; CHECK-NEXT: adc.w r1, r1, r2, asr #31192; CHECK-NEXT: vmov.s16 r2, q0[7]193; CHECK-NEXT: adds r0, r0, r2194; CHECK-NEXT: adc.w r1, r1, r2, asr #31195; CHECK-NEXT: bx lr196entry:197 %xx = sext <8 x i16> %x to <8 x i64>198 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)199 ret i64 %z200}201 202define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_zext(<4 x i16> %x) {203; CHECK-LABEL: add_v4i16_v4i64_zext:204; CHECK: @ %bb.0: @ %entry205; CHECK-NEXT: vmovlb.u16 q0, q0206; CHECK-NEXT: vaddlv.u32 r0, r1, q0207; CHECK-NEXT: bx lr208entry:209 %xx = zext <4 x i16> %x to <4 x i64>210 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)211 ret i64 %z212}213 214define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_sext(<4 x i16> %x) {215; CHECK-LABEL: add_v4i16_v4i64_sext:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vmovlb.s16 q0, q0218; CHECK-NEXT: vaddlv.s32 r0, r1, q0219; CHECK-NEXT: bx lr220entry:221 %xx = sext <4 x i16> %x to <4 x i64>222 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)223 ret i64 %z224}225 226define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x) {227; CHECK-LABEL: add_v2i16_v2i64_zext:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: vmov.i64 q1, #0xffff230; CHECK-NEXT: vand q0, q0, q1231; CHECK-NEXT: vmov r0, s2232; CHECK-NEXT: vmov r2, r1, d0233; CHECK-NEXT: add r0, r2234; CHECK-NEXT: bx lr235entry:236 %xx = zext <2 x i16> %x to <2 x i64>237 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)238 ret i64 %z239}240 241define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x) {242; CHECK-LABEL: add_v2i16_v2i64_sext:243; CHECK: @ %bb.0: @ %entry244; CHECK-NEXT: vmov r0, s0245; CHECK-NEXT: vmov r2, s2246; CHECK-NEXT: sxth r0, r0247; CHECK-NEXT: asrs r1, r0, #31248; CHECK-NEXT: sxth r2, r2249; CHECK-NEXT: adds r0, r0, r2250; CHECK-NEXT: adc.w r1, r1, r2, asr #31251; CHECK-NEXT: bx lr252entry:253 %xx = sext <2 x i16> %x to <2 x i64>254 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)255 ret i64 %z256}257 258define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x) {259; CHECK-LABEL: add_v16i8_v16i32_zext:260; CHECK: @ %bb.0: @ %entry261; CHECK-NEXT: vaddv.u8 r0, q0262; CHECK-NEXT: bx lr263entry:264 %xx = zext <16 x i8> %x to <16 x i32>265 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)266 ret i32 %z267}268 269define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x) {270; CHECK-LABEL: add_v16i8_v16i32_sext:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vaddv.s8 r0, q0273; CHECK-NEXT: bx lr274entry:275 %xx = sext <16 x i8> %x to <16 x i32>276 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)277 ret i32 %z278}279 280define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_zext(<8 x i8> %x) {281; CHECK-LABEL: add_v8i8_v8i32_zext:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: vmovlb.u8 q0, q0284; CHECK-NEXT: vaddv.u16 r0, q0285; CHECK-NEXT: bx lr286entry:287 %xx = zext <8 x i8> %x to <8 x i32>288 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)289 ret i32 %z290}291 292define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_sext(<8 x i8> %x) {293; CHECK-LABEL: add_v8i8_v8i32_sext:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vmovlb.s8 q0, q0296; CHECK-NEXT: vaddv.s16 r0, q0297; CHECK-NEXT: bx lr298entry:299 %xx = sext <8 x i8> %x to <8 x i32>300 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)301 ret i32 %z302}303 304define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x) {305; CHECK-LABEL: add_v4i8_v4i32_zext:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vmov.i32 q1, #0xff308; CHECK-NEXT: vand q0, q0, q1309; CHECK-NEXT: vaddv.u32 r0, q0310; CHECK-NEXT: bx lr311entry:312 %xx = zext <4 x i8> %x to <4 x i32>313 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)314 ret i32 %z315}316 317define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x) {318; CHECK-LABEL: add_v4i8_v4i32_sext:319; CHECK: @ %bb.0: @ %entry320; CHECK-NEXT: vmovlb.s8 q0, q0321; CHECK-NEXT: vmovlb.s16 q0, q0322; CHECK-NEXT: vaddv.u32 r0, q0323; CHECK-NEXT: bx lr324entry:325 %xx = sext <4 x i8> %x to <4 x i32>326 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)327 ret i32 %z328}329 330define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x) {331; CHECK-LABEL: add_v16i8_v16i16_zext:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vaddv.u8 r0, q0334; CHECK-NEXT: uxth r0, r0335; CHECK-NEXT: bx lr336entry:337 %xx = zext <16 x i8> %x to <16 x i16>338 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)339 ret i16 %z340}341 342define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x) {343; CHECK-LABEL: add_v16i8_v16i16_sext:344; CHECK: @ %bb.0: @ %entry345; CHECK-NEXT: vaddv.s8 r0, q0346; CHECK-NEXT: sxth r0, r0347; CHECK-NEXT: bx lr348entry:349 %xx = sext <16 x i8> %x to <16 x i16>350 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)351 ret i16 %z352}353 354define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x) {355; CHECK-LABEL: add_v8i8_v8i16_zext:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vmovlb.u8 q0, q0358; CHECK-NEXT: vaddv.u16 r0, q0359; CHECK-NEXT: uxth r0, r0360; CHECK-NEXT: bx lr361entry:362 %xx = zext <8 x i8> %x to <8 x i16>363 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)364 ret i16 %z365}366 367define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x) {368; CHECK-LABEL: add_v8i8_v8i16_sext:369; CHECK: @ %bb.0: @ %entry370; CHECK-NEXT: vmovlb.s8 q0, q0371; CHECK-NEXT: vaddv.u16 r0, q0372; CHECK-NEXT: sxth r0, r0373; CHECK-NEXT: bx lr374entry:375 %xx = sext <8 x i8> %x to <8 x i16>376 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)377 ret i16 %z378}379 380define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x) {381; CHECK-LABEL: add_v16i8_v16i8:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: vaddv.u8 r0, q0384; CHECK-NEXT: uxtb r0, r0385; CHECK-NEXT: bx lr386entry:387 %z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)388 ret i8 %z389}390 391define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_zext(<16 x i8> %x) {392; CHECK-LABEL: add_v16i8_v16i64_zext:393; CHECK: @ %bb.0: @ %entry394; CHECK-NEXT: vmov.u8 r0, q0[1]395; CHECK-NEXT: vmov.u8 r1, q0[0]396; CHECK-NEXT: vmov q2[2], q2[0], r1, r0397; CHECK-NEXT: vmov.i64 q1, #0xff398; CHECK-NEXT: vand q2, q2, q1399; CHECK-NEXT: vmov.u8 r3, q0[2]400; CHECK-NEXT: vmov r0, s10401; CHECK-NEXT: vmov r1, r2, d4402; CHECK-NEXT: add r0, r1403; CHECK-NEXT: vmov.u8 r1, q0[3]404; CHECK-NEXT: vmov q2[2], q2[0], r3, r1405; CHECK-NEXT: vmov.u8 r3, q0[4]406; CHECK-NEXT: vand q2, q2, q1407; CHECK-NEXT: vmov r1, s8408; CHECK-NEXT: add r0, r1409; CHECK-NEXT: vmov r1, s10410; CHECK-NEXT: add r0, r1411; CHECK-NEXT: vmov.u8 r1, q0[5]412; CHECK-NEXT: vmov q2[2], q2[0], r3, r1413; CHECK-NEXT: vand q2, q2, q1414; CHECK-NEXT: vmov r1, s8415; CHECK-NEXT: add r0, r1416; CHECK-NEXT: vmov r1, r3, d5417; CHECK-NEXT: adds r0, r0, r1418; CHECK-NEXT: adc.w r1, r2, r3419; CHECK-NEXT: vmov.u8 r2, q0[7]420; CHECK-NEXT: vmov.u8 r3, q0[6]421; CHECK-NEXT: vmov q2[2], q2[0], r3, r2422; CHECK-NEXT: vand q2, q2, q1423; CHECK-NEXT: vmov r2, r3, d4424; CHECK-NEXT: adds r0, r0, r2425; CHECK-NEXT: adcs r1, r3426; CHECK-NEXT: vmov r2, r3, d5427; CHECK-NEXT: adds r0, r0, r2428; CHECK-NEXT: vmov.u8 r2, q0[9]429; CHECK-NEXT: adcs r1, r3430; CHECK-NEXT: vmov.u8 r3, q0[8]431; CHECK-NEXT: vmov q2[2], q2[0], r3, r2432; CHECK-NEXT: vand q2, q2, q1433; CHECK-NEXT: vmov r2, r3, d4434; CHECK-NEXT: adds r0, r0, r2435; CHECK-NEXT: adcs r1, r3436; CHECK-NEXT: vmov r2, r3, d5437; CHECK-NEXT: adds r0, r0, r2438; CHECK-NEXT: vmov.u8 r2, q0[11]439; CHECK-NEXT: adcs r1, r3440; CHECK-NEXT: vmov.u8 r3, q0[10]441; CHECK-NEXT: vmov q2[2], q2[0], r3, r2442; CHECK-NEXT: vand q2, q2, q1443; CHECK-NEXT: vmov r2, r3, d4444; CHECK-NEXT: adds r0, r0, r2445; CHECK-NEXT: adcs r1, r3446; CHECK-NEXT: vmov r2, r3, d5447; CHECK-NEXT: adds r0, r0, r2448; CHECK-NEXT: vmov.u8 r2, q0[13]449; CHECK-NEXT: adcs r1, r3450; CHECK-NEXT: vmov.u8 r3, q0[12]451; CHECK-NEXT: vmov q2[2], q2[0], r3, r2452; CHECK-NEXT: vand q2, q2, q1453; CHECK-NEXT: vmov r2, r3, d4454; CHECK-NEXT: adds r0, r0, r2455; CHECK-NEXT: adcs r1, r3456; CHECK-NEXT: vmov r2, r3, d5457; CHECK-NEXT: adds r0, r0, r2458; CHECK-NEXT: vmov.u8 r2, q0[15]459; CHECK-NEXT: adcs r1, r3460; CHECK-NEXT: vmov.u8 r3, q0[14]461; CHECK-NEXT: vmov q0[2], q0[0], r3, r2462; CHECK-NEXT: vand q0, q0, q1463; CHECK-NEXT: vmov r2, r3, d0464; CHECK-NEXT: adds r0, r0, r2465; CHECK-NEXT: adcs r1, r3466; CHECK-NEXT: vmov r2, r3, d1467; CHECK-NEXT: adds r0, r0, r2468; CHECK-NEXT: adcs r1, r3469; CHECK-NEXT: bx lr470entry:471 %xx = zext <16 x i8> %x to <16 x i64>472 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)473 ret i64 %z474}475 476define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x) {477; CHECK-LABEL: add_v16i8_v16i64_sext:478; CHECK: @ %bb.0: @ %entry479; CHECK-NEXT: vmov.s8 r0, q0[0]480; CHECK-NEXT: vmov.s8 r2, q0[1]481; CHECK-NEXT: asrs r1, r0, #31482; CHECK-NEXT: adds r0, r0, r2483; CHECK-NEXT: adc.w r1, r1, r2, asr #31484; CHECK-NEXT: vmov.s8 r2, q0[2]485; CHECK-NEXT: adds r0, r0, r2486; CHECK-NEXT: adc.w r1, r1, r2, asr #31487; CHECK-NEXT: vmov.s8 r2, q0[3]488; CHECK-NEXT: adds r0, r0, r2489; CHECK-NEXT: adc.w r1, r1, r2, asr #31490; CHECK-NEXT: vmov.s8 r2, q0[4]491; CHECK-NEXT: adds r0, r0, r2492; CHECK-NEXT: adc.w r1, r1, r2, asr #31493; CHECK-NEXT: vmov.s8 r2, q0[5]494; CHECK-NEXT: adds r0, r0, r2495; CHECK-NEXT: adc.w r1, r1, r2, asr #31496; CHECK-NEXT: vmov.s8 r2, q0[6]497; CHECK-NEXT: adds r0, r0, r2498; CHECK-NEXT: adc.w r1, r1, r2, asr #31499; CHECK-NEXT: vmov.s8 r2, q0[7]500; CHECK-NEXT: adds r0, r0, r2501; CHECK-NEXT: adc.w r1, r1, r2, asr #31502; CHECK-NEXT: vmov.s8 r2, q0[8]503; CHECK-NEXT: adds r0, r0, r2504; CHECK-NEXT: adc.w r1, r1, r2, asr #31505; CHECK-NEXT: vmov.s8 r2, q0[9]506; CHECK-NEXT: adds r0, r0, r2507; CHECK-NEXT: adc.w r1, r1, r2, asr #31508; CHECK-NEXT: vmov.s8 r2, q0[10]509; CHECK-NEXT: adds r0, r0, r2510; CHECK-NEXT: adc.w r1, r1, r2, asr #31511; CHECK-NEXT: vmov.s8 r2, q0[11]512; CHECK-NEXT: adds r0, r0, r2513; CHECK-NEXT: adc.w r1, r1, r2, asr #31514; CHECK-NEXT: vmov.s8 r2, q0[12]515; CHECK-NEXT: adds r0, r0, r2516; CHECK-NEXT: adc.w r1, r1, r2, asr #31517; CHECK-NEXT: vmov.s8 r2, q0[13]518; CHECK-NEXT: adds r0, r0, r2519; CHECK-NEXT: adc.w r1, r1, r2, asr #31520; CHECK-NEXT: vmov.s8 r2, q0[14]521; CHECK-NEXT: adds r0, r0, r2522; CHECK-NEXT: adc.w r1, r1, r2, asr #31523; CHECK-NEXT: vmov.s8 r2, q0[15]524; CHECK-NEXT: adds r0, r0, r2525; CHECK-NEXT: adc.w r1, r1, r2, asr #31526; CHECK-NEXT: bx lr527entry:528 %xx = sext <16 x i8> %x to <16 x i64>529 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)530 ret i64 %z531}532 533define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_zext(<8 x i8> %x) {534; CHECK-LABEL: add_v8i8_v8i64_zext:535; CHECK: @ %bb.0: @ %entry536; CHECK-NEXT: vmovlb.u8 q0, q0537; CHECK-NEXT: vmov.i64 q1, #0xffff538; CHECK-NEXT: vmov.u16 r0, q0[1]539; CHECK-NEXT: vmov.u16 r1, q0[0]540; CHECK-NEXT: vmov q2[2], q2[0], r1, r0541; CHECK-NEXT: vmov.u16 r3, q0[2]542; CHECK-NEXT: vand q2, q2, q1543; CHECK-NEXT: vmov r0, s10544; CHECK-NEXT: vmov r1, r2, d4545; CHECK-NEXT: add r0, r1546; CHECK-NEXT: vmov.u16 r1, q0[3]547; CHECK-NEXT: vmov q2[2], q2[0], r3, r1548; CHECK-NEXT: vmov.u16 r3, q0[4]549; CHECK-NEXT: vand q2, q2, q1550; CHECK-NEXT: vmov r1, s8551; CHECK-NEXT: add r0, r1552; CHECK-NEXT: vmov r1, s10553; CHECK-NEXT: add r0, r1554; CHECK-NEXT: vmov.u16 r1, q0[5]555; CHECK-NEXT: vmov q2[2], q2[0], r3, r1556; CHECK-NEXT: vand q2, q2, q1557; CHECK-NEXT: vmov r1, s8558; CHECK-NEXT: add r0, r1559; CHECK-NEXT: vmov r1, r3, d5560; CHECK-NEXT: adds r0, r0, r1561; CHECK-NEXT: adc.w r1, r2, r3562; CHECK-NEXT: vmov.u16 r2, q0[7]563; CHECK-NEXT: vmov.u16 r3, q0[6]564; CHECK-NEXT: vmov q0[2], q0[0], r3, r2565; CHECK-NEXT: vand q0, q0, q1566; CHECK-NEXT: vmov r2, r3, d0567; CHECK-NEXT: adds r0, r0, r2568; CHECK-NEXT: adcs r1, r3569; CHECK-NEXT: vmov r2, r3, d1570; CHECK-NEXT: adds r0, r0, r2571; CHECK-NEXT: adcs r1, r3572; CHECK-NEXT: bx lr573entry:574 %xx = zext <8 x i8> %x to <8 x i64>575 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)576 ret i64 %z577}578 579define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_sext(<8 x i8> %x) {580; CHECK-LABEL: add_v8i8_v8i64_sext:581; CHECK: @ %bb.0: @ %entry582; CHECK-NEXT: vmov.u16 r0, q0[0]583; CHECK-NEXT: vmov.u16 r2, q0[1]584; CHECK-NEXT: sxtb r0, r0585; CHECK-NEXT: sxtb r2, r2586; CHECK-NEXT: asrs r1, r0, #31587; CHECK-NEXT: adds r0, r0, r2588; CHECK-NEXT: adc.w r1, r1, r2, asr #31589; CHECK-NEXT: vmov.u16 r2, q0[2]590; CHECK-NEXT: sxtb r2, r2591; CHECK-NEXT: adds r0, r0, r2592; CHECK-NEXT: adc.w r1, r1, r2, asr #31593; CHECK-NEXT: vmov.u16 r2, q0[3]594; CHECK-NEXT: sxtb r2, r2595; CHECK-NEXT: adds r0, r0, r2596; CHECK-NEXT: adc.w r1, r1, r2, asr #31597; CHECK-NEXT: vmov.u16 r2, q0[4]598; CHECK-NEXT: sxtb r2, r2599; CHECK-NEXT: adds r0, r0, r2600; CHECK-NEXT: adc.w r1, r1, r2, asr #31601; CHECK-NEXT: vmov.u16 r2, q0[5]602; CHECK-NEXT: sxtb r2, r2603; CHECK-NEXT: adds r0, r0, r2604; CHECK-NEXT: adc.w r1, r1, r2, asr #31605; CHECK-NEXT: vmov.u16 r2, q0[6]606; CHECK-NEXT: sxtb r2, r2607; CHECK-NEXT: adds r0, r0, r2608; CHECK-NEXT: adc.w r1, r1, r2, asr #31609; CHECK-NEXT: vmov.u16 r2, q0[7]610; CHECK-NEXT: sxtb r2, r2611; CHECK-NEXT: adds r0, r0, r2612; CHECK-NEXT: adc.w r1, r1, r2, asr #31613; CHECK-NEXT: bx lr614entry:615 %xx = sext <8 x i8> %x to <8 x i64>616 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)617 ret i64 %z618}619 620define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_zext(<4 x i8> %x) {621; CHECK-LABEL: add_v4i8_v4i64_zext:622; CHECK: @ %bb.0: @ %entry623; CHECK-NEXT: vmov.i32 q1, #0xff624; CHECK-NEXT: vand q0, q0, q1625; CHECK-NEXT: vaddlv.u32 r0, r1, q0626; CHECK-NEXT: bx lr627entry:628 %xx = zext <4 x i8> %x to <4 x i64>629 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)630 ret i64 %z631}632 633define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_sext(<4 x i8> %x) {634; CHECK-LABEL: add_v4i8_v4i64_sext:635; CHECK: @ %bb.0: @ %entry636; CHECK-NEXT: vmovlb.s8 q0, q0637; CHECK-NEXT: vmovlb.s16 q0, q0638; CHECK-NEXT: vaddlv.s32 r0, r1, q0639; CHECK-NEXT: bx lr640entry:641 %xx = sext <4 x i8> %x to <4 x i64>642 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)643 ret i64 %z644}645 646define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x) {647; CHECK-LABEL: add_v2i8_v2i64_zext:648; CHECK: @ %bb.0: @ %entry649; CHECK-NEXT: vmov.i64 q1, #0xff650; CHECK-NEXT: vand q0, q0, q1651; CHECK-NEXT: vmov r0, s2652; CHECK-NEXT: vmov r2, r1, d0653; CHECK-NEXT: add r0, r2654; CHECK-NEXT: bx lr655entry:656 %xx = zext <2 x i8> %x to <2 x i64>657 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)658 ret i64 %z659}660 661define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x) {662; CHECK-LABEL: add_v2i8_v2i64_sext:663; CHECK: @ %bb.0: @ %entry664; CHECK-NEXT: vmov r0, s0665; CHECK-NEXT: vmov r2, s2666; CHECK-NEXT: sxtb r0, r0667; CHECK-NEXT: asrs r1, r0, #31668; CHECK-NEXT: sxtb r2, r2669; CHECK-NEXT: adds r0, r0, r2670; CHECK-NEXT: adc.w r1, r1, r2, asr #31671; CHECK-NEXT: bx lr672entry:673 %xx = sext <2 x i8> %x to <2 x i64>674 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)675 ret i64 %z676}677 678define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x) {679; CHECK-LABEL: add_v2i64_v2i64:680; CHECK: @ %bb.0: @ %entry681; CHECK-NEXT: vmov r0, r1, d1682; CHECK-NEXT: vmov r2, r3, d0683; CHECK-NEXT: adds r0, r0, r2684; CHECK-NEXT: adcs r1, r3685; CHECK-NEXT: bx lr686entry:687 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %x)688 ret i64 %z689}690 691define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, i32 %a) {692; CHECK-LABEL: add_v4i32_v4i32_acc:693; CHECK: @ %bb.0: @ %entry694; CHECK-NEXT: vaddva.u32 r0, q0695; CHECK-NEXT: bx lr696entry:697 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %x)698 %r = add i32 %z, %a699 ret i32 %r700}701 702define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, i64 %a) {703; CHECK-LABEL: add_v4i32_v4i64_acc_zext:704; CHECK: @ %bb.0: @ %entry705; CHECK-NEXT: vaddlva.u32 r0, r1, q0706; CHECK-NEXT: bx lr707entry:708 %xx = zext <4 x i32> %x to <4 x i64>709 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)710 %r = add i64 %z, %a711 ret i64 %r712}713 714define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, i64 %a) {715; CHECK-LABEL: add_v4i32_v4i64_acc_sext:716; CHECK: @ %bb.0: @ %entry717; CHECK-NEXT: vaddlva.s32 r0, r1, q0718; CHECK-NEXT: bx lr719entry:720 %xx = sext <4 x i32> %x to <4 x i64>721 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)722 %r = add i64 %z, %a723 ret i64 %r724}725 726define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, i64 %a) {727; CHECK-LABEL: add_v2i32_v2i64_acc_zext:728; CHECK: @ %bb.0: @ %entry729; CHECK-NEXT: .save {r7, lr}730; CHECK-NEXT: push {r7, lr}731; CHECK-NEXT: vmov.i64 q1, #0xffffffff732; CHECK-NEXT: vand q0, q0, q1733; CHECK-NEXT: vmov lr, r12, d1734; CHECK-NEXT: vmov r3, r2, d0735; CHECK-NEXT: adds.w r3, r3, lr736; CHECK-NEXT: adc.w r2, r2, r12737; CHECK-NEXT: adds r0, r0, r3738; CHECK-NEXT: adcs r1, r2739; CHECK-NEXT: pop {r7, pc}740entry:741 %xx = zext <2 x i32> %x to <2 x i64>742 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)743 %r = add i64 %z, %a744 ret i64 %r745}746 747define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, i64 %a) {748; CHECK-LABEL: add_v2i32_v2i64_acc_sext:749; CHECK: @ %bb.0: @ %entry750; CHECK-NEXT: vmov r2, s0751; CHECK-NEXT: vmov r3, s2752; CHECK-NEXT: asr.w r12, r2, #31753; CHECK-NEXT: adds r2, r2, r3754; CHECK-NEXT: adc.w r3, r12, r3, asr #31755; CHECK-NEXT: adds r0, r0, r2756; CHECK-NEXT: adcs r1, r3757; CHECK-NEXT: bx lr758entry:759 %xx = sext <2 x i32> %x to <2 x i64>760 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)761 %r = add i64 %z, %a762 ret i64 %r763}764 765define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, i32 %a) {766; CHECK-LABEL: add_v8i16_v8i32_acc_zext:767; CHECK: @ %bb.0: @ %entry768; CHECK-NEXT: vaddva.u16 r0, q0769; CHECK-NEXT: bx lr770entry:771 %xx = zext <8 x i16> %x to <8 x i32>772 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)773 %r = add i32 %z, %a774 ret i32 %r775}776 777define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, i32 %a) {778; CHECK-LABEL: add_v8i16_v8i32_acc_sext:779; CHECK: @ %bb.0: @ %entry780; CHECK-NEXT: vaddva.s16 r0, q0781; CHECK-NEXT: bx lr782entry:783 %xx = sext <8 x i16> %x to <8 x i32>784 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)785 %r = add i32 %z, %a786 ret i32 %r787}788 789define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, i32 %a) {790; CHECK-LABEL: add_v4i16_v4i32_acc_zext:791; CHECK: @ %bb.0: @ %entry792; CHECK-NEXT: vmovlb.u16 q0, q0793; CHECK-NEXT: vaddva.u32 r0, q0794; CHECK-NEXT: bx lr795entry:796 %xx = zext <4 x i16> %x to <4 x i32>797 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)798 %r = add i32 %z, %a799 ret i32 %r800}801 802define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, i32 %a) {803; CHECK-LABEL: add_v4i16_v4i32_acc_sext:804; CHECK: @ %bb.0: @ %entry805; CHECK-NEXT: vmovlb.s16 q0, q0806; CHECK-NEXT: vaddva.u32 r0, q0807; CHECK-NEXT: bx lr808entry:809 %xx = sext <4 x i16> %x to <4 x i32>810 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)811 %r = add i32 %z, %a812 ret i32 %r813}814 815define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, i16 %a) {816; CHECK-LABEL: add_v8i16_v8i16_acc:817; CHECK: @ %bb.0: @ %entry818; CHECK-NEXT: vaddva.u16 r0, q0819; CHECK-NEXT: uxth r0, r0820; CHECK-NEXT: bx lr821entry:822 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %x)823 %r = add i16 %z, %a824 ret i16 %r825}826 827define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_zext(<8 x i16> %x, i64 %a) {828; CHECK-LABEL: add_v8i16_v8i64_acc_zext:829; CHECK: @ %bb.0: @ %entry830; CHECK-NEXT: .save {r7, lr}831; CHECK-NEXT: push {r7, lr}832; CHECK-NEXT: vmov.u16 r2, q0[1]833; CHECK-NEXT: vmov.u16 r3, q0[0]834; CHECK-NEXT: vmov q2[2], q2[0], r3, r2835; CHECK-NEXT: vmov.i64 q1, #0xffff836; CHECK-NEXT: vand q2, q2, q1837; CHECK-NEXT: vmov r2, s10838; CHECK-NEXT: vmov r3, r12, d4839; CHECK-NEXT: add.w lr, r3, r2840; CHECK-NEXT: vmov.u16 r3, q0[3]841; CHECK-NEXT: vmov.u16 r2, q0[2]842; CHECK-NEXT: vmov q2[2], q2[0], r2, r3843; CHECK-NEXT: vand q2, q2, q1844; CHECK-NEXT: vmov r2, s8845; CHECK-NEXT: vmov r3, s10846; CHECK-NEXT: add r2, lr847; CHECK-NEXT: add.w lr, r2, r3848; CHECK-NEXT: vmov.u16 r3, q0[5]849; CHECK-NEXT: vmov.u16 r2, q0[4]850; CHECK-NEXT: vmov q2[2], q2[0], r2, r3851; CHECK-NEXT: vand q2, q2, q1852; CHECK-NEXT: vmov r2, s8853; CHECK-NEXT: add lr, r2854; CHECK-NEXT: vmov r3, r2, d5855; CHECK-NEXT: adds.w lr, lr, r3856; CHECK-NEXT: vmov.u16 r3, q0[6]857; CHECK-NEXT: adc.w r12, r12, r2858; CHECK-NEXT: vmov.u16 r2, q0[7]859; CHECK-NEXT: vmov q0[2], q0[0], r3, r2860; CHECK-NEXT: vand q0, q0, q1861; CHECK-NEXT: vmov r2, r3, d0862; CHECK-NEXT: adds.w lr, lr, r2863; CHECK-NEXT: adc.w r12, r12, r3864; CHECK-NEXT: vmov r2, r3, d1865; CHECK-NEXT: adds.w r2, r2, lr866; CHECK-NEXT: adc.w r3, r3, r12867; CHECK-NEXT: adds r0, r0, r2868; CHECK-NEXT: adcs r1, r3869; CHECK-NEXT: pop {r7, pc}870entry:871 %xx = zext <8 x i16> %x to <8 x i64>872 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)873 %r = add i64 %z, %a874 ret i64 %r875}876 877define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, i64 %a) {878; CHECK-LABEL: add_v8i16_v8i64_acc_sext:879; CHECK: @ %bb.0: @ %entry880; CHECK-NEXT: .save {r7, lr}881; CHECK-NEXT: push {r7, lr}882; CHECK-NEXT: vmov.s16 r2, q0[0]883; CHECK-NEXT: vmov.s16 r3, q0[1]884; CHECK-NEXT: asr.w r12, r2, #31885; CHECK-NEXT: adds.w lr, r2, r3886; CHECK-NEXT: vmov.s16 r2, q0[2]887; CHECK-NEXT: adc.w r3, r12, r3, asr #31888; CHECK-NEXT: adds.w r12, lr, r2889; CHECK-NEXT: adc.w r2, r3, r2, asr #31890; CHECK-NEXT: vmov.s16 r3, q0[3]891; CHECK-NEXT: adds.w r12, r12, r3892; CHECK-NEXT: adc.w r2, r2, r3, asr #31893; CHECK-NEXT: vmov.s16 r3, q0[4]894; CHECK-NEXT: adds.w r12, r12, r3895; CHECK-NEXT: adc.w r2, r2, r3, asr #31896; CHECK-NEXT: vmov.s16 r3, q0[5]897; CHECK-NEXT: adds.w r12, r12, r3898; CHECK-NEXT: adc.w r2, r2, r3, asr #31899; CHECK-NEXT: vmov.s16 r3, q0[6]900; CHECK-NEXT: adds.w r12, r12, r3901; CHECK-NEXT: adc.w lr, r2, r3, asr #31902; CHECK-NEXT: vmov.s16 r3, q0[7]903; CHECK-NEXT: adds.w r2, r12, r3904; CHECK-NEXT: adc.w r3, lr, r3, asr #31905; CHECK-NEXT: adds r0, r0, r2906; CHECK-NEXT: adcs r1, r3907; CHECK-NEXT: pop {r7, pc}908entry:909 %xx = sext <8 x i16> %x to <8 x i64>910 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)911 %r = add i64 %z, %a912 ret i64 %r913}914 915define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_acc_zext(<4 x i16> %x, i64 %a) {916; CHECK-LABEL: add_v4i16_v4i64_acc_zext:917; CHECK: @ %bb.0: @ %entry918; CHECK-NEXT: vmovlb.u16 q0, q0919; CHECK-NEXT: vaddlva.u32 r0, r1, q0920; CHECK-NEXT: bx lr921entry:922 %xx = zext <4 x i16> %x to <4 x i64>923 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)924 %r = add i64 %z, %a925 ret i64 %r926}927 928define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_acc_sext(<4 x i16> %x, i64 %a) {929; CHECK-LABEL: add_v4i16_v4i64_acc_sext:930; CHECK: @ %bb.0: @ %entry931; CHECK-NEXT: vmovlb.s16 q0, q0932; CHECK-NEXT: vaddlva.s32 r0, r1, q0933; CHECK-NEXT: bx lr934entry:935 %xx = sext <4 x i16> %x to <4 x i64>936 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)937 %r = add i64 %z, %a938 ret i64 %r939}940 941define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, i64 %a) {942; CHECK-LABEL: add_v2i16_v2i64_acc_zext:943; CHECK: @ %bb.0: @ %entry944; CHECK-NEXT: vmov.i64 q1, #0xffff945; CHECK-NEXT: vand q0, q0, q1946; CHECK-NEXT: vmov r2, s2947; CHECK-NEXT: vmov r3, r12, d0948; CHECK-NEXT: add r2, r3949; CHECK-NEXT: adds r0, r0, r2950; CHECK-NEXT: adc.w r1, r1, r12951; CHECK-NEXT: bx lr952entry:953 %xx = zext <2 x i16> %x to <2 x i64>954 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)955 %r = add i64 %z, %a956 ret i64 %r957}958 959define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, i64 %a) {960; CHECK-LABEL: add_v2i16_v2i64_acc_sext:961; CHECK: @ %bb.0: @ %entry962; CHECK-NEXT: vmov r2, s0963; CHECK-NEXT: vmov r3, s2964; CHECK-NEXT: sxth r2, r2965; CHECK-NEXT: asr.w r12, r2, #31966; CHECK-NEXT: sxth r3, r3967; CHECK-NEXT: adds r2, r2, r3968; CHECK-NEXT: adc.w r3, r12, r3, asr #31969; CHECK-NEXT: adds r0, r0, r2970; CHECK-NEXT: adcs r1, r3971; CHECK-NEXT: bx lr972entry:973 %xx = sext <2 x i16> %x to <2 x i64>974 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)975 %r = add i64 %z, %a976 ret i64 %r977}978 979define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, i32 %a) {980; CHECK-LABEL: add_v16i8_v16i32_acc_zext:981; CHECK: @ %bb.0: @ %entry982; CHECK-NEXT: vaddva.u8 r0, q0983; CHECK-NEXT: bx lr984entry:985 %xx = zext <16 x i8> %x to <16 x i32>986 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)987 %r = add i32 %z, %a988 ret i32 %r989}990 991define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, i32 %a) {992; CHECK-LABEL: add_v16i8_v16i32_acc_sext:993; CHECK: @ %bb.0: @ %entry994; CHECK-NEXT: vaddva.s8 r0, q0995; CHECK-NEXT: bx lr996entry:997 %xx = sext <16 x i8> %x to <16 x i32>998 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)999 %r = add i32 %z, %a1000 ret i32 %r1001}1002 1003define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_acc_zext(<8 x i8> %x, i32 %a) {1004; CHECK-LABEL: add_v8i8_v8i32_acc_zext:1005; CHECK: @ %bb.0: @ %entry1006; CHECK-NEXT: vmovlb.u8 q0, q01007; CHECK-NEXT: vaddva.u16 r0, q01008; CHECK-NEXT: bx lr1009entry:1010 %xx = zext <8 x i8> %x to <8 x i32>1011 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)1012 %r = add i32 %z, %a1013 ret i32 %r1014}1015 1016define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_acc_sext(<8 x i8> %x, i32 %a) {1017; CHECK-LABEL: add_v8i8_v8i32_acc_sext:1018; CHECK: @ %bb.0: @ %entry1019; CHECK-NEXT: vmovlb.s8 q0, q01020; CHECK-NEXT: vaddva.s16 r0, q01021; CHECK-NEXT: bx lr1022entry:1023 %xx = sext <8 x i8> %x to <8 x i32>1024 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)1025 %r = add i32 %z, %a1026 ret i32 %r1027}1028 1029define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, i32 %a) {1030; CHECK-LABEL: add_v4i8_v4i32_acc_zext:1031; CHECK: @ %bb.0: @ %entry1032; CHECK-NEXT: vmov.i32 q1, #0xff1033; CHECK-NEXT: vand q0, q0, q11034; CHECK-NEXT: vaddva.u32 r0, q01035; CHECK-NEXT: bx lr1036entry:1037 %xx = zext <4 x i8> %x to <4 x i32>1038 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)1039 %r = add i32 %z, %a1040 ret i32 %r1041}1042 1043define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, i32 %a) {1044; CHECK-LABEL: add_v4i8_v4i32_acc_sext:1045; CHECK: @ %bb.0: @ %entry1046; CHECK-NEXT: vmovlb.s8 q0, q01047; CHECK-NEXT: vmovlb.s16 q0, q01048; CHECK-NEXT: vaddva.u32 r0, q01049; CHECK-NEXT: bx lr1050entry:1051 %xx = sext <4 x i8> %x to <4 x i32>1052 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)1053 %r = add i32 %z, %a1054 ret i32 %r1055}1056 1057define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_acc_zext(<16 x i8> %x, i16 %a) {1058; CHECK-LABEL: add_v16i8_v16i16_acc_zext:1059; CHECK: @ %bb.0: @ %entry1060; CHECK-NEXT: vaddva.u8 r0, q01061; CHECK-NEXT: uxth r0, r01062; CHECK-NEXT: bx lr1063entry:1064 %xx = zext <16 x i8> %x to <16 x i16>1065 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)1066 %r = add i16 %z, %a1067 ret i16 %r1068}1069 1070define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_acc_sext(<16 x i8> %x, i16 %a) {1071; CHECK-LABEL: add_v16i8_v16i16_acc_sext:1072; CHECK: @ %bb.0: @ %entry1073; CHECK-NEXT: vaddva.s8 r0, q01074; CHECK-NEXT: sxth r0, r01075; CHECK-NEXT: bx lr1076entry:1077 %xx = sext <16 x i8> %x to <16 x i16>1078 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)1079 %r = add i16 %z, %a1080 ret i16 %r1081}1082 1083define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, i16 %a) {1084; CHECK-LABEL: add_v8i8_v8i16_acc_zext:1085; CHECK: @ %bb.0: @ %entry1086; CHECK-NEXT: vmovlb.u8 q0, q01087; CHECK-NEXT: vaddva.u16 r0, q01088; CHECK-NEXT: uxth r0, r01089; CHECK-NEXT: bx lr1090entry:1091 %xx = zext <8 x i8> %x to <8 x i16>1092 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)1093 %r = add i16 %z, %a1094 ret i16 %r1095}1096 1097define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, i16 %a) {1098; CHECK-LABEL: add_v8i8_v8i16_acc_sext:1099; CHECK: @ %bb.0: @ %entry1100; CHECK-NEXT: vmovlb.s8 q0, q01101; CHECK-NEXT: vaddva.u16 r0, q01102; CHECK-NEXT: sxth r0, r01103; CHECK-NEXT: bx lr1104entry:1105 %xx = sext <8 x i8> %x to <8 x i16>1106 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)1107 %r = add i16 %z, %a1108 ret i16 %r1109}1110 1111define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, i8 %a) {1112; CHECK-LABEL: add_v16i8_v16i8_acc:1113; CHECK: @ %bb.0: @ %entry1114; CHECK-NEXT: vaddva.u8 r0, q01115; CHECK-NEXT: uxtb r0, r01116; CHECK-NEXT: bx lr1117entry:1118 %z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)1119 %r = add i8 %z, %a1120 ret i8 %r1121}1122 1123define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_zext(<16 x i8> %x, i64 %a) {1124; CHECK-LABEL: add_v16i8_v16i64_acc_zext:1125; CHECK: @ %bb.0: @ %entry1126; CHECK-NEXT: .save {r7, lr}1127; CHECK-NEXT: push {r7, lr}1128; CHECK-NEXT: vmov.u8 r2, q0[1]1129; CHECK-NEXT: vmov.u8 r3, q0[0]1130; CHECK-NEXT: vmov q2[2], q2[0], r3, r21131; CHECK-NEXT: vmov.i64 q1, #0xff1132; CHECK-NEXT: vand q2, q2, q11133; CHECK-NEXT: vmov r2, s101134; CHECK-NEXT: vmov r3, r12, d41135; CHECK-NEXT: add.w lr, r3, r21136; CHECK-NEXT: vmov.u8 r3, q0[3]1137; CHECK-NEXT: vmov.u8 r2, q0[2]1138; CHECK-NEXT: vmov q2[2], q2[0], r2, r31139; CHECK-NEXT: vand q2, q2, q11140; CHECK-NEXT: vmov r2, s81141; CHECK-NEXT: vmov r3, s101142; CHECK-NEXT: add r2, lr1143; CHECK-NEXT: add.w lr, r2, r31144; CHECK-NEXT: vmov.u8 r3, q0[5]1145; CHECK-NEXT: vmov.u8 r2, q0[4]1146; CHECK-NEXT: vmov q2[2], q2[0], r2, r31147; CHECK-NEXT: vand q2, q2, q11148; CHECK-NEXT: vmov r2, s81149; CHECK-NEXT: add lr, r21150; CHECK-NEXT: vmov r3, r2, d51151; CHECK-NEXT: adds.w lr, lr, r31152; CHECK-NEXT: vmov.u8 r3, q0[6]1153; CHECK-NEXT: adc.w r12, r12, r21154; CHECK-NEXT: vmov.u8 r2, q0[7]1155; CHECK-NEXT: vmov q2[2], q2[0], r3, r21156; CHECK-NEXT: vand q2, q2, q11157; CHECK-NEXT: vmov r2, r3, d41158; CHECK-NEXT: adds.w lr, lr, r21159; CHECK-NEXT: adc.w r12, r12, r31160; CHECK-NEXT: vmov r2, r3, d51161; CHECK-NEXT: adds.w lr, lr, r21162; CHECK-NEXT: vmov.u8 r2, q0[9]1163; CHECK-NEXT: adc.w r12, r12, r31164; CHECK-NEXT: vmov.u8 r3, q0[8]1165; CHECK-NEXT: vmov q2[2], q2[0], r3, r21166; CHECK-NEXT: vand q2, q2, q11167; CHECK-NEXT: vmov r2, r3, d41168; CHECK-NEXT: adds.w lr, lr, r21169; CHECK-NEXT: adc.w r12, r12, r31170; CHECK-NEXT: vmov r2, r3, d51171; CHECK-NEXT: adds.w lr, lr, r21172; CHECK-NEXT: vmov.u8 r2, q0[11]1173; CHECK-NEXT: adc.w r12, r12, r31174; CHECK-NEXT: vmov.u8 r3, q0[10]1175; CHECK-NEXT: vmov q2[2], q2[0], r3, r21176; CHECK-NEXT: vand q2, q2, q11177; CHECK-NEXT: vmov r2, r3, d41178; CHECK-NEXT: adds.w lr, lr, r21179; CHECK-NEXT: adc.w r12, r12, r31180; CHECK-NEXT: vmov r2, r3, d51181; CHECK-NEXT: adds.w lr, lr, r21182; CHECK-NEXT: vmov.u8 r2, q0[13]1183; CHECK-NEXT: adc.w r12, r12, r31184; CHECK-NEXT: vmov.u8 r3, q0[12]1185; CHECK-NEXT: vmov q2[2], q2[0], r3, r21186; CHECK-NEXT: vand q2, q2, q11187; CHECK-NEXT: vmov r2, r3, d41188; CHECK-NEXT: adds.w lr, lr, r21189; CHECK-NEXT: adc.w r12, r12, r31190; CHECK-NEXT: vmov r2, r3, d51191; CHECK-NEXT: adds.w lr, lr, r21192; CHECK-NEXT: vmov.u8 r2, q0[15]1193; CHECK-NEXT: adc.w r12, r12, r31194; CHECK-NEXT: vmov.u8 r3, q0[14]1195; CHECK-NEXT: vmov q0[2], q0[0], r3, r21196; CHECK-NEXT: vand q0, q0, q11197; CHECK-NEXT: vmov r2, r3, d01198; CHECK-NEXT: adds.w lr, lr, r21199; CHECK-NEXT: adc.w r12, r12, r31200; CHECK-NEXT: vmov r2, r3, d11201; CHECK-NEXT: adds.w r2, r2, lr1202; CHECK-NEXT: adc.w r3, r3, r121203; CHECK-NEXT: adds r0, r0, r21204; CHECK-NEXT: adcs r1, r31205; CHECK-NEXT: pop {r7, pc}1206entry:1207 %xx = zext <16 x i8> %x to <16 x i64>1208 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)1209 %r = add i64 %z, %a1210 ret i64 %r1211}1212 1213define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext(<16 x i8> %x, i64 %a) {1214; CHECK-LABEL: add_v16i8_v16i64_acc_sext:1215; CHECK: @ %bb.0: @ %entry1216; CHECK-NEXT: .save {r7, lr}1217; CHECK-NEXT: push {r7, lr}1218; CHECK-NEXT: vmov.s8 r2, q0[0]1219; CHECK-NEXT: vmov.s8 r3, q0[1]1220; CHECK-NEXT: asr.w r12, r2, #311221; CHECK-NEXT: adds.w lr, r2, r31222; CHECK-NEXT: vmov.s8 r2, q0[2]1223; CHECK-NEXT: adc.w r3, r12, r3, asr #311224; CHECK-NEXT: adds.w r12, lr, r21225; CHECK-NEXT: adc.w r2, r3, r2, asr #311226; CHECK-NEXT: vmov.s8 r3, q0[3]1227; CHECK-NEXT: adds.w r12, r12, r31228; CHECK-NEXT: adc.w r2, r2, r3, asr #311229; CHECK-NEXT: vmov.s8 r3, q0[4]1230; CHECK-NEXT: adds.w r12, r12, r31231; CHECK-NEXT: adc.w r2, r2, r3, asr #311232; CHECK-NEXT: vmov.s8 r3, q0[5]1233; CHECK-NEXT: adds.w r12, r12, r31234; CHECK-NEXT: adc.w r2, r2, r3, asr #311235; CHECK-NEXT: vmov.s8 r3, q0[6]1236; CHECK-NEXT: adds.w r12, r12, r31237; CHECK-NEXT: adc.w r2, r2, r3, asr #311238; CHECK-NEXT: vmov.s8 r3, q0[7]1239; CHECK-NEXT: adds.w r12, r12, r31240; CHECK-NEXT: adc.w r2, r2, r3, asr #311241; CHECK-NEXT: vmov.s8 r3, q0[8]1242; CHECK-NEXT: adds.w r12, r12, r31243; CHECK-NEXT: adc.w r2, r2, r3, asr #311244; CHECK-NEXT: vmov.s8 r3, q0[9]1245; CHECK-NEXT: adds.w r12, r12, r31246; CHECK-NEXT: adc.w r2, r2, r3, asr #311247; CHECK-NEXT: vmov.s8 r3, q0[10]1248; CHECK-NEXT: adds.w r12, r12, r31249; CHECK-NEXT: adc.w r2, r2, r3, asr #311250; CHECK-NEXT: vmov.s8 r3, q0[11]1251; CHECK-NEXT: adds.w r12, r12, r31252; CHECK-NEXT: adc.w r2, r2, r3, asr #311253; CHECK-NEXT: vmov.s8 r3, q0[12]1254; CHECK-NEXT: adds.w r12, r12, r31255; CHECK-NEXT: adc.w r2, r2, r3, asr #311256; CHECK-NEXT: vmov.s8 r3, q0[13]1257; CHECK-NEXT: adds.w r12, r12, r31258; CHECK-NEXT: adc.w r2, r2, r3, asr #311259; CHECK-NEXT: vmov.s8 r3, q0[14]1260; CHECK-NEXT: adds.w r12, r12, r31261; CHECK-NEXT: adc.w lr, r2, r3, asr #311262; CHECK-NEXT: vmov.s8 r3, q0[15]1263; CHECK-NEXT: adds.w r2, r12, r31264; CHECK-NEXT: adc.w r3, lr, r3, asr #311265; CHECK-NEXT: adds r0, r0, r21266; CHECK-NEXT: adcs r1, r31267; CHECK-NEXT: pop {r7, pc}1268entry:1269 %xx = sext <16 x i8> %x to <16 x i64>1270 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)1271 %r = add i64 %z, %a1272 ret i64 %r1273}1274 1275define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_acc_zext(<8 x i8> %x, i64 %a) {1276; CHECK-LABEL: add_v8i8_v8i64_acc_zext:1277; CHECK: @ %bb.0: @ %entry1278; CHECK-NEXT: .save {r7, lr}1279; CHECK-NEXT: push {r7, lr}1280; CHECK-NEXT: vmovlb.u8 q0, q01281; CHECK-NEXT: vmov.i64 q1, #0xffff1282; CHECK-NEXT: vmov.u16 r2, q0[1]1283; CHECK-NEXT: vmov.u16 r3, q0[0]1284; CHECK-NEXT: vmov q2[2], q2[0], r3, r21285; CHECK-NEXT: vand q2, q2, q11286; CHECK-NEXT: vmov r2, s101287; CHECK-NEXT: vmov r3, r12, d41288; CHECK-NEXT: add.w lr, r3, r21289; CHECK-NEXT: vmov.u16 r3, q0[3]1290; CHECK-NEXT: vmov.u16 r2, q0[2]1291; CHECK-NEXT: vmov q2[2], q2[0], r2, r31292; CHECK-NEXT: vand q2, q2, q11293; CHECK-NEXT: vmov r2, s81294; CHECK-NEXT: vmov r3, s101295; CHECK-NEXT: add r2, lr1296; CHECK-NEXT: add.w lr, r2, r31297; CHECK-NEXT: vmov.u16 r3, q0[5]1298; CHECK-NEXT: vmov.u16 r2, q0[4]1299; CHECK-NEXT: vmov q2[2], q2[0], r2, r31300; CHECK-NEXT: vand q2, q2, q11301; CHECK-NEXT: vmov r2, s81302; CHECK-NEXT: add lr, r21303; CHECK-NEXT: vmov r3, r2, d51304; CHECK-NEXT: adds.w lr, lr, r31305; CHECK-NEXT: vmov.u16 r3, q0[6]1306; CHECK-NEXT: adc.w r12, r12, r21307; CHECK-NEXT: vmov.u16 r2, q0[7]1308; CHECK-NEXT: vmov q0[2], q0[0], r3, r21309; CHECK-NEXT: vand q0, q0, q11310; CHECK-NEXT: vmov r2, r3, d01311; CHECK-NEXT: adds.w lr, lr, r21312; CHECK-NEXT: adc.w r12, r12, r31313; CHECK-NEXT: vmov r2, r3, d11314; CHECK-NEXT: adds.w r2, r2, lr1315; CHECK-NEXT: adc.w r3, r3, r121316; CHECK-NEXT: adds r0, r0, r21317; CHECK-NEXT: adcs r1, r31318; CHECK-NEXT: pop {r7, pc}1319entry:1320 %xx = zext <8 x i8> %x to <8 x i64>1321 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)1322 %r = add i64 %z, %a1323 ret i64 %r1324}1325 1326define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_acc_sext(<8 x i8> %x, i64 %a) {1327; CHECK-LABEL: add_v8i8_v8i64_acc_sext:1328; CHECK: @ %bb.0: @ %entry1329; CHECK-NEXT: .save {r7, lr}1330; CHECK-NEXT: push {r7, lr}1331; CHECK-NEXT: vmov.u16 r2, q0[0]1332; CHECK-NEXT: vmov.u16 r3, q0[1]1333; CHECK-NEXT: sxtb r2, r21334; CHECK-NEXT: sxtb r3, r31335; CHECK-NEXT: asr.w r12, r2, #311336; CHECK-NEXT: adds.w lr, r2, r31337; CHECK-NEXT: vmov.u16 r2, q0[2]1338; CHECK-NEXT: adc.w r3, r12, r3, asr #311339; CHECK-NEXT: sxtb r2, r21340; CHECK-NEXT: adds.w r12, lr, r21341; CHECK-NEXT: adc.w r2, r3, r2, asr #311342; CHECK-NEXT: vmov.u16 r3, q0[3]1343; CHECK-NEXT: sxtb r3, r31344; CHECK-NEXT: adds.w r12, r12, r31345; CHECK-NEXT: adc.w r2, r2, r3, asr #311346; CHECK-NEXT: vmov.u16 r3, q0[4]1347; CHECK-NEXT: sxtb r3, r31348; CHECK-NEXT: adds.w r12, r12, r31349; CHECK-NEXT: adc.w r2, r2, r3, asr #311350; CHECK-NEXT: vmov.u16 r3, q0[5]1351; CHECK-NEXT: sxtb r3, r31352; CHECK-NEXT: adds.w r12, r12, r31353; CHECK-NEXT: adc.w r2, r2, r3, asr #311354; CHECK-NEXT: vmov.u16 r3, q0[6]1355; CHECK-NEXT: sxtb r3, r31356; CHECK-NEXT: adds.w r12, r12, r31357; CHECK-NEXT: adc.w lr, r2, r3, asr #311358; CHECK-NEXT: vmov.u16 r3, q0[7]1359; CHECK-NEXT: sxtb r3, r31360; CHECK-NEXT: adds.w r2, r12, r31361; CHECK-NEXT: adc.w r3, lr, r3, asr #311362; CHECK-NEXT: adds r0, r0, r21363; CHECK-NEXT: adcs r1, r31364; CHECK-NEXT: pop {r7, pc}1365entry:1366 %xx = sext <8 x i8> %x to <8 x i64>1367 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)1368 %r = add i64 %z, %a1369 ret i64 %r1370}1371 1372define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_acc_zext(<4 x i8> %x, i64 %a) {1373; CHECK-LABEL: add_v4i8_v4i64_acc_zext:1374; CHECK: @ %bb.0: @ %entry1375; CHECK-NEXT: vmov.i32 q1, #0xff1376; CHECK-NEXT: vand q0, q0, q11377; CHECK-NEXT: vaddlva.u32 r0, r1, q01378; CHECK-NEXT: bx lr1379entry:1380 %xx = zext <4 x i8> %x to <4 x i64>1381 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)1382 %r = add i64 %z, %a1383 ret i64 %r1384}1385 1386define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_acc_sext(<4 x i8> %x, i64 %a) {1387; CHECK-LABEL: add_v4i8_v4i64_acc_sext:1388; CHECK: @ %bb.0: @ %entry1389; CHECK-NEXT: vmovlb.s8 q0, q01390; CHECK-NEXT: vmovlb.s16 q0, q01391; CHECK-NEXT: vaddlva.s32 r0, r1, q01392; CHECK-NEXT: bx lr1393entry:1394 %xx = sext <4 x i8> %x to <4 x i64>1395 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)1396 %r = add i64 %z, %a1397 ret i64 %r1398}1399 1400define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, i64 %a) {1401; CHECK-LABEL: add_v2i8_v2i64_acc_zext:1402; CHECK: @ %bb.0: @ %entry1403; CHECK-NEXT: vmov.i64 q1, #0xff1404; CHECK-NEXT: vand q0, q0, q11405; CHECK-NEXT: vmov r2, s21406; CHECK-NEXT: vmov r3, r12, d01407; CHECK-NEXT: add r2, r31408; CHECK-NEXT: adds r0, r0, r21409; CHECK-NEXT: adc.w r1, r1, r121410; CHECK-NEXT: bx lr1411entry:1412 %xx = zext <2 x i8> %x to <2 x i64>1413 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)1414 %r = add i64 %z, %a1415 ret i64 %r1416}1417 1418define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, i64 %a) {1419; CHECK-LABEL: add_v2i8_v2i64_acc_sext:1420; CHECK: @ %bb.0: @ %entry1421; CHECK-NEXT: vmov r2, s01422; CHECK-NEXT: vmov r3, s21423; CHECK-NEXT: sxtb r2, r21424; CHECK-NEXT: asr.w r12, r2, #311425; CHECK-NEXT: sxtb r3, r31426; CHECK-NEXT: adds r2, r2, r31427; CHECK-NEXT: adc.w r3, r12, r3, asr #311428; CHECK-NEXT: adds r0, r0, r21429; CHECK-NEXT: adcs r1, r31430; CHECK-NEXT: bx lr1431entry:1432 %xx = sext <2 x i8> %x to <2 x i64>1433 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)1434 %r = add i64 %z, %a1435 ret i64 %r1436}1437 1438define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, i64 %a) {1439; CHECK-LABEL: add_v2i64_v2i64_acc:1440; CHECK: @ %bb.0: @ %entry1441; CHECK-NEXT: .save {r7, lr}1442; CHECK-NEXT: push {r7, lr}1443; CHECK-NEXT: vmov lr, r12, d11444; CHECK-NEXT: vmov r3, r2, d01445; CHECK-NEXT: adds.w r3, r3, lr1446; CHECK-NEXT: adc.w r2, r2, r121447; CHECK-NEXT: adds r0, r0, r31448; CHECK-NEXT: adcs r1, r21449; CHECK-NEXT: pop {r7, pc}1450entry:1451 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %x)1452 %r = add i64 %z, %a1453 ret i64 %r1454}1455 1456declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)1457declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)1458declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)1459declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)1460declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)1461declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)1462declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)1463declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)1464declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)1465declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)1466