2623 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) {5; CHECK-LABEL: add_v4i32_v4i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vpt.i32 eq, q1, zr8; CHECK-NEXT: vaddvt.u32 r0, q09; CHECK-NEXT: bx lr10entry:11 %c = icmp eq <4 x i32> %b, zeroinitializer12 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer13 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)14 ret i32 %z15}16 17define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %b) {18; CHECK-LABEL: add_v4i32_v4i64_zext:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vpt.i32 eq, q1, zr21; CHECK-NEXT: vaddlvt.u32 r0, r1, q022; CHECK-NEXT: bx lr23entry:24 %c = icmp eq <4 x i32> %b, zeroinitializer25 %xx = zext <4 x i32> %x to <4 x i64>26 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer27 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)28 ret i64 %z29}30 31define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %b) {32; CHECK-LABEL: add_v4i32_v4i64_sext:33; CHECK: @ %bb.0: @ %entry34; CHECK-NEXT: vpt.i32 eq, q1, zr35; CHECK-NEXT: vaddlvt.s32 r0, r1, q036; CHECK-NEXT: bx lr37entry:38 %c = icmp eq <4 x i32> %b, zeroinitializer39 %xx = sext <4 x i32> %x to <4 x i64>40 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer41 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)42 ret i64 %z43}44 45define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %b) {46; CHECK-LABEL: add_v2i32_v2i64_zext:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vmov r0, s449; CHECK-NEXT: movs r1, #050; CHECK-NEXT: vmov.i64 q2, #0xffffffff51; CHECK-NEXT: vand q0, q0, q252; CHECK-NEXT: cmp r0, #053; CHECK-NEXT: csetm r0, eq54; CHECK-NEXT: bfi r1, r0, #0, #855; CHECK-NEXT: vmov r0, s656; CHECK-NEXT: vmov.i32 q1, #0x057; CHECK-NEXT: cmp r0, #058; CHECK-NEXT: csetm r0, eq59; CHECK-NEXT: bfi r1, r0, #8, #860; CHECK-NEXT: vmsr p0, r161; CHECK-NEXT: vpsel q0, q0, q162; CHECK-NEXT: vmov r0, r1, d163; CHECK-NEXT: vmov r2, r3, d064; CHECK-NEXT: adds r0, r0, r265; CHECK-NEXT: adcs r1, r366; CHECK-NEXT: bx lr67entry:68 %c = icmp eq <2 x i32> %b, zeroinitializer69 %xx = zext <2 x i32> %x to <2 x i64>70 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer71 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)72 ret i64 %z73}74 75define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %b) {76; CHECK-LABEL: add_v2i32_v2i64_sext:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vmov r0, s279; CHECK-NEXT: vmov r1, s080; CHECK-NEXT: vmov q0[2], q0[0], r1, r081; CHECK-NEXT: asrs r0, r0, #3182; CHECK-NEXT: asrs r1, r1, #3183; CHECK-NEXT: vmov q0[3], q0[1], r1, r084; CHECK-NEXT: vmov r0, s485; CHECK-NEXT: movs r1, #086; CHECK-NEXT: cmp r0, #087; CHECK-NEXT: csetm r0, eq88; CHECK-NEXT: bfi r1, r0, #0, #889; CHECK-NEXT: vmov r0, s690; CHECK-NEXT: vmov.i32 q1, #0x091; CHECK-NEXT: cmp r0, #092; CHECK-NEXT: csetm r0, eq93; CHECK-NEXT: bfi r1, r0, #8, #894; CHECK-NEXT: vmsr p0, r195; CHECK-NEXT: vpsel q0, q0, q196; CHECK-NEXT: vmov r0, r1, d197; CHECK-NEXT: vmov r2, r3, d098; CHECK-NEXT: adds r0, r0, r299; CHECK-NEXT: adcs r1, r3100; CHECK-NEXT: bx lr101entry:102 %c = icmp eq <2 x i32> %b, zeroinitializer103 %xx = sext <2 x i32> %x to <2 x i64>104 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer105 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)106 ret i64 %z107}108 109define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %b) {110; CHECK-LABEL: add_v8i16_v8i32_zext:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: vpt.i16 eq, q1, zr113; CHECK-NEXT: vaddvt.u16 r0, q0114; CHECK-NEXT: bx lr115entry:116 %c = icmp eq <8 x i16> %b, zeroinitializer117 %xx = zext <8 x i16> %x to <8 x i32>118 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer119 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)120 ret i32 %z121}122 123define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %b) {124; CHECK-LABEL: add_v8i16_v8i32_sext:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vpt.i16 eq, q1, zr127; CHECK-NEXT: vaddvt.s16 r0, q0128; CHECK-NEXT: bx lr129entry:130 %c = icmp eq <8 x i16> %b, zeroinitializer131 %xx = sext <8 x i16> %x to <8 x i32>132 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer133 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)134 ret i32 %z135}136 137define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %b) {138; CHECK-LABEL: add_v4i16_v4i32_zext:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vmovlb.u16 q1, q1141; CHECK-NEXT: vmovlb.u16 q0, q0142; CHECK-NEXT: vpt.i32 eq, q1, zr143; CHECK-NEXT: vaddvt.u32 r0, q0144; CHECK-NEXT: bx lr145entry:146 %c = icmp eq <4 x i16> %b, zeroinitializer147 %xx = zext <4 x i16> %x to <4 x i32>148 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer149 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)150 ret i32 %z151}152 153define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %b) {154; CHECK-LABEL: add_v4i16_v4i32_sext:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: vmovlb.u16 q1, q1157; CHECK-NEXT: vmovlb.s16 q0, q0158; CHECK-NEXT: vpt.i32 eq, q1, zr159; CHECK-NEXT: vaddvt.u32 r0, q0160; CHECK-NEXT: bx lr161entry:162 %c = icmp eq <4 x i16> %b, zeroinitializer163 %xx = sext <4 x i16> %x to <4 x i32>164 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer165 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)166 ret i32 %z167}168 169define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b) {170; CHECK-LABEL: add_v8i16_v8i16:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vpt.i16 eq, q1, zr173; CHECK-NEXT: vaddvt.u16 r0, q0174; CHECK-NEXT: uxth r0, r0175; CHECK-NEXT: bx lr176entry:177 %c = icmp eq <8 x i16> %b, zeroinitializer178 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer179 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)180 ret i16 %z181}182 183define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_zext(<8 x i16> %x, <8 x i16> %b) {184; CHECK-LABEL: add_v8i16_v8i64_zext:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}187; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}188; CHECK-NEXT: vmov.i8 q3, #0x0189; CHECK-NEXT: vmov.i8 q4, #0xff190; CHECK-NEXT: vcmp.i16 eq, q1, zr191; CHECK-NEXT: vpsel q5, q4, q3192; CHECK-NEXT: vmov.u16 r0, q5[2]193; CHECK-NEXT: vmov.u16 r1, q5[0]194; CHECK-NEXT: vmov q1[2], q1[0], r1, r0195; CHECK-NEXT: vmov.u16 r0, q5[3]196; CHECK-NEXT: vmov.u16 r1, q5[1]197; CHECK-NEXT: vmov q1[3], q1[1], r1, r0198; CHECK-NEXT: vcmp.i32 ne, q1, zr199; CHECK-NEXT: vpsel q6, q4, q3200; CHECK-NEXT: vmov r0, r1, d12201; CHECK-NEXT: vmov q1[2], q1[0], r0, r1202; CHECK-NEXT: vmov q1[3], q1[1], r0, r1203; CHECK-NEXT: vmov.u16 r0, q0[1]204; CHECK-NEXT: vmov.u16 r1, q0[0]205; CHECK-NEXT: vcmp.i32 ne, q1, zr206; CHECK-NEXT: vmov q2[2], q2[0], r1, r0207; CHECK-NEXT: vmov.i64 q1, #0xffff208; CHECK-NEXT: vand q7, q2, q1209; CHECK-NEXT: vmov.i32 q2, #0x0210; CHECK-NEXT: vpsel q7, q7, q2211; CHECK-NEXT: vmov r0, r1, d15212; CHECK-NEXT: vmov r2, r3, d14213; CHECK-NEXT: orrs r1, r3214; CHECK-NEXT: add r0, r2215; CHECK-NEXT: vmov r2, r3, d13216; CHECK-NEXT: vmov q6[2], q6[0], r2, r3217; CHECK-NEXT: vmov q6[3], q6[1], r2, r3218; CHECK-NEXT: vmov.u16 r2, q0[3]219; CHECK-NEXT: vmov.u16 r3, q0[2]220; CHECK-NEXT: vcmp.i32 ne, q6, zr221; CHECK-NEXT: vmov q6[2], q6[0], r3, r2222; CHECK-NEXT: vand q6, q6, q1223; CHECK-NEXT: vpsel q6, q6, q2224; CHECK-NEXT: vmov r2, r3, d12225; CHECK-NEXT: adds r0, r0, r2226; CHECK-NEXT: adcs r1, r3227; CHECK-NEXT: vmov r2, r3, d13228; CHECK-NEXT: adds r0, r0, r2229; CHECK-NEXT: vmov.u16 r2, q5[6]230; CHECK-NEXT: adcs r1, r3231; CHECK-NEXT: vmov.u16 r3, q5[4]232; CHECK-NEXT: vmov q6[2], q6[0], r3, r2233; CHECK-NEXT: vmov.u16 r2, q5[7]234; CHECK-NEXT: vmov.u16 r3, q5[5]235; CHECK-NEXT: vmov q6[3], q6[1], r3, r2236; CHECK-NEXT: vcmp.i32 ne, q6, zr237; CHECK-NEXT: vpsel q3, q4, q3238; CHECK-NEXT: vmov r2, r3, d6239; CHECK-NEXT: vmov q4[2], q4[0], r2, r3240; CHECK-NEXT: vmov q4[3], q4[1], r2, r3241; CHECK-NEXT: vmov.u16 r2, q0[5]242; CHECK-NEXT: vmov.u16 r3, q0[4]243; CHECK-NEXT: vcmp.i32 ne, q4, zr244; CHECK-NEXT: vmov q4[2], q4[0], r3, r2245; CHECK-NEXT: vand q4, q4, q1246; CHECK-NEXT: vpsel q4, q4, q2247; CHECK-NEXT: vmov r2, r3, d8248; CHECK-NEXT: adds r0, r0, r2249; CHECK-NEXT: adcs r1, r3250; CHECK-NEXT: vmov r2, r3, d9251; CHECK-NEXT: adds r0, r0, r2252; CHECK-NEXT: adcs r1, r3253; CHECK-NEXT: vmov r2, r3, d7254; CHECK-NEXT: vmov q3[2], q3[0], r2, r3255; CHECK-NEXT: vmov q3[3], q3[1], r2, r3256; CHECK-NEXT: vmov.u16 r2, q0[7]257; CHECK-NEXT: vmov.u16 r3, q0[6]258; CHECK-NEXT: vcmp.i32 ne, q3, zr259; CHECK-NEXT: vmov q0[2], q0[0], r3, r2260; CHECK-NEXT: vand q0, q0, q1261; CHECK-NEXT: vpsel q0, q0, q2262; CHECK-NEXT: vmov r2, r3, d0263; CHECK-NEXT: adds r0, r0, r2264; CHECK-NEXT: adcs r1, r3265; CHECK-NEXT: vmov r2, r3, d1266; CHECK-NEXT: adds r0, r0, r2267; CHECK-NEXT: adcs r1, r3268; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}269; CHECK-NEXT: bx lr270entry:271 %c = icmp eq <8 x i16> %b, zeroinitializer272 %xx = zext <8 x i16> %x to <8 x i64>273 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer274 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)275 ret i64 %z276}277 278define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x, <8 x i16> %b) {279; CHECK-LABEL: add_v8i16_v8i64_sext:280; CHECK: @ %bb.0: @ %entry281; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}282; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}283; CHECK-NEXT: vmov.i8 q2, #0x0284; CHECK-NEXT: vmov.i8 q3, #0xff285; CHECK-NEXT: vcmp.i16 eq, q1, zr286; CHECK-NEXT: vpsel q4, q3, q2287; CHECK-NEXT: vmov.u16 r0, q4[2]288; CHECK-NEXT: vmov.u16 r1, q4[0]289; CHECK-NEXT: vmov q1[2], q1[0], r1, r0290; CHECK-NEXT: vmov.u16 r0, q4[3]291; CHECK-NEXT: vmov.u16 r1, q4[1]292; CHECK-NEXT: vmov q1[3], q1[1], r1, r0293; CHECK-NEXT: vcmp.i32 ne, q1, zr294; CHECK-NEXT: vpsel q5, q3, q2295; CHECK-NEXT: vmov r0, r1, d10296; CHECK-NEXT: vmov q1[2], q1[0], r0, r1297; CHECK-NEXT: vmov q1[3], q1[1], r0, r1298; CHECK-NEXT: vmov.s16 r0, q0[1]299; CHECK-NEXT: vmov.s16 r1, q0[0]300; CHECK-NEXT: vcmp.i32 ne, q1, zr301; CHECK-NEXT: vmov q6[2], q6[0], r1, r0302; CHECK-NEXT: asrs r0, r0, #31303; CHECK-NEXT: asrs r1, r1, #31304; CHECK-NEXT: vmov.i32 q1, #0x0305; CHECK-NEXT: vmov q6[3], q6[1], r1, r0306; CHECK-NEXT: vpsel q6, q6, q1307; CHECK-NEXT: vmov r0, r1, d13308; CHECK-NEXT: vmov r2, r3, d12309; CHECK-NEXT: adds r0, r0, r2310; CHECK-NEXT: adcs r1, r3311; CHECK-NEXT: vmov r2, r3, d11312; CHECK-NEXT: vmov q5[2], q5[0], r2, r3313; CHECK-NEXT: vmov q5[3], q5[1], r2, r3314; CHECK-NEXT: vmov.s16 r2, q0[3]315; CHECK-NEXT: vmov.s16 r3, q0[2]316; CHECK-NEXT: vcmp.i32 ne, q5, zr317; CHECK-NEXT: vmov q5[2], q5[0], r3, r2318; CHECK-NEXT: asrs r2, r2, #31319; CHECK-NEXT: asrs r3, r3, #31320; CHECK-NEXT: vmov q5[3], q5[1], r3, r2321; CHECK-NEXT: vpsel q5, q5, q1322; CHECK-NEXT: vmov r2, r3, d10323; CHECK-NEXT: adds r0, r0, r2324; CHECK-NEXT: adcs r1, r3325; CHECK-NEXT: vmov r2, r3, d11326; CHECK-NEXT: adds r0, r0, r2327; CHECK-NEXT: vmov.u16 r2, q4[6]328; CHECK-NEXT: adcs r1, r3329; CHECK-NEXT: vmov.u16 r3, q4[4]330; CHECK-NEXT: vmov q5[2], q5[0], r3, r2331; CHECK-NEXT: vmov.u16 r2, q4[7]332; CHECK-NEXT: vmov.u16 r3, q4[5]333; CHECK-NEXT: vmov q5[3], q5[1], r3, r2334; CHECK-NEXT: vcmp.i32 ne, q5, zr335; CHECK-NEXT: vpsel q2, q3, q2336; CHECK-NEXT: vmov r2, r3, d4337; CHECK-NEXT: vmov q3[2], q3[0], r2, r3338; CHECK-NEXT: vmov q3[3], q3[1], r2, r3339; CHECK-NEXT: vmov.s16 r2, q0[5]340; CHECK-NEXT: vmov.s16 r3, q0[4]341; CHECK-NEXT: vcmp.i32 ne, q3, zr342; CHECK-NEXT: vmov q3[2], q3[0], r3, r2343; CHECK-NEXT: asrs r2, r2, #31344; CHECK-NEXT: asrs r3, r3, #31345; CHECK-NEXT: vmov q3[3], q3[1], r3, r2346; CHECK-NEXT: vpsel q3, q3, q1347; CHECK-NEXT: vmov r2, r3, d6348; CHECK-NEXT: adds r0, r0, r2349; CHECK-NEXT: adcs r1, r3350; CHECK-NEXT: vmov r2, r3, d7351; CHECK-NEXT: adds r0, r0, r2352; CHECK-NEXT: adcs r1, r3353; CHECK-NEXT: vmov r2, r3, d5354; CHECK-NEXT: vmov q2[2], q2[0], r2, r3355; CHECK-NEXT: vmov q2[3], q2[1], r2, r3356; CHECK-NEXT: vmov.s16 r2, q0[7]357; CHECK-NEXT: vmov.s16 r3, q0[6]358; CHECK-NEXT: vcmp.i32 ne, q2, zr359; CHECK-NEXT: vmov q0[2], q0[0], r3, r2360; CHECK-NEXT: asrs r2, r2, #31361; CHECK-NEXT: asrs r3, r3, #31362; CHECK-NEXT: vmov q0[3], q0[1], r3, r2363; CHECK-NEXT: vpsel q0, q0, q1364; CHECK-NEXT: vmov r2, r3, d0365; CHECK-NEXT: adds r0, r0, r2366; CHECK-NEXT: adcs r1, r3367; CHECK-NEXT: vmov r2, r3, d1368; CHECK-NEXT: adds r0, r0, r2369; CHECK-NEXT: adcs r1, r3370; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}371; CHECK-NEXT: bx lr372entry:373 %c = icmp eq <8 x i16> %b, zeroinitializer374 %xx = sext <8 x i16> %x to <8 x i64>375 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer376 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)377 ret i64 %z378}379 380define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_zext(<4 x i16> %x, <4 x i16> %b) {381; CHECK-LABEL: add_v4i16_v4i64_zext:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: vmovlb.u16 q1, q1384; CHECK-NEXT: vmovlb.u16 q0, q0385; CHECK-NEXT: vpt.i32 eq, q1, zr386; CHECK-NEXT: vaddlvt.u32 r0, r1, q0387; CHECK-NEXT: bx lr388entry:389 %c = icmp eq <4 x i16> %b, zeroinitializer390 %xx = zext <4 x i16> %x to <4 x i64>391 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer392 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)393 ret i64 %z394}395 396define arm_aapcs_vfpcc i64 @add_v4i16_v4i64_sext(<4 x i16> %x, <4 x i16> %b) {397; CHECK-LABEL: add_v4i16_v4i64_sext:398; CHECK: @ %bb.0: @ %entry399; CHECK-NEXT: vmovlb.u16 q1, q1400; CHECK-NEXT: vmovlb.s16 q0, q0401; CHECK-NEXT: vpt.i32 eq, q1, zr402; CHECK-NEXT: vaddlvt.s32 r0, r1, q0403; CHECK-NEXT: bx lr404entry:405 %c = icmp eq <4 x i16> %b, zeroinitializer406 %xx = sext <4 x i16> %x to <4 x i64>407 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer408 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)409 ret i64 %z410}411 412define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %b) {413; CHECK-LABEL: add_v2i16_v2i64_zext:414; CHECK: @ %bb.0: @ %entry415; CHECK-NEXT: vmov.i64 q2, #0xffff416; CHECK-NEXT: movs r1, #0417; CHECK-NEXT: vand q1, q1, q2418; CHECK-NEXT: vand q0, q0, q2419; CHECK-NEXT: vmov r0, s4420; CHECK-NEXT: cmp r0, #0421; CHECK-NEXT: csetm r0, eq422; CHECK-NEXT: bfi r1, r0, #0, #8423; CHECK-NEXT: vmov r0, s6424; CHECK-NEXT: vmov.i32 q1, #0x0425; CHECK-NEXT: cmp r0, #0426; CHECK-NEXT: csetm r0, eq427; CHECK-NEXT: bfi r1, r0, #8, #8428; CHECK-NEXT: vmsr p0, r1429; CHECK-NEXT: vpsel q0, q0, q1430; CHECK-NEXT: vmov r0, r1, d1431; CHECK-NEXT: vmov r2, r3, d0432; CHECK-NEXT: add r0, r2433; CHECK-NEXT: orrs r1, r3434; CHECK-NEXT: bx lr435entry:436 %c = icmp eq <2 x i16> %b, zeroinitializer437 %xx = zext <2 x i16> %x to <2 x i64>438 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer439 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)440 ret i64 %z441}442 443define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %b) {444; CHECK-LABEL: add_v2i16_v2i64_sext:445; CHECK: @ %bb.0: @ %entry446; CHECK-NEXT: vmov.i32 q2, #0xffff447; CHECK-NEXT: movs r1, #0448; CHECK-NEXT: vand q1, q1, q2449; CHECK-NEXT: vmov r0, s4450; CHECK-NEXT: cmp r0, #0451; CHECK-NEXT: csetm r0, eq452; CHECK-NEXT: bfi r1, r0, #0, #8453; CHECK-NEXT: vmov r0, s6454; CHECK-NEXT: vmov.i32 q1, #0x0455; CHECK-NEXT: cmp r0, #0456; CHECK-NEXT: csetm r0, eq457; CHECK-NEXT: bfi r1, r0, #8, #8458; CHECK-NEXT: vmov r0, s2459; CHECK-NEXT: vmsr p0, r1460; CHECK-NEXT: vmov r1, s0461; CHECK-NEXT: sxth r0, r0462; CHECK-NEXT: sxth r1, r1463; CHECK-NEXT: vmov q0[2], q0[0], r1, r0464; CHECK-NEXT: asrs r0, r0, #31465; CHECK-NEXT: asrs r1, r1, #31466; CHECK-NEXT: vmov q0[3], q0[1], r1, r0467; CHECK-NEXT: vpsel q0, q0, q1468; CHECK-NEXT: vmov r0, r1, d1469; CHECK-NEXT: vmov r2, r3, d0470; CHECK-NEXT: adds r0, r0, r2471; CHECK-NEXT: adcs r1, r3472; CHECK-NEXT: bx lr473entry:474 %c = icmp eq <2 x i16> %b, zeroinitializer475 %xx = sext <2 x i16> %x to <2 x i64>476 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer477 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)478 ret i64 %z479}480 481define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %b) {482; CHECK-LABEL: add_v16i8_v16i32_zext:483; CHECK: @ %bb.0: @ %entry484; CHECK-NEXT: vpt.i8 eq, q1, zr485; CHECK-NEXT: vaddvt.u8 r0, q0486; CHECK-NEXT: bx lr487entry:488 %c = icmp eq <16 x i8> %b, zeroinitializer489 %xx = zext <16 x i8> %x to <16 x i32>490 %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer491 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)492 ret i32 %z493}494 495define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %b) {496; CHECK-LABEL: add_v16i8_v16i32_sext:497; CHECK: @ %bb.0: @ %entry498; CHECK-NEXT: vpt.i8 eq, q1, zr499; CHECK-NEXT: vaddvt.s8 r0, q0500; CHECK-NEXT: bx lr501entry:502 %c = icmp eq <16 x i8> %b, zeroinitializer503 %xx = sext <16 x i8> %x to <16 x i32>504 %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer505 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)506 ret i32 %z507}508 509define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_zext(<8 x i8> %x, <8 x i8> %b) {510; CHECK-LABEL: add_v8i8_v8i32_zext:511; CHECK: @ %bb.0: @ %entry512; CHECK-NEXT: vmovlb.u8 q1, q1513; CHECK-NEXT: vmovlb.u8 q0, q0514; CHECK-NEXT: vpt.i16 eq, q1, zr515; CHECK-NEXT: vaddvt.u16 r0, q0516; CHECK-NEXT: bx lr517entry:518 %c = icmp eq <8 x i8> %b, zeroinitializer519 %xx = zext <8 x i8> %x to <8 x i32>520 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer521 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)522 ret i32 %z523}524 525define arm_aapcs_vfpcc i32 @add_v8i8_v8i32_sext(<8 x i8> %x, <8 x i8> %b) {526; CHECK-LABEL: add_v8i8_v8i32_sext:527; CHECK: @ %bb.0: @ %entry528; CHECK-NEXT: vmovlb.u8 q1, q1529; CHECK-NEXT: vmovlb.s8 q0, q0530; CHECK-NEXT: vpt.i16 eq, q1, zr531; CHECK-NEXT: vaddvt.s16 r0, q0532; CHECK-NEXT: bx lr533entry:534 %c = icmp eq <8 x i8> %b, zeroinitializer535 %xx = sext <8 x i8> %x to <8 x i32>536 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer537 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)538 ret i32 %z539}540 541define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %b) {542; CHECK-LABEL: add_v4i8_v4i32_zext:543; CHECK: @ %bb.0: @ %entry544; CHECK-NEXT: vmov.i32 q2, #0xff545; CHECK-NEXT: vand q1, q1, q2546; CHECK-NEXT: vand q0, q0, q2547; CHECK-NEXT: vpt.i32 eq, q1, zr548; CHECK-NEXT: vaddvt.u32 r0, q0549; CHECK-NEXT: bx lr550entry:551 %c = icmp eq <4 x i8> %b, zeroinitializer552 %xx = zext <4 x i8> %x to <4 x i32>553 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer554 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)555 ret i32 %z556}557 558define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %b) {559; CHECK-LABEL: add_v4i8_v4i32_sext:560; CHECK: @ %bb.0: @ %entry561; CHECK-NEXT: vmov.i32 q2, #0xff562; CHECK-NEXT: vmovlb.s8 q0, q0563; CHECK-NEXT: vand q1, q1, q2564; CHECK-NEXT: vmovlb.s16 q0, q0565; CHECK-NEXT: vpt.i32 eq, q1, zr566; CHECK-NEXT: vaddvt.u32 r0, q0567; CHECK-NEXT: bx lr568entry:569 %c = icmp eq <4 x i8> %b, zeroinitializer570 %xx = sext <4 x i8> %x to <4 x i32>571 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer572 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)573 ret i32 %z574}575 576define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x, <16 x i8> %b) {577; CHECK-LABEL: add_v16i8_v16i16_zext:578; CHECK: @ %bb.0: @ %entry579; CHECK-NEXT: vpt.i8 eq, q1, zr580; CHECK-NEXT: vaddvt.u8 r0, q0581; CHECK-NEXT: uxth r0, r0582; CHECK-NEXT: bx lr583entry:584 %c = icmp eq <16 x i8> %b, zeroinitializer585 %xx = zext <16 x i8> %x to <16 x i16>586 %s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer587 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)588 ret i16 %z589}590 591define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x, <16 x i8> %b) {592; CHECK-LABEL: add_v16i8_v16i16_sext:593; CHECK: @ %bb.0: @ %entry594; CHECK-NEXT: vpt.i8 eq, q1, zr595; CHECK-NEXT: vaddvt.s8 r0, q0596; CHECK-NEXT: sxth r0, r0597; CHECK-NEXT: bx lr598entry:599 %c = icmp eq <16 x i8> %b, zeroinitializer600 %xx = sext <16 x i8> %x to <16 x i16>601 %s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer602 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)603 ret i16 %z604}605 606define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %b) {607; CHECK-LABEL: add_v8i8_v8i16_zext:608; CHECK: @ %bb.0: @ %entry609; CHECK-NEXT: vmovlb.u8 q1, q1610; CHECK-NEXT: vmovlb.u8 q0, q0611; CHECK-NEXT: vpt.i16 eq, q1, zr612; CHECK-NEXT: vaddvt.u16 r0, q0613; CHECK-NEXT: uxth r0, r0614; CHECK-NEXT: bx lr615entry:616 %c = icmp eq <8 x i8> %b, zeroinitializer617 %xx = zext <8 x i8> %x to <8 x i16>618 %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer619 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)620 ret i16 %z621}622 623define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %b) {624; CHECK-LABEL: add_v8i8_v8i16_sext:625; CHECK: @ %bb.0: @ %entry626; CHECK-NEXT: vmovlb.u8 q1, q1627; CHECK-NEXT: vmovlb.s8 q0, q0628; CHECK-NEXT: vpt.i16 eq, q1, zr629; CHECK-NEXT: vaddvt.u16 r0, q0630; CHECK-NEXT: sxth r0, r0631; CHECK-NEXT: bx lr632entry:633 %c = icmp eq <8 x i8> %b, zeroinitializer634 %xx = sext <8 x i8> %x to <8 x i16>635 %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer636 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)637 ret i16 %z638}639 640define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) {641; CHECK-LABEL: add_v16i8_v16i8:642; CHECK: @ %bb.0: @ %entry643; CHECK-NEXT: vpt.i8 eq, q1, zr644; CHECK-NEXT: vaddvt.u8 r0, q0645; CHECK-NEXT: uxtb r0, r0646; CHECK-NEXT: bx lr647entry:648 %c = icmp eq <16 x i8> %b, zeroinitializer649 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer650 %z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)651 ret i8 %z652}653 654define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_zext(<16 x i8> %x, <16 x i8> %b) {655; CHECK-LABEL: add_v16i8_v16i64_zext:656; CHECK: @ %bb.0: @ %entry657; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}658; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}659; CHECK-NEXT: vmov q2, q0660; CHECK-NEXT: vcmp.i8 eq, q1, zr661; CHECK-NEXT: vmov.i8 q0, #0x0662; CHECK-NEXT: vmov.i8 q1, #0xff663; CHECK-NEXT: vpsel q5, q1, q0664; CHECK-NEXT: vmov.i8 q0, #0x0665; CHECK-NEXT: vmov.u8 r0, q5[0]666; CHECK-NEXT: vmov.16 q3[0], r0667; CHECK-NEXT: vmov.u8 r0, q5[1]668; CHECK-NEXT: vmov.16 q3[1], r0669; CHECK-NEXT: vmov.u8 r0, q5[2]670; CHECK-NEXT: vmov.16 q3[2], r0671; CHECK-NEXT: vmov.u8 r0, q5[3]672; CHECK-NEXT: vmov.16 q3[3], r0673; CHECK-NEXT: vmov.u8 r0, q5[4]674; CHECK-NEXT: vmov.16 q3[4], r0675; CHECK-NEXT: vmov.u8 r0, q5[5]676; CHECK-NEXT: vmov.16 q3[5], r0677; CHECK-NEXT: vmov.u8 r0, q5[6]678; CHECK-NEXT: vmov.16 q3[6], r0679; CHECK-NEXT: vmov.u8 r0, q5[7]680; CHECK-NEXT: vmov.16 q3[7], r0681; CHECK-NEXT: vcmp.i16 ne, q3, zr682; CHECK-NEXT: vpsel q6, q1, q0683; CHECK-NEXT: vmov.u16 r0, q6[2]684; CHECK-NEXT: vmov.u16 r1, q6[0]685; CHECK-NEXT: vmov q3[2], q3[0], r1, r0686; CHECK-NEXT: vmov.u16 r0, q6[3]687; CHECK-NEXT: vmov.u16 r1, q6[1]688; CHECK-NEXT: vmov q3[3], q3[1], r1, r0689; CHECK-NEXT: vcmp.i32 ne, q3, zr690; CHECK-NEXT: vpsel q7, q1, q0691; CHECK-NEXT: vmov r0, r1, d14692; CHECK-NEXT: vmov q3[2], q3[0], r0, r1693; CHECK-NEXT: vmov q3[3], q3[1], r0, r1694; CHECK-NEXT: vmov.u8 r0, q2[1]695; CHECK-NEXT: vmov.u8 r1, q2[0]696; CHECK-NEXT: vcmp.i32 ne, q3, zr697; CHECK-NEXT: vmov q4[2], q4[0], r1, r0698; CHECK-NEXT: vmov.i64 q3, #0xff699; CHECK-NEXT: vand q0, q4, q3700; CHECK-NEXT: vmov.i32 q4, #0x0701; CHECK-NEXT: vpsel q0, q0, q4702; CHECK-NEXT: vmov r0, r1, d1703; CHECK-NEXT: vmov r2, r3, d0704; CHECK-NEXT: orrs r1, r3705; CHECK-NEXT: add r0, r2706; CHECK-NEXT: vmov r2, r3, d15707; CHECK-NEXT: vmov.i8 q7, #0x0708; CHECK-NEXT: vmov q0[2], q0[0], r2, r3709; CHECK-NEXT: vmov q0[3], q0[1], r2, r3710; CHECK-NEXT: vmov.u8 r2, q2[3]711; CHECK-NEXT: vmov.u8 r3, q2[2]712; CHECK-NEXT: vcmp.i32 ne, q0, zr713; CHECK-NEXT: vmov q0[2], q0[0], r3, r2714; CHECK-NEXT: vand q0, q0, q3715; CHECK-NEXT: vpsel q0, q0, q4716; CHECK-NEXT: vmov r2, r3, d0717; CHECK-NEXT: adds r0, r0, r2718; CHECK-NEXT: adcs r1, r3719; CHECK-NEXT: vmov r2, r3, d1720; CHECK-NEXT: adds r0, r0, r2721; CHECK-NEXT: vmov.u16 r2, q6[6]722; CHECK-NEXT: adcs r1, r3723; CHECK-NEXT: vmov.u16 r3, q6[4]724; CHECK-NEXT: vmov q0[2], q0[0], r3, r2725; CHECK-NEXT: vmov.u16 r2, q6[7]726; CHECK-NEXT: vmov.u16 r3, q6[5]727; CHECK-NEXT: vmov q0[3], q0[1], r3, r2728; CHECK-NEXT: vcmp.i32 ne, q0, zr729; CHECK-NEXT: vpsel q6, q1, q7730; CHECK-NEXT: vmov r2, r3, d12731; CHECK-NEXT: vmov q0[2], q0[0], r2, r3732; CHECK-NEXT: vmov q0[3], q0[1], r2, r3733; CHECK-NEXT: vmov.u8 r2, q2[5]734; CHECK-NEXT: vmov.u8 r3, q2[4]735; CHECK-NEXT: vcmp.i32 ne, q0, zr736; CHECK-NEXT: vmov q0[2], q0[0], r3, r2737; CHECK-NEXT: vand q0, q0, q3738; CHECK-NEXT: vpsel q0, q0, q4739; CHECK-NEXT: vmov r2, r3, d0740; CHECK-NEXT: adds r0, r0, r2741; CHECK-NEXT: adcs r1, r3742; CHECK-NEXT: vmov r2, r3, d1743; CHECK-NEXT: adds r0, r0, r2744; CHECK-NEXT: adcs r1, r3745; CHECK-NEXT: vmov r2, r3, d13746; CHECK-NEXT: vmov q0[2], q0[0], r2, r3747; CHECK-NEXT: vmov q0[3], q0[1], r2, r3748; CHECK-NEXT: vmov.u8 r2, q2[7]749; CHECK-NEXT: vmov.u8 r3, q2[6]750; CHECK-NEXT: vcmp.i32 ne, q0, zr751; CHECK-NEXT: vmov q0[2], q0[0], r3, r2752; CHECK-NEXT: vand q0, q0, q3753; CHECK-NEXT: vpsel q0, q0, q4754; CHECK-NEXT: vmov r2, r3, d0755; CHECK-NEXT: adds r0, r0, r2756; CHECK-NEXT: adcs r1, r3757; CHECK-NEXT: vmov r2, r3, d1758; CHECK-NEXT: adds r0, r0, r2759; CHECK-NEXT: vmov.u8 r2, q5[8]760; CHECK-NEXT: vmov.16 q6[0], r2761; CHECK-NEXT: vmov.u8 r2, q5[9]762; CHECK-NEXT: vmov.16 q6[1], r2763; CHECK-NEXT: vmov.u8 r2, q5[10]764; CHECK-NEXT: vmov.16 q6[2], r2765; CHECK-NEXT: vmov.u8 r2, q5[11]766; CHECK-NEXT: vmov.16 q6[3], r2767; CHECK-NEXT: vmov.u8 r2, q5[12]768; CHECK-NEXT: vmov.16 q6[4], r2769; CHECK-NEXT: vmov.u8 r2, q5[13]770; CHECK-NEXT: vmov.16 q6[5], r2771; CHECK-NEXT: vmov.u8 r2, q5[14]772; CHECK-NEXT: vmov.16 q6[6], r2773; CHECK-NEXT: vmov.u8 r2, q5[15]774; CHECK-NEXT: vmov.16 q6[7], r2775; CHECK-NEXT: adcs r1, r3776; CHECK-NEXT: vcmp.i16 ne, q6, zr777; CHECK-NEXT: vpsel q5, q1, q7778; CHECK-NEXT: vmov.u16 r2, q5[2]779; CHECK-NEXT: vmov.u16 r3, q5[0]780; CHECK-NEXT: vmov q0[2], q0[0], r3, r2781; CHECK-NEXT: vmov.u16 r2, q5[3]782; CHECK-NEXT: vmov.u16 r3, q5[1]783; CHECK-NEXT: vmov q0[3], q0[1], r3, r2784; CHECK-NEXT: vcmp.i32 ne, q0, zr785; CHECK-NEXT: vpsel q6, q1, q7786; CHECK-NEXT: vmov.i8 q7, #0x0787; CHECK-NEXT: vmov r2, r3, d12788; CHECK-NEXT: vmov q0[2], q0[0], r2, r3789; CHECK-NEXT: vmov q0[3], q0[1], r2, r3790; CHECK-NEXT: vmov.u8 r2, q2[9]791; CHECK-NEXT: vmov.u8 r3, q2[8]792; CHECK-NEXT: vcmp.i32 ne, q0, zr793; CHECK-NEXT: vmov q0[2], q0[0], r3, r2794; CHECK-NEXT: vand q0, q0, q3795; CHECK-NEXT: vpsel q0, q0, q4796; CHECK-NEXT: vmov r2, r3, d0797; CHECK-NEXT: adds r0, r0, r2798; CHECK-NEXT: adcs r1, r3799; CHECK-NEXT: vmov r2, r3, d1800; CHECK-NEXT: adds r0, r0, r2801; CHECK-NEXT: adcs r1, r3802; CHECK-NEXT: vmov r2, r3, d13803; CHECK-NEXT: vmov q0[2], q0[0], r2, r3804; CHECK-NEXT: vmov q0[3], q0[1], r2, r3805; CHECK-NEXT: vmov.u8 r2, q2[11]806; CHECK-NEXT: vmov.u8 r3, q2[10]807; CHECK-NEXT: vcmp.i32 ne, q0, zr808; CHECK-NEXT: vmov q0[2], q0[0], r3, r2809; CHECK-NEXT: vand q0, q0, q3810; CHECK-NEXT: vpsel q0, q0, q4811; CHECK-NEXT: vmov r2, r3, d0812; CHECK-NEXT: adds r0, r0, r2813; CHECK-NEXT: adcs r1, r3814; CHECK-NEXT: vmov r2, r3, d1815; CHECK-NEXT: adds r0, r0, r2816; CHECK-NEXT: vmov.u16 r2, q5[6]817; CHECK-NEXT: adcs r1, r3818; CHECK-NEXT: vmov.u16 r3, q5[4]819; CHECK-NEXT: vmov q0[2], q0[0], r3, r2820; CHECK-NEXT: vmov.u16 r2, q5[7]821; CHECK-NEXT: vmov.u16 r3, q5[5]822; CHECK-NEXT: vmov q0[3], q0[1], r3, r2823; CHECK-NEXT: vcmp.i32 ne, q0, zr824; CHECK-NEXT: vpsel q1, q1, q7825; CHECK-NEXT: vmov r2, r3, d2826; CHECK-NEXT: vmov q0[2], q0[0], r2, r3827; CHECK-NEXT: vmov q0[3], q0[1], r2, r3828; CHECK-NEXT: vmov.u8 r2, q2[13]829; CHECK-NEXT: vmov.u8 r3, q2[12]830; CHECK-NEXT: vcmp.i32 ne, q0, zr831; CHECK-NEXT: vmov q0[2], q0[0], r3, r2832; CHECK-NEXT: vand q0, q0, q3833; CHECK-NEXT: vpsel q0, q0, q4834; CHECK-NEXT: vmov r2, r3, d0835; CHECK-NEXT: adds r0, r0, r2836; CHECK-NEXT: adcs r1, r3837; CHECK-NEXT: vmov r2, r3, d1838; CHECK-NEXT: adds r0, r0, r2839; CHECK-NEXT: adcs r1, r3840; CHECK-NEXT: vmov r2, r3, d3841; CHECK-NEXT: vmov q0[2], q0[0], r2, r3842; CHECK-NEXT: vmov q0[3], q0[1], r2, r3843; CHECK-NEXT: vmov.u8 r2, q2[15]844; CHECK-NEXT: vmov.u8 r3, q2[14]845; CHECK-NEXT: vcmp.i32 ne, q0, zr846; CHECK-NEXT: vmov q0[2], q0[0], r3, r2847; CHECK-NEXT: vand q0, q0, q3848; CHECK-NEXT: vpsel q0, q0, q4849; CHECK-NEXT: vmov r2, r3, d0850; CHECK-NEXT: adds r0, r0, r2851; CHECK-NEXT: adcs r1, r3852; CHECK-NEXT: vmov r2, r3, d1853; CHECK-NEXT: adds r0, r0, r2854; CHECK-NEXT: adcs r1, r3855; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}856; CHECK-NEXT: bx lr857entry:858 %c = icmp eq <16 x i8> %b, zeroinitializer859 %xx = zext <16 x i8> %x to <16 x i64>860 %s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer861 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)862 ret i64 %z863}864 865define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x, <16 x i8> %b) {866; CHECK-LABEL: add_v16i8_v16i64_sext:867; CHECK: @ %bb.0: @ %entry868; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}869; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}870; CHECK-NEXT: vcmp.i8 eq, q1, zr871; CHECK-NEXT: vmov.i8 q1, #0x0872; CHECK-NEXT: vmov.i8 q2, #0xff873; CHECK-NEXT: vpsel q4, q2, q1874; CHECK-NEXT: vmov.u8 r0, q4[0]875; CHECK-NEXT: vmov.16 q3[0], r0876; CHECK-NEXT: vmov.u8 r0, q4[1]877; CHECK-NEXT: vmov.16 q3[1], r0878; CHECK-NEXT: vmov.u8 r0, q4[2]879; CHECK-NEXT: vmov.16 q3[2], r0880; CHECK-NEXT: vmov.u8 r0, q4[3]881; CHECK-NEXT: vmov.16 q3[3], r0882; CHECK-NEXT: vmov.u8 r0, q4[4]883; CHECK-NEXT: vmov.16 q3[4], r0884; CHECK-NEXT: vmov.u8 r0, q4[5]885; CHECK-NEXT: vmov.16 q3[5], r0886; CHECK-NEXT: vmov.u8 r0, q4[6]887; CHECK-NEXT: vmov.16 q3[6], r0888; CHECK-NEXT: vmov.u8 r0, q4[7]889; CHECK-NEXT: vmov.16 q3[7], r0890; CHECK-NEXT: vcmp.i16 ne, q3, zr891; CHECK-NEXT: vpsel q5, q2, q1892; CHECK-NEXT: vmov.u16 r0, q5[2]893; CHECK-NEXT: vmov.u16 r1, q5[0]894; CHECK-NEXT: vmov q3[2], q3[0], r1, r0895; CHECK-NEXT: vmov.u16 r0, q5[3]896; CHECK-NEXT: vmov.u16 r1, q5[1]897; CHECK-NEXT: vmov q3[3], q3[1], r1, r0898; CHECK-NEXT: vcmp.i32 ne, q3, zr899; CHECK-NEXT: vpsel q6, q2, q1900; CHECK-NEXT: vmov r0, r1, d12901; CHECK-NEXT: vmov q3[2], q3[0], r0, r1902; CHECK-NEXT: vmov q3[3], q3[1], r0, r1903; CHECK-NEXT: vmov.s8 r0, q0[1]904; CHECK-NEXT: vmov.s8 r1, q0[0]905; CHECK-NEXT: vcmp.i32 ne, q3, zr906; CHECK-NEXT: vmov q7[2], q7[0], r1, r0907; CHECK-NEXT: asrs r0, r0, #31908; CHECK-NEXT: asrs r1, r1, #31909; CHECK-NEXT: vmov.i32 q3, #0x0910; CHECK-NEXT: vmov q7[3], q7[1], r1, r0911; CHECK-NEXT: vpsel q7, q7, q3912; CHECK-NEXT: vmov r0, r1, d15913; CHECK-NEXT: vmov r2, r3, d14914; CHECK-NEXT: adds r0, r0, r2915; CHECK-NEXT: adcs r1, r3916; CHECK-NEXT: vmov r2, r3, d13917; CHECK-NEXT: vmov q6[2], q6[0], r2, r3918; CHECK-NEXT: vmov q6[3], q6[1], r2, r3919; CHECK-NEXT: vmov.s8 r2, q0[3]920; CHECK-NEXT: vmov.s8 r3, q0[2]921; CHECK-NEXT: vcmp.i32 ne, q6, zr922; CHECK-NEXT: vmov q6[2], q6[0], r3, r2923; CHECK-NEXT: asrs r2, r2, #31924; CHECK-NEXT: asrs r3, r3, #31925; CHECK-NEXT: vmov q6[3], q6[1], r3, r2926; CHECK-NEXT: vpsel q6, q6, q3927; CHECK-NEXT: vmov r2, r3, d12928; CHECK-NEXT: adds r0, r0, r2929; CHECK-NEXT: adcs r1, r3930; CHECK-NEXT: vmov r2, r3, d13931; CHECK-NEXT: adds r0, r0, r2932; CHECK-NEXT: vmov.u16 r2, q5[6]933; CHECK-NEXT: adcs r1, r3934; CHECK-NEXT: vmov.u16 r3, q5[4]935; CHECK-NEXT: vmov q6[2], q6[0], r3, r2936; CHECK-NEXT: vmov.u16 r2, q5[7]937; CHECK-NEXT: vmov.u16 r3, q5[5]938; CHECK-NEXT: vmov q6[3], q6[1], r3, r2939; CHECK-NEXT: vcmp.i32 ne, q6, zr940; CHECK-NEXT: vpsel q5, q2, q1941; CHECK-NEXT: vmov r2, r3, d10942; CHECK-NEXT: vmov q6[2], q6[0], r2, r3943; CHECK-NEXT: vmov q6[3], q6[1], r2, r3944; CHECK-NEXT: vmov.s8 r2, q0[5]945; CHECK-NEXT: vmov.s8 r3, q0[4]946; CHECK-NEXT: vcmp.i32 ne, q6, zr947; CHECK-NEXT: vmov q6[2], q6[0], r3, r2948; CHECK-NEXT: asrs r2, r2, #31949; CHECK-NEXT: asrs r3, r3, #31950; CHECK-NEXT: vmov q6[3], q6[1], r3, r2951; CHECK-NEXT: vpsel q6, q6, q3952; CHECK-NEXT: vmov r2, r3, d12953; CHECK-NEXT: adds r0, r0, r2954; CHECK-NEXT: adcs r1, r3955; CHECK-NEXT: vmov r2, r3, d13956; CHECK-NEXT: adds r0, r0, r2957; CHECK-NEXT: adcs r1, r3958; CHECK-NEXT: vmov r2, r3, d11959; CHECK-NEXT: vmov q5[2], q5[0], r2, r3960; CHECK-NEXT: vmov q5[3], q5[1], r2, r3961; CHECK-NEXT: vmov.s8 r2, q0[7]962; CHECK-NEXT: vmov.s8 r3, q0[6]963; CHECK-NEXT: vcmp.i32 ne, q5, zr964; CHECK-NEXT: vmov q5[2], q5[0], r3, r2965; CHECK-NEXT: asrs r2, r2, #31966; CHECK-NEXT: asrs r3, r3, #31967; CHECK-NEXT: vmov q5[3], q5[1], r3, r2968; CHECK-NEXT: vpsel q5, q5, q3969; CHECK-NEXT: vmov r2, r3, d10970; CHECK-NEXT: adds r0, r0, r2971; CHECK-NEXT: adcs r1, r3972; CHECK-NEXT: vmov r2, r3, d11973; CHECK-NEXT: adds r0, r0, r2974; CHECK-NEXT: vmov.u8 r2, q4[8]975; CHECK-NEXT: vmov.16 q5[0], r2976; CHECK-NEXT: vmov.u8 r2, q4[9]977; CHECK-NEXT: vmov.16 q5[1], r2978; CHECK-NEXT: vmov.u8 r2, q4[10]979; CHECK-NEXT: vmov.16 q5[2], r2980; CHECK-NEXT: vmov.u8 r2, q4[11]981; CHECK-NEXT: vmov.16 q5[3], r2982; CHECK-NEXT: vmov.u8 r2, q4[12]983; CHECK-NEXT: vmov.16 q5[4], r2984; CHECK-NEXT: vmov.u8 r2, q4[13]985; CHECK-NEXT: vmov.16 q5[5], r2986; CHECK-NEXT: vmov.u8 r2, q4[14]987; CHECK-NEXT: vmov.16 q5[6], r2988; CHECK-NEXT: vmov.u8 r2, q4[15]989; CHECK-NEXT: vmov.16 q5[7], r2990; CHECK-NEXT: adcs r1, r3991; CHECK-NEXT: vcmp.i16 ne, q5, zr992; CHECK-NEXT: vpsel q4, q2, q1993; CHECK-NEXT: vmov.u16 r2, q4[2]994; CHECK-NEXT: vmov.u16 r3, q4[0]995; CHECK-NEXT: vmov q5[2], q5[0], r3, r2996; CHECK-NEXT: vmov.u16 r2, q4[3]997; CHECK-NEXT: vmov.u16 r3, q4[1]998; CHECK-NEXT: vmov q5[3], q5[1], r3, r2999; CHECK-NEXT: vcmp.i32 ne, q5, zr1000; CHECK-NEXT: vpsel q5, q2, q11001; CHECK-NEXT: vmov r2, r3, d101002; CHECK-NEXT: vmov q6[2], q6[0], r2, r31003; CHECK-NEXT: vmov q6[3], q6[1], r2, r31004; CHECK-NEXT: vmov.s8 r2, q0[9]1005; CHECK-NEXT: vmov.s8 r3, q0[8]1006; CHECK-NEXT: vcmp.i32 ne, q6, zr1007; CHECK-NEXT: vmov q6[2], q6[0], r3, r21008; CHECK-NEXT: asrs r2, r2, #311009; CHECK-NEXT: asrs r3, r3, #311010; CHECK-NEXT: vmov q6[3], q6[1], r3, r21011; CHECK-NEXT: vpsel q6, q6, q31012; CHECK-NEXT: vmov r2, r3, d121013; CHECK-NEXT: adds r0, r0, r21014; CHECK-NEXT: adcs r1, r31015; CHECK-NEXT: vmov r2, r3, d131016; CHECK-NEXT: adds r0, r0, r21017; CHECK-NEXT: adcs r1, r31018; CHECK-NEXT: vmov r2, r3, d111019; CHECK-NEXT: vmov q5[2], q5[0], r2, r31020; CHECK-NEXT: vmov q5[3], q5[1], r2, r31021; CHECK-NEXT: vmov.s8 r2, q0[11]1022; CHECK-NEXT: vmov.s8 r3, q0[10]1023; CHECK-NEXT: vcmp.i32 ne, q5, zr1024; CHECK-NEXT: vmov q5[2], q5[0], r3, r21025; CHECK-NEXT: asrs r2, r2, #311026; CHECK-NEXT: asrs r3, r3, #311027; CHECK-NEXT: vmov q5[3], q5[1], r3, r21028; CHECK-NEXT: vpsel q5, q5, q31029; CHECK-NEXT: vmov r2, r3, d101030; CHECK-NEXT: adds r0, r0, r21031; CHECK-NEXT: adcs r1, r31032; CHECK-NEXT: vmov r2, r3, d111033; CHECK-NEXT: adds r0, r0, r21034; CHECK-NEXT: vmov.u16 r2, q4[6]1035; CHECK-NEXT: adcs r1, r31036; CHECK-NEXT: vmov.u16 r3, q4[4]1037; CHECK-NEXT: vmov q5[2], q5[0], r3, r21038; CHECK-NEXT: vmov.u16 r2, q4[7]1039; CHECK-NEXT: vmov.u16 r3, q4[5]1040; CHECK-NEXT: vmov q5[3], q5[1], r3, r21041; CHECK-NEXT: vcmp.i32 ne, q5, zr1042; CHECK-NEXT: vpsel q1, q2, q11043; CHECK-NEXT: vmov r2, r3, d21044; CHECK-NEXT: vmov q2[2], q2[0], r2, r31045; CHECK-NEXT: vmov q2[3], q2[1], r2, r31046; CHECK-NEXT: vmov.s8 r2, q0[13]1047; CHECK-NEXT: vmov.s8 r3, q0[12]1048; CHECK-NEXT: vcmp.i32 ne, q2, zr1049; CHECK-NEXT: vmov q2[2], q2[0], r3, r21050; CHECK-NEXT: asrs r2, r2, #311051; CHECK-NEXT: asrs r3, r3, #311052; CHECK-NEXT: vmov q2[3], q2[1], r3, r21053; CHECK-NEXT: vpsel q2, q2, q31054; CHECK-NEXT: vmov r2, r3, d41055; CHECK-NEXT: adds r0, r0, r21056; CHECK-NEXT: adcs r1, r31057; CHECK-NEXT: vmov r2, r3, d51058; CHECK-NEXT: adds r0, r0, r21059; CHECK-NEXT: adcs r1, r31060; CHECK-NEXT: vmov r2, r3, d31061; CHECK-NEXT: vmov q1[2], q1[0], r2, r31062; CHECK-NEXT: vmov q1[3], q1[1], r2, r31063; CHECK-NEXT: vmov.s8 r2, q0[15]1064; CHECK-NEXT: vmov.s8 r3, q0[14]1065; CHECK-NEXT: vcmp.i32 ne, q1, zr1066; CHECK-NEXT: vmov q0[2], q0[0], r3, r21067; CHECK-NEXT: asrs r2, r2, #311068; CHECK-NEXT: asrs r3, r3, #311069; CHECK-NEXT: vmov q0[3], q0[1], r3, r21070; CHECK-NEXT: vpsel q0, q0, q31071; CHECK-NEXT: vmov r2, r3, d01072; CHECK-NEXT: adds r0, r0, r21073; CHECK-NEXT: adcs r1, r31074; CHECK-NEXT: vmov r2, r3, d11075; CHECK-NEXT: adds r0, r0, r21076; CHECK-NEXT: adcs r1, r31077; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1078; CHECK-NEXT: bx lr1079entry:1080 %c = icmp eq <16 x i8> %b, zeroinitializer1081 %xx = sext <16 x i8> %x to <16 x i64>1082 %s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer1083 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)1084 ret i64 %z1085}1086 1087define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_zext(<8 x i8> %x, <8 x i8> %b) {1088; CHECK-LABEL: add_v8i8_v8i64_zext:1089; CHECK: @ %bb.0: @ %entry1090; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1091; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1092; CHECK-NEXT: vmovlb.u8 q1, q11093; CHECK-NEXT: vmov.i8 q3, #0x01094; CHECK-NEXT: vcmp.i16 eq, q1, zr1095; CHECK-NEXT: vmov.i8 q4, #0xff1096; CHECK-NEXT: vpsel q5, q4, q31097; CHECK-NEXT: vmovlb.u8 q0, q01098; CHECK-NEXT: vmov.u16 r0, q5[2]1099; CHECK-NEXT: vmov.u16 r1, q5[0]1100; CHECK-NEXT: vmov q1[2], q1[0], r1, r01101; CHECK-NEXT: vmov.u16 r0, q5[3]1102; CHECK-NEXT: vmov.u16 r1, q5[1]1103; CHECK-NEXT: vmov q1[3], q1[1], r1, r01104; CHECK-NEXT: vcmp.i32 ne, q1, zr1105; CHECK-NEXT: vpsel q6, q4, q31106; CHECK-NEXT: vmov r0, r1, d121107; CHECK-NEXT: vmov q1[2], q1[0], r0, r11108; CHECK-NEXT: vmov q1[3], q1[1], r0, r11109; CHECK-NEXT: vmov.u16 r0, q0[1]1110; CHECK-NEXT: vmov.u16 r1, q0[0]1111; CHECK-NEXT: vcmp.i32 ne, q1, zr1112; CHECK-NEXT: vmov q2[2], q2[0], r1, r01113; CHECK-NEXT: vmov.i64 q1, #0xffff1114; CHECK-NEXT: vand q7, q2, q11115; CHECK-NEXT: vmov.i32 q2, #0x01116; CHECK-NEXT: vpsel q7, q7, q21117; CHECK-NEXT: vmov r0, r1, d151118; CHECK-NEXT: vmov r2, r3, d141119; CHECK-NEXT: orrs r1, r31120; CHECK-NEXT: add r0, r21121; CHECK-NEXT: vmov r2, r3, d131122; CHECK-NEXT: vmov q6[2], q6[0], r2, r31123; CHECK-NEXT: vmov q6[3], q6[1], r2, r31124; CHECK-NEXT: vmov.u16 r2, q0[3]1125; CHECK-NEXT: vmov.u16 r3, q0[2]1126; CHECK-NEXT: vcmp.i32 ne, q6, zr1127; CHECK-NEXT: vmov q6[2], q6[0], r3, r21128; CHECK-NEXT: vand q6, q6, q11129; CHECK-NEXT: vpsel q6, q6, q21130; CHECK-NEXT: vmov r2, r3, d121131; CHECK-NEXT: adds r0, r0, r21132; CHECK-NEXT: adcs r1, r31133; CHECK-NEXT: vmov r2, r3, d131134; CHECK-NEXT: adds r0, r0, r21135; CHECK-NEXT: vmov.u16 r2, q5[6]1136; CHECK-NEXT: adcs r1, r31137; CHECK-NEXT: vmov.u16 r3, q5[4]1138; CHECK-NEXT: vmov q6[2], q6[0], r3, r21139; CHECK-NEXT: vmov.u16 r2, q5[7]1140; CHECK-NEXT: vmov.u16 r3, q5[5]1141; CHECK-NEXT: vmov q6[3], q6[1], r3, r21142; CHECK-NEXT: vcmp.i32 ne, q6, zr1143; CHECK-NEXT: vpsel q3, q4, q31144; CHECK-NEXT: vmov r2, r3, d61145; CHECK-NEXT: vmov q4[2], q4[0], r2, r31146; CHECK-NEXT: vmov q4[3], q4[1], r2, r31147; CHECK-NEXT: vmov.u16 r2, q0[5]1148; CHECK-NEXT: vmov.u16 r3, q0[4]1149; CHECK-NEXT: vcmp.i32 ne, q4, zr1150; CHECK-NEXT: vmov q4[2], q4[0], r3, r21151; CHECK-NEXT: vand q4, q4, q11152; CHECK-NEXT: vpsel q4, q4, q21153; CHECK-NEXT: vmov r2, r3, d81154; CHECK-NEXT: adds r0, r0, r21155; CHECK-NEXT: adcs r1, r31156; CHECK-NEXT: vmov r2, r3, d91157; CHECK-NEXT: adds r0, r0, r21158; CHECK-NEXT: adcs r1, r31159; CHECK-NEXT: vmov r2, r3, d71160; CHECK-NEXT: vmov q3[2], q3[0], r2, r31161; CHECK-NEXT: vmov q3[3], q3[1], r2, r31162; CHECK-NEXT: vmov.u16 r2, q0[7]1163; CHECK-NEXT: vmov.u16 r3, q0[6]1164; CHECK-NEXT: vcmp.i32 ne, q3, zr1165; CHECK-NEXT: vmov q0[2], q0[0], r3, r21166; CHECK-NEXT: vand q0, q0, q11167; CHECK-NEXT: vpsel q0, q0, q21168; CHECK-NEXT: vmov r2, r3, d01169; CHECK-NEXT: adds r0, r0, r21170; CHECK-NEXT: adcs r1, r31171; CHECK-NEXT: vmov r2, r3, d11172; CHECK-NEXT: adds r0, r0, r21173; CHECK-NEXT: adcs r1, r31174; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1175; CHECK-NEXT: bx lr1176entry:1177 %c = icmp eq <8 x i8> %b, zeroinitializer1178 %xx = zext <8 x i8> %x to <8 x i64>1179 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer1180 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)1181 ret i64 %z1182}1183 1184define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_sext(<8 x i8> %x, <8 x i8> %b) {1185; CHECK-LABEL: add_v8i8_v8i64_sext:1186; CHECK: @ %bb.0: @ %entry1187; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1188; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}1189; CHECK-NEXT: vmovlb.u8 q1, q11190; CHECK-NEXT: vmov.i8 q2, #0x01191; CHECK-NEXT: vcmp.i16 eq, q1, zr1192; CHECK-NEXT: vmov.i8 q3, #0xff1193; CHECK-NEXT: vpsel q4, q3, q21194; CHECK-NEXT: vmov.u16 r0, q4[2]1195; CHECK-NEXT: vmov.u16 r1, q4[0]1196; CHECK-NEXT: vmov q1[2], q1[0], r1, r01197; CHECK-NEXT: vmov.u16 r0, q4[3]1198; CHECK-NEXT: vmov.u16 r1, q4[1]1199; CHECK-NEXT: vmov q1[3], q1[1], r1, r01200; CHECK-NEXT: vcmp.i32 ne, q1, zr1201; CHECK-NEXT: vpsel q5, q3, q21202; CHECK-NEXT: vmov r0, r1, d101203; CHECK-NEXT: vmov q1[2], q1[0], r0, r11204; CHECK-NEXT: vmov q1[3], q1[1], r0, r11205; CHECK-NEXT: vmov.u16 r0, q0[1]1206; CHECK-NEXT: vmov.u16 r1, q0[0]1207; CHECK-NEXT: sxtb r0, r01208; CHECK-NEXT: sxtb r1, r11209; CHECK-NEXT: vcmp.i32 ne, q1, zr1210; CHECK-NEXT: vmov q6[2], q6[0], r1, r01211; CHECK-NEXT: asrs r0, r0, #311212; CHECK-NEXT: asrs r1, r1, #311213; CHECK-NEXT: vmov.i32 q1, #0x01214; CHECK-NEXT: vmov q6[3], q6[1], r1, r01215; CHECK-NEXT: vpsel q6, q6, q11216; CHECK-NEXT: vmov r0, r1, d131217; CHECK-NEXT: vmov r2, r3, d121218; CHECK-NEXT: adds r0, r0, r21219; CHECK-NEXT: adcs r1, r31220; CHECK-NEXT: vmov r2, r3, d111221; CHECK-NEXT: vmov q5[2], q5[0], r2, r31222; CHECK-NEXT: vmov q5[3], q5[1], r2, r31223; CHECK-NEXT: vmov.u16 r2, q0[3]1224; CHECK-NEXT: vmov.u16 r3, q0[2]1225; CHECK-NEXT: sxtb r2, r21226; CHECK-NEXT: sxtb r3, r31227; CHECK-NEXT: vcmp.i32 ne, q5, zr1228; CHECK-NEXT: vmov q5[2], q5[0], r3, r21229; CHECK-NEXT: asrs r2, r2, #311230; CHECK-NEXT: asrs r3, r3, #311231; CHECK-NEXT: vmov q5[3], q5[1], r3, r21232; CHECK-NEXT: vpsel q5, q5, q11233; CHECK-NEXT: vmov r2, r3, d101234; CHECK-NEXT: adds r0, r0, r21235; CHECK-NEXT: adcs r1, r31236; CHECK-NEXT: vmov r2, r3, d111237; CHECK-NEXT: adds r0, r0, r21238; CHECK-NEXT: vmov.u16 r2, q4[6]1239; CHECK-NEXT: adcs r1, r31240; CHECK-NEXT: vmov.u16 r3, q4[4]1241; CHECK-NEXT: vmov q5[2], q5[0], r3, r21242; CHECK-NEXT: vmov.u16 r2, q4[7]1243; CHECK-NEXT: vmov.u16 r3, q4[5]1244; CHECK-NEXT: vmov q5[3], q5[1], r3, r21245; CHECK-NEXT: vcmp.i32 ne, q5, zr1246; CHECK-NEXT: vpsel q2, q3, q21247; CHECK-NEXT: vmov r2, r3, d41248; CHECK-NEXT: vmov q3[2], q3[0], r2, r31249; CHECK-NEXT: vmov q3[3], q3[1], r2, r31250; CHECK-NEXT: vmov.u16 r2, q0[5]1251; CHECK-NEXT: vmov.u16 r3, q0[4]1252; CHECK-NEXT: sxtb r2, r21253; CHECK-NEXT: sxtb r3, r31254; CHECK-NEXT: vcmp.i32 ne, q3, zr1255; CHECK-NEXT: vmov q3[2], q3[0], r3, r21256; CHECK-NEXT: asrs r2, r2, #311257; CHECK-NEXT: asrs r3, r3, #311258; CHECK-NEXT: vmov q3[3], q3[1], r3, r21259; CHECK-NEXT: vpsel q3, q3, q11260; CHECK-NEXT: vmov r2, r3, d61261; CHECK-NEXT: adds r0, r0, r21262; CHECK-NEXT: adcs r1, r31263; CHECK-NEXT: vmov r2, r3, d71264; CHECK-NEXT: adds r0, r0, r21265; CHECK-NEXT: adcs r1, r31266; CHECK-NEXT: vmov r2, r3, d51267; CHECK-NEXT: vmov q2[2], q2[0], r2, r31268; CHECK-NEXT: vmov q2[3], q2[1], r2, r31269; CHECK-NEXT: vmov.u16 r2, q0[7]1270; CHECK-NEXT: vmov.u16 r3, q0[6]1271; CHECK-NEXT: sxtb r2, r21272; CHECK-NEXT: sxtb r3, r31273; CHECK-NEXT: vcmp.i32 ne, q2, zr1274; CHECK-NEXT: vmov q0[2], q0[0], r3, r21275; CHECK-NEXT: asrs r2, r2, #311276; CHECK-NEXT: asrs r3, r3, #311277; CHECK-NEXT: vmov q0[3], q0[1], r3, r21278; CHECK-NEXT: vpsel q0, q0, q11279; CHECK-NEXT: vmov r2, r3, d01280; CHECK-NEXT: adds r0, r0, r21281; CHECK-NEXT: adcs r1, r31282; CHECK-NEXT: vmov r2, r3, d11283; CHECK-NEXT: adds r0, r0, r21284; CHECK-NEXT: adcs r1, r31285; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1286; CHECK-NEXT: bx lr1287entry:1288 %c = icmp eq <8 x i8> %b, zeroinitializer1289 %xx = sext <8 x i8> %x to <8 x i64>1290 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer1291 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)1292 ret i64 %z1293}1294 1295define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_zext(<4 x i8> %x, <4 x i8> %b) {1296; CHECK-LABEL: add_v4i8_v4i64_zext:1297; CHECK: @ %bb.0: @ %entry1298; CHECK-NEXT: vmov.i32 q2, #0xff1299; CHECK-NEXT: vand q1, q1, q21300; CHECK-NEXT: vand q0, q0, q21301; CHECK-NEXT: vpt.i32 eq, q1, zr1302; CHECK-NEXT: vaddlvt.u32 r0, r1, q01303; CHECK-NEXT: bx lr1304entry:1305 %c = icmp eq <4 x i8> %b, zeroinitializer1306 %xx = zext <4 x i8> %x to <4 x i64>1307 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer1308 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)1309 ret i64 %z1310}1311 1312define arm_aapcs_vfpcc i64 @add_v4i8_v4i64_sext(<4 x i8> %x, <4 x i8> %b) {1313; CHECK-LABEL: add_v4i8_v4i64_sext:1314; CHECK: @ %bb.0: @ %entry1315; CHECK-NEXT: vmov.i32 q2, #0xff1316; CHECK-NEXT: vmovlb.s8 q0, q01317; CHECK-NEXT: vand q1, q1, q21318; CHECK-NEXT: vmovlb.s16 q0, q01319; CHECK-NEXT: vpt.i32 eq, q1, zr1320; CHECK-NEXT: vaddlvt.s32 r0, r1, q01321; CHECK-NEXT: bx lr1322entry:1323 %c = icmp eq <4 x i8> %b, zeroinitializer1324 %xx = sext <4 x i8> %x to <4 x i64>1325 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer1326 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)1327 ret i64 %z1328}1329 1330define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %b) {1331; CHECK-LABEL: add_v2i8_v2i64_zext:1332; CHECK: @ %bb.0: @ %entry1333; CHECK-NEXT: vmov.i64 q2, #0xff1334; CHECK-NEXT: movs r1, #01335; CHECK-NEXT: vand q1, q1, q21336; CHECK-NEXT: vand q0, q0, q21337; CHECK-NEXT: vmov r0, s41338; CHECK-NEXT: cmp r0, #01339; CHECK-NEXT: csetm r0, eq1340; CHECK-NEXT: bfi r1, r0, #0, #81341; CHECK-NEXT: vmov r0, s61342; CHECK-NEXT: vmov.i32 q1, #0x01343; CHECK-NEXT: cmp r0, #01344; CHECK-NEXT: csetm r0, eq1345; CHECK-NEXT: bfi r1, r0, #8, #81346; CHECK-NEXT: vmsr p0, r11347; CHECK-NEXT: vpsel q0, q0, q11348; CHECK-NEXT: vmov r0, r1, d11349; CHECK-NEXT: vmov r2, r3, d01350; CHECK-NEXT: add r0, r21351; CHECK-NEXT: orrs r1, r31352; CHECK-NEXT: bx lr1353entry:1354 %c = icmp eq <2 x i8> %b, zeroinitializer1355 %xx = zext <2 x i8> %x to <2 x i64>1356 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1357 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1358 ret i64 %z1359}1360 1361define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %b) {1362; CHECK-LABEL: add_v2i8_v2i64_sext:1363; CHECK: @ %bb.0: @ %entry1364; CHECK-NEXT: vmov.i32 q2, #0xff1365; CHECK-NEXT: movs r1, #01366; CHECK-NEXT: vand q1, q1, q21367; CHECK-NEXT: vmov r0, s41368; CHECK-NEXT: cmp r0, #01369; CHECK-NEXT: csetm r0, eq1370; CHECK-NEXT: bfi r1, r0, #0, #81371; CHECK-NEXT: vmov r0, s61372; CHECK-NEXT: vmov.i32 q1, #0x01373; CHECK-NEXT: cmp r0, #01374; CHECK-NEXT: csetm r0, eq1375; CHECK-NEXT: bfi r1, r0, #8, #81376; CHECK-NEXT: vmov r0, s21377; CHECK-NEXT: vmsr p0, r11378; CHECK-NEXT: vmov r1, s01379; CHECK-NEXT: sxtb r0, r01380; CHECK-NEXT: sxtb r1, r11381; CHECK-NEXT: vmov q0[2], q0[0], r1, r01382; CHECK-NEXT: asrs r0, r0, #311383; CHECK-NEXT: asrs r1, r1, #311384; CHECK-NEXT: vmov q0[3], q0[1], r1, r01385; CHECK-NEXT: vpsel q0, q0, q11386; CHECK-NEXT: vmov r0, r1, d11387; CHECK-NEXT: vmov r2, r3, d01388; CHECK-NEXT: adds r0, r0, r21389; CHECK-NEXT: adcs r1, r31390; CHECK-NEXT: bx lr1391entry:1392 %c = icmp eq <2 x i8> %b, zeroinitializer1393 %xx = sext <2 x i8> %x to <2 x i64>1394 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1395 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1396 ret i64 %z1397}1398 1399define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %b) {1400; CHECK-LABEL: add_v2i64_v2i64:1401; CHECK: @ %bb.0: @ %entry1402; CHECK-NEXT: vmov r0, r1, d21403; CHECK-NEXT: orrs r0, r11404; CHECK-NEXT: mov.w r1, #01405; CHECK-NEXT: csetm r0, eq1406; CHECK-NEXT: bfi r1, r0, #0, #81407; CHECK-NEXT: vmov r0, r2, d31408; CHECK-NEXT: vmov.i32 q1, #0x01409; CHECK-NEXT: orrs r0, r21410; CHECK-NEXT: csetm r0, eq1411; CHECK-NEXT: bfi r1, r0, #8, #81412; CHECK-NEXT: vmsr p0, r11413; CHECK-NEXT: vpsel q0, q0, q11414; CHECK-NEXT: vmov r0, r1, d11415; CHECK-NEXT: vmov r2, r3, d01416; CHECK-NEXT: adds r0, r0, r21417; CHECK-NEXT: adcs r1, r31418; CHECK-NEXT: bx lr1419entry:1420 %c = icmp eq <2 x i64> %b, zeroinitializer1421 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer1422 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1423 ret i64 %z1424}1425 1426define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %b, i32 %a) {1427; CHECK-LABEL: add_v4i32_v4i32_acc:1428; CHECK: @ %bb.0: @ %entry1429; CHECK-NEXT: vpt.i32 eq, q1, zr1430; CHECK-NEXT: vaddvat.u32 r0, q01431; CHECK-NEXT: bx lr1432entry:1433 %c = icmp eq <4 x i32> %b, zeroinitializer1434 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer1435 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)1436 %r = add i32 %z, %a1437 ret i32 %r1438}1439 1440define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, <4 x i32> %b, i64 %a) {1441; CHECK-LABEL: add_v4i32_v4i64_acc_zext:1442; CHECK: @ %bb.0: @ %entry1443; CHECK-NEXT: vpt.i32 eq, q1, zr1444; CHECK-NEXT: vaddlvat.u32 r0, r1, q01445; CHECK-NEXT: bx lr1446entry:1447 %c = icmp eq <4 x i32> %b, zeroinitializer1448 %xx = zext <4 x i32> %x to <4 x i64>1449 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer1450 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)1451 %r = add i64 %z, %a1452 ret i64 %r1453}1454 1455define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, <4 x i32> %b, i64 %a) {1456; CHECK-LABEL: add_v4i32_v4i64_acc_sext:1457; CHECK: @ %bb.0: @ %entry1458; CHECK-NEXT: vpt.i32 eq, q1, zr1459; CHECK-NEXT: vaddlvat.s32 r0, r1, q01460; CHECK-NEXT: bx lr1461entry:1462 %c = icmp eq <4 x i32> %b, zeroinitializer1463 %xx = sext <4 x i32> %x to <4 x i64>1464 %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer1465 %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)1466 %r = add i64 %z, %a1467 ret i64 %r1468}1469 1470define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %b, i64 %a) {1471; CHECK-LABEL: add_v2i32_v2i64_acc_zext:1472; CHECK: @ %bb.0: @ %entry1473; CHECK-NEXT: .save {r7, lr}1474; CHECK-NEXT: push {r7, lr}1475; CHECK-NEXT: vmov r2, s41476; CHECK-NEXT: movs r3, #01477; CHECK-NEXT: vmov.i64 q2, #0xffffffff1478; CHECK-NEXT: vand q0, q0, q21479; CHECK-NEXT: cmp r2, #01480; CHECK-NEXT: csetm r2, eq1481; CHECK-NEXT: bfi r3, r2, #0, #81482; CHECK-NEXT: vmov r2, s61483; CHECK-NEXT: vmov.i32 q1, #0x01484; CHECK-NEXT: cmp r2, #01485; CHECK-NEXT: csetm r2, eq1486; CHECK-NEXT: bfi r3, r2, #8, #81487; CHECK-NEXT: vmsr p0, r31488; CHECK-NEXT: vpsel q0, q0, q11489; CHECK-NEXT: vmov lr, r12, d11490; CHECK-NEXT: vmov r3, r2, d01491; CHECK-NEXT: adds.w r3, r3, lr1492; CHECK-NEXT: adc.w r2, r2, r121493; CHECK-NEXT: adds r0, r0, r31494; CHECK-NEXT: adcs r1, r21495; CHECK-NEXT: pop {r7, pc}1496entry:1497 %c = icmp eq <2 x i32> %b, zeroinitializer1498 %xx = zext <2 x i32> %x to <2 x i64>1499 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1500 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1501 %r = add i64 %z, %a1502 ret i64 %r1503}1504 1505define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %b, i64 %a) {1506; CHECK-LABEL: add_v2i32_v2i64_acc_sext:1507; CHECK: @ %bb.0: @ %entry1508; CHECK-NEXT: .save {r7, lr}1509; CHECK-NEXT: push {r7, lr}1510; CHECK-NEXT: vmov r2, s21511; CHECK-NEXT: vmov r3, s01512; CHECK-NEXT: vmov q0[2], q0[0], r3, r21513; CHECK-NEXT: asrs r2, r2, #311514; CHECK-NEXT: asrs r3, r3, #311515; CHECK-NEXT: vmov q0[3], q0[1], r3, r21516; CHECK-NEXT: vmov r2, s41517; CHECK-NEXT: movs r3, #01518; CHECK-NEXT: cmp r2, #01519; CHECK-NEXT: csetm r2, eq1520; CHECK-NEXT: bfi r3, r2, #0, #81521; CHECK-NEXT: vmov r2, s61522; CHECK-NEXT: vmov.i32 q1, #0x01523; CHECK-NEXT: cmp r2, #01524; CHECK-NEXT: csetm r2, eq1525; CHECK-NEXT: bfi r3, r2, #8, #81526; CHECK-NEXT: vmsr p0, r31527; CHECK-NEXT: vpsel q0, q0, q11528; CHECK-NEXT: vmov lr, r12, d11529; CHECK-NEXT: vmov r3, r2, d01530; CHECK-NEXT: adds.w r3, r3, lr1531; CHECK-NEXT: adc.w r2, r2, r121532; CHECK-NEXT: adds r0, r0, r31533; CHECK-NEXT: adcs r1, r21534; CHECK-NEXT: pop {r7, pc}1535entry:1536 %c = icmp eq <2 x i32> %b, zeroinitializer1537 %xx = sext <2 x i32> %x to <2 x i64>1538 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1539 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1540 %r = add i64 %z, %a1541 ret i64 %r1542}1543 1544define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, <8 x i16> %b, i32 %a) {1545; CHECK-LABEL: add_v8i16_v8i32_acc_zext:1546; CHECK: @ %bb.0: @ %entry1547; CHECK-NEXT: vpt.i16 eq, q1, zr1548; CHECK-NEXT: vaddvat.u16 r0, q01549; CHECK-NEXT: bx lr1550entry:1551 %c = icmp eq <8 x i16> %b, zeroinitializer1552 %xx = zext <8 x i16> %x to <8 x i32>1553 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer1554 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)1555 %r = add i32 %z, %a1556 ret i32 %r1557}1558 1559define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, <8 x i16> %b, i32 %a) {1560; CHECK-LABEL: add_v8i16_v8i32_acc_sext:1561; CHECK: @ %bb.0: @ %entry1562; CHECK-NEXT: vpt.i16 eq, q1, zr1563; CHECK-NEXT: vaddvat.s16 r0, q01564; CHECK-NEXT: bx lr1565entry:1566 %c = icmp eq <8 x i16> %b, zeroinitializer1567 %xx = sext <8 x i16> %x to <8 x i32>1568 %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer1569 %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)1570 %r = add i32 %z, %a1571 ret i32 %r1572}1573 1574define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %b, i32 %a) {1575; CHECK-LABEL: add_v4i16_v4i32_acc_zext:1576; CHECK: @ %bb.0: @ %entry1577; CHECK-NEXT: vmovlb.u16 q1, q11578; CHECK-NEXT: vmovlb.u16 q0, q01579; CHECK-NEXT: vpt.i32 eq, q1, zr1580; CHECK-NEXT: vaddvat.u32 r0, q01581; CHECK-NEXT: bx lr1582entry:1583 %c = icmp eq <4 x i16> %b, zeroinitializer1584 %xx = zext <4 x i16> %x to <4 x i32>1585 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer1586 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)1587 %r = add i32 %z, %a1588 ret i32 %r1589}1590 1591define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %b, i32 %a) {1592; CHECK-LABEL: add_v4i16_v4i32_acc_sext:1593; CHECK: @ %bb.0: @ %entry1594; CHECK-NEXT: vmovlb.u16 q1, q11595; CHECK-NEXT: vmovlb.s16 q0, q01596; CHECK-NEXT: vpt.i32 eq, q1, zr1597; CHECK-NEXT: vaddvat.u32 r0, q01598; CHECK-NEXT: bx lr1599entry:1600 %c = icmp eq <4 x i16> %b, zeroinitializer1601 %xx = sext <4 x i16> %x to <4 x i32>1602 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer1603 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)1604 %r = add i32 %z, %a1605 ret i32 %r1606}1607 1608define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %b, i16 %a) {1609; CHECK-LABEL: add_v8i16_v8i16_acc:1610; CHECK: @ %bb.0: @ %entry1611; CHECK-NEXT: vpt.i16 eq, q1, zr1612; CHECK-NEXT: vaddvat.u16 r0, q01613; CHECK-NEXT: uxth r0, r01614; CHECK-NEXT: bx lr1615entry:1616 %c = icmp eq <8 x i16> %b, zeroinitializer1617 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer1618 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)1619 %r = add i16 %z, %a1620 ret i16 %r1621}1622 1623define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_zext(<8 x i16> %x, <8 x i16> %b, i64 %a) {1624; CHECK-LABEL: add_v8i16_v8i64_acc_zext:1625; CHECK: @ %bb.0: @ %entry1626; CHECK-NEXT: .save {r7, lr}1627; CHECK-NEXT: push {r7, lr}1628; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1629; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1630; CHECK-NEXT: vmov.i8 q3, #0x01631; CHECK-NEXT: vmov.i8 q4, #0xff1632; CHECK-NEXT: vcmp.i16 eq, q1, zr1633; CHECK-NEXT: vpsel q5, q4, q31634; CHECK-NEXT: vmov.u16 r2, q5[2]1635; CHECK-NEXT: vmov.u16 r3, q5[0]1636; CHECK-NEXT: vmov q1[2], q1[0], r3, r21637; CHECK-NEXT: vmov.u16 r2, q5[3]1638; CHECK-NEXT: vmov.u16 r3, q5[1]1639; CHECK-NEXT: vmov q1[3], q1[1], r3, r21640; CHECK-NEXT: vcmp.i32 ne, q1, zr1641; CHECK-NEXT: vpsel q6, q4, q31642; CHECK-NEXT: vmov r2, r3, d121643; CHECK-NEXT: vmov q1[2], q1[0], r2, r31644; CHECK-NEXT: vmov q1[3], q1[1], r2, r31645; CHECK-NEXT: vmov.u16 r2, q0[1]1646; CHECK-NEXT: vmov.u16 r3, q0[0]1647; CHECK-NEXT: vcmp.i32 ne, q1, zr1648; CHECK-NEXT: vmov q2[2], q2[0], r3, r21649; CHECK-NEXT: vmov.i64 q1, #0xffff1650; CHECK-NEXT: vand q7, q2, q11651; CHECK-NEXT: vmov.i32 q2, #0x01652; CHECK-NEXT: vpsel q7, q7, q21653; CHECK-NEXT: vmov r12, lr, d151654; CHECK-NEXT: vmov r2, r3, d141655; CHECK-NEXT: orr.w lr, lr, r31656; CHECK-NEXT: add r12, r21657; CHECK-NEXT: vmov r3, r2, d131658; CHECK-NEXT: vmov q6[2], q6[0], r3, r21659; CHECK-NEXT: vmov q6[3], q6[1], r3, r21660; CHECK-NEXT: vmov.u16 r2, q0[3]1661; CHECK-NEXT: vmov.u16 r3, q0[2]1662; CHECK-NEXT: vcmp.i32 ne, q6, zr1663; CHECK-NEXT: vmov q6[2], q6[0], r3, r21664; CHECK-NEXT: vand q6, q6, q11665; CHECK-NEXT: vpsel q6, q6, q21666; CHECK-NEXT: vmov r2, r3, d121667; CHECK-NEXT: adds.w r12, r12, r21668; CHECK-NEXT: adc.w lr, lr, r31669; CHECK-NEXT: vmov r2, r3, d131670; CHECK-NEXT: adds.w r12, r12, r21671; CHECK-NEXT: vmov.u16 r2, q5[6]1672; CHECK-NEXT: adc.w lr, lr, r31673; CHECK-NEXT: vmov.u16 r3, q5[4]1674; CHECK-NEXT: vmov q6[2], q6[0], r3, r21675; CHECK-NEXT: vmov.u16 r2, q5[7]1676; CHECK-NEXT: vmov.u16 r3, q5[5]1677; CHECK-NEXT: vmov q6[3], q6[1], r3, r21678; CHECK-NEXT: vcmp.i32 ne, q6, zr1679; CHECK-NEXT: vpsel q3, q4, q31680; CHECK-NEXT: vmov r2, r3, d61681; CHECK-NEXT: vmov q4[2], q4[0], r2, r31682; CHECK-NEXT: vmov q4[3], q4[1], r2, r31683; CHECK-NEXT: vmov.u16 r2, q0[5]1684; CHECK-NEXT: vmov.u16 r3, q0[4]1685; CHECK-NEXT: vcmp.i32 ne, q4, zr1686; CHECK-NEXT: vmov q4[2], q4[0], r3, r21687; CHECK-NEXT: vand q4, q4, q11688; CHECK-NEXT: vpsel q4, q4, q21689; CHECK-NEXT: vmov r2, r3, d81690; CHECK-NEXT: adds.w r12, r12, r21691; CHECK-NEXT: adc.w lr, lr, r31692; CHECK-NEXT: vmov r2, r3, d91693; CHECK-NEXT: adds.w r12, r12, r21694; CHECK-NEXT: adc.w lr, lr, r31695; CHECK-NEXT: vmov r2, r3, d71696; CHECK-NEXT: vmov q3[2], q3[0], r2, r31697; CHECK-NEXT: vmov q3[3], q3[1], r2, r31698; CHECK-NEXT: vmov.u16 r2, q0[7]1699; CHECK-NEXT: vmov.u16 r3, q0[6]1700; CHECK-NEXT: vcmp.i32 ne, q3, zr1701; CHECK-NEXT: vmov q0[2], q0[0], r3, r21702; CHECK-NEXT: vand q0, q0, q11703; CHECK-NEXT: vpsel q0, q0, q21704; CHECK-NEXT: vmov r2, r3, d01705; CHECK-NEXT: adds.w r12, r12, r21706; CHECK-NEXT: adc.w lr, lr, r31707; CHECK-NEXT: vmov r2, r3, d11708; CHECK-NEXT: adds.w r2, r2, r121709; CHECK-NEXT: adc.w r3, r3, lr1710; CHECK-NEXT: adds r0, r0, r21711; CHECK-NEXT: adcs r1, r31712; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1713; CHECK-NEXT: pop {r7, pc}1714entry:1715 %c = icmp eq <8 x i16> %b, zeroinitializer1716 %xx = zext <8 x i16> %x to <8 x i64>1717 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer1718 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)1719 %r = add i64 %z, %a1720 ret i64 %r1721}1722 1723define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, <8 x i16> %b, i64 %a) {1724; CHECK-LABEL: add_v8i16_v8i64_acc_sext:1725; CHECK: @ %bb.0: @ %entry1726; CHECK-NEXT: .save {r7, lr}1727; CHECK-NEXT: push {r7, lr}1728; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1729; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}1730; CHECK-NEXT: vmov.i8 q2, #0x01731; CHECK-NEXT: vmov.i8 q3, #0xff1732; CHECK-NEXT: vcmp.i16 eq, q1, zr1733; CHECK-NEXT: vpsel q4, q3, q21734; CHECK-NEXT: vmov.u16 r2, q4[2]1735; CHECK-NEXT: vmov.u16 r3, q4[0]1736; CHECK-NEXT: vmov q1[2], q1[0], r3, r21737; CHECK-NEXT: vmov.u16 r2, q4[3]1738; CHECK-NEXT: vmov.u16 r3, q4[1]1739; CHECK-NEXT: vmov q1[3], q1[1], r3, r21740; CHECK-NEXT: vcmp.i32 ne, q1, zr1741; CHECK-NEXT: vpsel q5, q3, q21742; CHECK-NEXT: vmov r2, r3, d101743; CHECK-NEXT: vmov q1[2], q1[0], r2, r31744; CHECK-NEXT: vmov q1[3], q1[1], r2, r31745; CHECK-NEXT: vmov.s16 r2, q0[1]1746; CHECK-NEXT: vmov.s16 r3, q0[0]1747; CHECK-NEXT: vcmp.i32 ne, q1, zr1748; CHECK-NEXT: vmov q6[2], q6[0], r3, r21749; CHECK-NEXT: asrs r2, r2, #311750; CHECK-NEXT: asrs r3, r3, #311751; CHECK-NEXT: vmov.i32 q1, #0x01752; CHECK-NEXT: vmov q6[3], q6[1], r3, r21753; CHECK-NEXT: vpsel q6, q6, q11754; CHECK-NEXT: vmov lr, r12, d131755; CHECK-NEXT: vmov r3, r2, d121756; CHECK-NEXT: adds.w lr, lr, r31757; CHECK-NEXT: adc.w r12, r12, r21758; CHECK-NEXT: vmov r2, r3, d111759; CHECK-NEXT: vmov q5[2], q5[0], r2, r31760; CHECK-NEXT: vmov q5[3], q5[1], r2, r31761; CHECK-NEXT: vmov.s16 r2, q0[3]1762; CHECK-NEXT: vmov.s16 r3, q0[2]1763; CHECK-NEXT: vcmp.i32 ne, q5, zr1764; CHECK-NEXT: vmov q5[2], q5[0], r3, r21765; CHECK-NEXT: asrs r2, r2, #311766; CHECK-NEXT: asrs r3, r3, #311767; CHECK-NEXT: vmov q5[3], q5[1], r3, r21768; CHECK-NEXT: vpsel q5, q5, q11769; CHECK-NEXT: vmov r2, r3, d101770; CHECK-NEXT: adds.w lr, lr, r21771; CHECK-NEXT: adc.w r12, r12, r31772; CHECK-NEXT: vmov r2, r3, d111773; CHECK-NEXT: adds.w lr, lr, r21774; CHECK-NEXT: vmov.u16 r2, q4[6]1775; CHECK-NEXT: adc.w r12, r12, r31776; CHECK-NEXT: vmov.u16 r3, q4[4]1777; CHECK-NEXT: vmov q5[2], q5[0], r3, r21778; CHECK-NEXT: vmov.u16 r2, q4[7]1779; CHECK-NEXT: vmov.u16 r3, q4[5]1780; CHECK-NEXT: vmov q5[3], q5[1], r3, r21781; CHECK-NEXT: vcmp.i32 ne, q5, zr1782; CHECK-NEXT: vpsel q2, q3, q21783; CHECK-NEXT: vmov r2, r3, d41784; CHECK-NEXT: vmov q3[2], q3[0], r2, r31785; CHECK-NEXT: vmov q3[3], q3[1], r2, r31786; CHECK-NEXT: vmov.s16 r2, q0[5]1787; CHECK-NEXT: vmov.s16 r3, q0[4]1788; CHECK-NEXT: vcmp.i32 ne, q3, zr1789; CHECK-NEXT: vmov q3[2], q3[0], r3, r21790; CHECK-NEXT: asrs r2, r2, #311791; CHECK-NEXT: asrs r3, r3, #311792; CHECK-NEXT: vmov q3[3], q3[1], r3, r21793; CHECK-NEXT: vpsel q3, q3, q11794; CHECK-NEXT: vmov r2, r3, d61795; CHECK-NEXT: adds.w lr, lr, r21796; CHECK-NEXT: adc.w r12, r12, r31797; CHECK-NEXT: vmov r2, r3, d71798; CHECK-NEXT: adds.w lr, lr, r21799; CHECK-NEXT: adc.w r12, r12, r31800; CHECK-NEXT: vmov r2, r3, d51801; CHECK-NEXT: vmov q2[2], q2[0], r2, r31802; CHECK-NEXT: vmov q2[3], q2[1], r2, r31803; CHECK-NEXT: vmov.s16 r2, q0[7]1804; CHECK-NEXT: vmov.s16 r3, q0[6]1805; CHECK-NEXT: vcmp.i32 ne, q2, zr1806; CHECK-NEXT: vmov q0[2], q0[0], r3, r21807; CHECK-NEXT: asrs r2, r2, #311808; CHECK-NEXT: asrs r3, r3, #311809; CHECK-NEXT: vmov q0[3], q0[1], r3, r21810; CHECK-NEXT: vpsel q0, q0, q11811; CHECK-NEXT: vmov r2, r3, d01812; CHECK-NEXT: adds.w lr, lr, r21813; CHECK-NEXT: adc.w r12, r12, r31814; CHECK-NEXT: vmov r2, r3, d11815; CHECK-NEXT: adds.w r2, r2, lr1816; CHECK-NEXT: adc.w r3, r3, r121817; CHECK-NEXT: adds r0, r0, r21818; CHECK-NEXT: adcs r1, r31819; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1820; CHECK-NEXT: pop {r7, pc}1821entry:1822 %c = icmp eq <8 x i16> %b, zeroinitializer1823 %xx = sext <8 x i16> %x to <8 x i64>1824 %s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer1825 %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)1826 %r = add i64 %z, %a1827 ret i64 %r1828}1829 1830define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %b, i64 %a) {1831; CHECK-LABEL: add_v2i16_v2i64_acc_zext:1832; CHECK: @ %bb.0: @ %entry1833; CHECK-NEXT: .save {r7, lr}1834; CHECK-NEXT: push {r7, lr}1835; CHECK-NEXT: vmov.i64 q2, #0xffff1836; CHECK-NEXT: movs r3, #01837; CHECK-NEXT: vand q1, q1, q21838; CHECK-NEXT: vand q0, q0, q21839; CHECK-NEXT: vmov r2, s41840; CHECK-NEXT: cmp r2, #01841; CHECK-NEXT: csetm r2, eq1842; CHECK-NEXT: bfi r3, r2, #0, #81843; CHECK-NEXT: vmov r2, s61844; CHECK-NEXT: vmov.i32 q1, #0x01845; CHECK-NEXT: cmp r2, #01846; CHECK-NEXT: csetm r2, eq1847; CHECK-NEXT: bfi r3, r2, #8, #81848; CHECK-NEXT: vmsr p0, r31849; CHECK-NEXT: vpsel q0, q0, q11850; CHECK-NEXT: vmov r12, lr, d11851; CHECK-NEXT: vmov r2, r3, d01852; CHECK-NEXT: add r2, r121853; CHECK-NEXT: orr.w r3, r3, lr1854; CHECK-NEXT: adds r0, r0, r21855; CHECK-NEXT: adcs r1, r31856; CHECK-NEXT: pop {r7, pc}1857entry:1858 %c = icmp eq <2 x i16> %b, zeroinitializer1859 %xx = zext <2 x i16> %x to <2 x i64>1860 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1861 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1862 %r = add i64 %z, %a1863 ret i64 %r1864}1865 1866define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %b, i64 %a) {1867; CHECK-LABEL: add_v2i16_v2i64_acc_sext:1868; CHECK: @ %bb.0: @ %entry1869; CHECK-NEXT: .save {r7, lr}1870; CHECK-NEXT: push {r7, lr}1871; CHECK-NEXT: vmov.i32 q2, #0xffff1872; CHECK-NEXT: movs r3, #01873; CHECK-NEXT: vand q1, q1, q21874; CHECK-NEXT: vmov r2, s41875; CHECK-NEXT: cmp r2, #01876; CHECK-NEXT: csetm r2, eq1877; CHECK-NEXT: bfi r3, r2, #0, #81878; CHECK-NEXT: vmov r2, s61879; CHECK-NEXT: vmov.i32 q1, #0x01880; CHECK-NEXT: cmp r2, #01881; CHECK-NEXT: csetm r2, eq1882; CHECK-NEXT: bfi r3, r2, #8, #81883; CHECK-NEXT: vmov r2, s21884; CHECK-NEXT: vmsr p0, r31885; CHECK-NEXT: vmov r3, s01886; CHECK-NEXT: sxth r2, r21887; CHECK-NEXT: sxth r3, r31888; CHECK-NEXT: vmov q0[2], q0[0], r3, r21889; CHECK-NEXT: asrs r2, r2, #311890; CHECK-NEXT: asrs r3, r3, #311891; CHECK-NEXT: vmov q0[3], q0[1], r3, r21892; CHECK-NEXT: vpsel q0, q0, q11893; CHECK-NEXT: vmov lr, r12, d11894; CHECK-NEXT: vmov r3, r2, d01895; CHECK-NEXT: adds.w r3, r3, lr1896; CHECK-NEXT: adc.w r2, r2, r121897; CHECK-NEXT: adds r0, r0, r31898; CHECK-NEXT: adcs r1, r21899; CHECK-NEXT: pop {r7, pc}1900entry:1901 %c = icmp eq <2 x i16> %b, zeroinitializer1902 %xx = sext <2 x i16> %x to <2 x i64>1903 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer1904 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)1905 %r = add i64 %z, %a1906 ret i64 %r1907}1908 1909define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, <16 x i8> %b, i32 %a) {1910; CHECK-LABEL: add_v16i8_v16i32_acc_zext:1911; CHECK: @ %bb.0: @ %entry1912; CHECK-NEXT: vpt.i8 eq, q1, zr1913; CHECK-NEXT: vaddvat.u8 r0, q01914; CHECK-NEXT: bx lr1915entry:1916 %c = icmp eq <16 x i8> %b, zeroinitializer1917 %xx = zext <16 x i8> %x to <16 x i32>1918 %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer1919 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)1920 %r = add i32 %z, %a1921 ret i32 %r1922}1923 1924define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, <16 x i8> %b, i32 %a) {1925; CHECK-LABEL: add_v16i8_v16i32_acc_sext:1926; CHECK: @ %bb.0: @ %entry1927; CHECK-NEXT: vpt.i8 eq, q1, zr1928; CHECK-NEXT: vaddvat.s8 r0, q01929; CHECK-NEXT: bx lr1930entry:1931 %c = icmp eq <16 x i8> %b, zeroinitializer1932 %xx = sext <16 x i8> %x to <16 x i32>1933 %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer1934 %z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)1935 %r = add i32 %z, %a1936 ret i32 %r1937}1938 1939define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %b, i32 %a) {1940; CHECK-LABEL: add_v4i8_v4i32_acc_zext:1941; CHECK: @ %bb.0: @ %entry1942; CHECK-NEXT: vmov.i32 q2, #0xff1943; CHECK-NEXT: vand q1, q1, q21944; CHECK-NEXT: vand q0, q0, q21945; CHECK-NEXT: vpt.i32 eq, q1, zr1946; CHECK-NEXT: vaddvat.u32 r0, q01947; CHECK-NEXT: bx lr1948entry:1949 %c = icmp eq <4 x i8> %b, zeroinitializer1950 %xx = zext <4 x i8> %x to <4 x i32>1951 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer1952 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)1953 %r = add i32 %z, %a1954 ret i32 %r1955}1956 1957define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %b, i32 %a) {1958; CHECK-LABEL: add_v4i8_v4i32_acc_sext:1959; CHECK: @ %bb.0: @ %entry1960; CHECK-NEXT: vmov.i32 q2, #0xff1961; CHECK-NEXT: vmovlb.s8 q0, q01962; CHECK-NEXT: vand q1, q1, q21963; CHECK-NEXT: vmovlb.s16 q0, q01964; CHECK-NEXT: vpt.i32 eq, q1, zr1965; CHECK-NEXT: vaddvat.u32 r0, q01966; CHECK-NEXT: bx lr1967entry:1968 %c = icmp eq <4 x i8> %b, zeroinitializer1969 %xx = sext <4 x i8> %x to <4 x i32>1970 %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer1971 %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)1972 %r = add i32 %z, %a1973 ret i32 %r1974}1975 1976define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_acc_zext(<16 x i8> %x, <16 x i8> %b, i16 %a) {1977; CHECK-LABEL: add_v16i8_v16i16_acc_zext:1978; CHECK: @ %bb.0: @ %entry1979; CHECK-NEXT: vpt.i8 eq, q1, zr1980; CHECK-NEXT: vaddvat.u8 r0, q01981; CHECK-NEXT: uxth r0, r01982; CHECK-NEXT: bx lr1983entry:1984 %c = icmp eq <16 x i8> %b, zeroinitializer1985 %xx = zext <16 x i8> %x to <16 x i16>1986 %s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer1987 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)1988 %r = add i16 %z, %a1989 ret i16 %r1990}1991 1992define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_acc_sext(<16 x i8> %x, <16 x i8> %b, i16 %a) {1993; CHECK-LABEL: add_v16i8_v16i16_acc_sext:1994; CHECK: @ %bb.0: @ %entry1995; CHECK-NEXT: vpt.i8 eq, q1, zr1996; CHECK-NEXT: vaddvat.s8 r0, q01997; CHECK-NEXT: sxth r0, r01998; CHECK-NEXT: bx lr1999entry:2000 %c = icmp eq <16 x i8> %b, zeroinitializer2001 %xx = sext <16 x i8> %x to <16 x i16>2002 %s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer2003 %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)2004 %r = add i16 %z, %a2005 ret i16 %r2006}2007 2008define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %b, i16 %a) {2009; CHECK-LABEL: add_v8i8_v8i16_acc_zext:2010; CHECK: @ %bb.0: @ %entry2011; CHECK-NEXT: vmovlb.u8 q1, q12012; CHECK-NEXT: vmovlb.u8 q0, q02013; CHECK-NEXT: vpt.i16 eq, q1, zr2014; CHECK-NEXT: vaddvat.u16 r0, q02015; CHECK-NEXT: uxth r0, r02016; CHECK-NEXT: bx lr2017entry:2018 %c = icmp eq <8 x i8> %b, zeroinitializer2019 %xx = zext <8 x i8> %x to <8 x i16>2020 %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer2021 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)2022 %r = add i16 %z, %a2023 ret i16 %r2024}2025 2026define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %b, i16 %a) {2027; CHECK-LABEL: add_v8i8_v8i16_acc_sext:2028; CHECK: @ %bb.0: @ %entry2029; CHECK-NEXT: vmovlb.u8 q1, q12030; CHECK-NEXT: vmovlb.s8 q0, q02031; CHECK-NEXT: vpt.i16 eq, q1, zr2032; CHECK-NEXT: vaddvat.u16 r0, q02033; CHECK-NEXT: sxth r0, r02034; CHECK-NEXT: bx lr2035entry:2036 %c = icmp eq <8 x i8> %b, zeroinitializer2037 %xx = sext <8 x i8> %x to <8 x i16>2038 %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer2039 %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)2040 %r = add i16 %z, %a2041 ret i16 %r2042}2043 2044define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %b, i8 %a) {2045; CHECK-LABEL: add_v16i8_v16i8_acc:2046; CHECK: @ %bb.0: @ %entry2047; CHECK-NEXT: vpt.i8 eq, q1, zr2048; CHECK-NEXT: vaddvat.u8 r0, q02049; CHECK-NEXT: uxtb r0, r02050; CHECK-NEXT: bx lr2051entry:2052 %c = icmp eq <16 x i8> %b, zeroinitializer2053 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer2054 %z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)2055 %r = add i8 %z, %a2056 ret i8 %r2057}2058 2059define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_zext(<16 x i8> %x, <16 x i8> %b, i64 %a) {2060; CHECK-LABEL: add_v16i8_v16i64_acc_zext:2061; CHECK: @ %bb.0: @ %entry2062; CHECK-NEXT: .save {r7, lr}2063; CHECK-NEXT: push {r7, lr}2064; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}2065; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}2066; CHECK-NEXT: vmov q2, q02067; CHECK-NEXT: vcmp.i8 eq, q1, zr2068; CHECK-NEXT: vmov.i8 q0, #0x02069; CHECK-NEXT: vmov.i8 q1, #0xff2070; CHECK-NEXT: vpsel q5, q1, q02071; CHECK-NEXT: vmov.i8 q0, #0x02072; CHECK-NEXT: vmov.u8 r2, q5[0]2073; CHECK-NEXT: vmov.16 q3[0], r22074; CHECK-NEXT: vmov.u8 r2, q5[1]2075; CHECK-NEXT: vmov.16 q3[1], r22076; CHECK-NEXT: vmov.u8 r2, q5[2]2077; CHECK-NEXT: vmov.16 q3[2], r22078; CHECK-NEXT: vmov.u8 r2, q5[3]2079; CHECK-NEXT: vmov.16 q3[3], r22080; CHECK-NEXT: vmov.u8 r2, q5[4]2081; CHECK-NEXT: vmov.16 q3[4], r22082; CHECK-NEXT: vmov.u8 r2, q5[5]2083; CHECK-NEXT: vmov.16 q3[5], r22084; CHECK-NEXT: vmov.u8 r2, q5[6]2085; CHECK-NEXT: vmov.16 q3[6], r22086; CHECK-NEXT: vmov.u8 r2, q5[7]2087; CHECK-NEXT: vmov.16 q3[7], r22088; CHECK-NEXT: vcmp.i16 ne, q3, zr2089; CHECK-NEXT: vpsel q6, q1, q02090; CHECK-NEXT: vmov.u16 r2, q6[2]2091; CHECK-NEXT: vmov.u16 r3, q6[0]2092; CHECK-NEXT: vmov q3[2], q3[0], r3, r22093; CHECK-NEXT: vmov.u16 r2, q6[3]2094; CHECK-NEXT: vmov.u16 r3, q6[1]2095; CHECK-NEXT: vmov q3[3], q3[1], r3, r22096; CHECK-NEXT: vcmp.i32 ne, q3, zr2097; CHECK-NEXT: vpsel q7, q1, q02098; CHECK-NEXT: vmov r2, r3, d142099; CHECK-NEXT: vmov q3[2], q3[0], r2, r32100; CHECK-NEXT: vmov q3[3], q3[1], r2, r32101; CHECK-NEXT: vmov.u8 r2, q2[1]2102; CHECK-NEXT: vmov.u8 r3, q2[0]2103; CHECK-NEXT: vcmp.i32 ne, q3, zr2104; CHECK-NEXT: vmov q4[2], q4[0], r3, r22105; CHECK-NEXT: vmov.i64 q3, #0xff2106; CHECK-NEXT: vand q0, q4, q32107; CHECK-NEXT: vmov.i32 q4, #0x02108; CHECK-NEXT: vpsel q0, q0, q42109; CHECK-NEXT: vmov r12, lr, d12110; CHECK-NEXT: vmov r2, r3, d02111; CHECK-NEXT: orr.w lr, lr, r32112; CHECK-NEXT: add r12, r22113; CHECK-NEXT: vmov r3, r2, d152114; CHECK-NEXT: vmov.i8 q7, #0x02115; CHECK-NEXT: vmov q0[2], q0[0], r3, r22116; CHECK-NEXT: vmov q0[3], q0[1], r3, r22117; CHECK-NEXT: vmov.u8 r2, q2[3]2118; CHECK-NEXT: vmov.u8 r3, q2[2]2119; CHECK-NEXT: vcmp.i32 ne, q0, zr2120; CHECK-NEXT: vmov q0[2], q0[0], r3, r22121; CHECK-NEXT: vand q0, q0, q32122; CHECK-NEXT: vpsel q0, q0, q42123; CHECK-NEXT: vmov r2, r3, d02124; CHECK-NEXT: adds.w r12, r12, r22125; CHECK-NEXT: adc.w lr, lr, r32126; CHECK-NEXT: vmov r2, r3, d12127; CHECK-NEXT: adds.w r12, r12, r22128; CHECK-NEXT: vmov.u16 r2, q6[6]2129; CHECK-NEXT: adc.w lr, lr, r32130; CHECK-NEXT: vmov.u16 r3, q6[4]2131; CHECK-NEXT: vmov q0[2], q0[0], r3, r22132; CHECK-NEXT: vmov.u16 r2, q6[7]2133; CHECK-NEXT: vmov.u16 r3, q6[5]2134; CHECK-NEXT: vmov q0[3], q0[1], r3, r22135; CHECK-NEXT: vcmp.i32 ne, q0, zr2136; CHECK-NEXT: vpsel q6, q1, q72137; CHECK-NEXT: vmov r2, r3, d122138; CHECK-NEXT: vmov q0[2], q0[0], r2, r32139; CHECK-NEXT: vmov q0[3], q0[1], r2, r32140; CHECK-NEXT: vmov.u8 r2, q2[5]2141; CHECK-NEXT: vmov.u8 r3, q2[4]2142; CHECK-NEXT: vcmp.i32 ne, q0, zr2143; CHECK-NEXT: vmov q0[2], q0[0], r3, r22144; CHECK-NEXT: vand q0, q0, q32145; CHECK-NEXT: vpsel q0, q0, q42146; CHECK-NEXT: vmov r2, r3, d02147; CHECK-NEXT: adds.w r12, r12, r22148; CHECK-NEXT: adc.w lr, lr, r32149; CHECK-NEXT: vmov r2, r3, d12150; CHECK-NEXT: adds.w r12, r12, r22151; CHECK-NEXT: adc.w lr, lr, r32152; CHECK-NEXT: vmov r2, r3, d132153; CHECK-NEXT: vmov q0[2], q0[0], r2, r32154; CHECK-NEXT: vmov q0[3], q0[1], r2, r32155; CHECK-NEXT: vmov.u8 r2, q2[7]2156; CHECK-NEXT: vmov.u8 r3, q2[6]2157; CHECK-NEXT: vcmp.i32 ne, q0, zr2158; CHECK-NEXT: vmov q0[2], q0[0], r3, r22159; CHECK-NEXT: vand q0, q0, q32160; CHECK-NEXT: vpsel q0, q0, q42161; CHECK-NEXT: vmov r2, r3, d02162; CHECK-NEXT: adds.w r12, r12, r22163; CHECK-NEXT: adc.w lr, lr, r32164; CHECK-NEXT: vmov r2, r3, d12165; CHECK-NEXT: adds.w r12, r12, r22166; CHECK-NEXT: vmov.u8 r2, q5[8]2167; CHECK-NEXT: vmov.16 q6[0], r22168; CHECK-NEXT: vmov.u8 r2, q5[9]2169; CHECK-NEXT: vmov.16 q6[1], r22170; CHECK-NEXT: vmov.u8 r2, q5[10]2171; CHECK-NEXT: vmov.16 q6[2], r22172; CHECK-NEXT: vmov.u8 r2, q5[11]2173; CHECK-NEXT: vmov.16 q6[3], r22174; CHECK-NEXT: vmov.u8 r2, q5[12]2175; CHECK-NEXT: vmov.16 q6[4], r22176; CHECK-NEXT: vmov.u8 r2, q5[13]2177; CHECK-NEXT: vmov.16 q6[5], r22178; CHECK-NEXT: vmov.u8 r2, q5[14]2179; CHECK-NEXT: vmov.16 q6[6], r22180; CHECK-NEXT: vmov.u8 r2, q5[15]2181; CHECK-NEXT: vmov.16 q6[7], r22182; CHECK-NEXT: adc.w lr, lr, r32183; CHECK-NEXT: vcmp.i16 ne, q6, zr2184; CHECK-NEXT: vpsel q5, q1, q72185; CHECK-NEXT: vmov.u16 r2, q5[2]2186; CHECK-NEXT: vmov.u16 r3, q5[0]2187; CHECK-NEXT: vmov q0[2], q0[0], r3, r22188; CHECK-NEXT: vmov.u16 r2, q5[3]2189; CHECK-NEXT: vmov.u16 r3, q5[1]2190; CHECK-NEXT: vmov q0[3], q0[1], r3, r22191; CHECK-NEXT: vcmp.i32 ne, q0, zr2192; CHECK-NEXT: vpsel q6, q1, q72193; CHECK-NEXT: vmov.i8 q7, #0x02194; CHECK-NEXT: vmov r2, r3, d122195; CHECK-NEXT: vmov q0[2], q0[0], r2, r32196; CHECK-NEXT: vmov q0[3], q0[1], r2, r32197; CHECK-NEXT: vmov.u8 r2, q2[9]2198; CHECK-NEXT: vmov.u8 r3, q2[8]2199; CHECK-NEXT: vcmp.i32 ne, q0, zr2200; CHECK-NEXT: vmov q0[2], q0[0], r3, r22201; CHECK-NEXT: vand q0, q0, q32202; CHECK-NEXT: vpsel q0, q0, q42203; CHECK-NEXT: vmov r2, r3, d02204; CHECK-NEXT: adds.w r12, r12, r22205; CHECK-NEXT: adc.w lr, lr, r32206; CHECK-NEXT: vmov r2, r3, d12207; CHECK-NEXT: adds.w r12, r12, r22208; CHECK-NEXT: adc.w lr, lr, r32209; CHECK-NEXT: vmov r2, r3, d132210; CHECK-NEXT: vmov q0[2], q0[0], r2, r32211; CHECK-NEXT: vmov q0[3], q0[1], r2, r32212; CHECK-NEXT: vmov.u8 r2, q2[11]2213; CHECK-NEXT: vmov.u8 r3, q2[10]2214; CHECK-NEXT: vcmp.i32 ne, q0, zr2215; CHECK-NEXT: vmov q0[2], q0[0], r3, r22216; CHECK-NEXT: vand q0, q0, q32217; CHECK-NEXT: vpsel q0, q0, q42218; CHECK-NEXT: vmov r2, r3, d02219; CHECK-NEXT: adds.w r12, r12, r22220; CHECK-NEXT: adc.w lr, lr, r32221; CHECK-NEXT: vmov r2, r3, d12222; CHECK-NEXT: adds.w r12, r12, r22223; CHECK-NEXT: vmov.u16 r2, q5[6]2224; CHECK-NEXT: adc.w lr, lr, r32225; CHECK-NEXT: vmov.u16 r3, q5[4]2226; CHECK-NEXT: vmov q0[2], q0[0], r3, r22227; CHECK-NEXT: vmov.u16 r2, q5[7]2228; CHECK-NEXT: vmov.u16 r3, q5[5]2229; CHECK-NEXT: vmov q0[3], q0[1], r3, r22230; CHECK-NEXT: vcmp.i32 ne, q0, zr2231; CHECK-NEXT: vpsel q1, q1, q72232; CHECK-NEXT: vmov r2, r3, d22233; CHECK-NEXT: vmov q0[2], q0[0], r2, r32234; CHECK-NEXT: vmov q0[3], q0[1], r2, r32235; CHECK-NEXT: vmov.u8 r2, q2[13]2236; CHECK-NEXT: vmov.u8 r3, q2[12]2237; CHECK-NEXT: vcmp.i32 ne, q0, zr2238; CHECK-NEXT: vmov q0[2], q0[0], r3, r22239; CHECK-NEXT: vand q0, q0, q32240; CHECK-NEXT: vpsel q0, q0, q42241; CHECK-NEXT: vmov r2, r3, d02242; CHECK-NEXT: adds.w r12, r12, r22243; CHECK-NEXT: adc.w lr, lr, r32244; CHECK-NEXT: vmov r2, r3, d12245; CHECK-NEXT: adds.w r12, r12, r22246; CHECK-NEXT: adc.w lr, lr, r32247; CHECK-NEXT: vmov r2, r3, d32248; CHECK-NEXT: vmov q0[2], q0[0], r2, r32249; CHECK-NEXT: vmov q0[3], q0[1], r2, r32250; CHECK-NEXT: vmov.u8 r2, q2[15]2251; CHECK-NEXT: vmov.u8 r3, q2[14]2252; CHECK-NEXT: vcmp.i32 ne, q0, zr2253; CHECK-NEXT: vmov q0[2], q0[0], r3, r22254; CHECK-NEXT: vand q0, q0, q32255; CHECK-NEXT: vpsel q0, q0, q42256; CHECK-NEXT: vmov r2, r3, d02257; CHECK-NEXT: adds.w r12, r12, r22258; CHECK-NEXT: adc.w lr, lr, r32259; CHECK-NEXT: vmov r2, r3, d12260; CHECK-NEXT: adds.w r2, r2, r122261; CHECK-NEXT: adc.w r3, r3, lr2262; CHECK-NEXT: adds r0, r0, r22263; CHECK-NEXT: adcs r1, r32264; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}2265; CHECK-NEXT: pop {r7, pc}2266entry:2267 %c = icmp eq <16 x i8> %b, zeroinitializer2268 %xx = zext <16 x i8> %x to <16 x i64>2269 %s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer2270 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)2271 %r = add i64 %z, %a2272 ret i64 %r2273}2274 2275define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext(<16 x i8> %x, <16 x i8> %b, i64 %a) {2276; CHECK-LABEL: add_v16i8_v16i64_acc_sext:2277; CHECK: @ %bb.0: @ %entry2278; CHECK-NEXT: .save {r7, lr}2279; CHECK-NEXT: push {r7, lr}2280; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}2281; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}2282; CHECK-NEXT: vcmp.i8 eq, q1, zr2283; CHECK-NEXT: vmov.i8 q1, #0x02284; CHECK-NEXT: vmov.i8 q2, #0xff2285; CHECK-NEXT: vpsel q4, q2, q12286; CHECK-NEXT: vmov.u8 r2, q4[0]2287; CHECK-NEXT: vmov.16 q3[0], r22288; CHECK-NEXT: vmov.u8 r2, q4[1]2289; CHECK-NEXT: vmov.16 q3[1], r22290; CHECK-NEXT: vmov.u8 r2, q4[2]2291; CHECK-NEXT: vmov.16 q3[2], r22292; CHECK-NEXT: vmov.u8 r2, q4[3]2293; CHECK-NEXT: vmov.16 q3[3], r22294; CHECK-NEXT: vmov.u8 r2, q4[4]2295; CHECK-NEXT: vmov.16 q3[4], r22296; CHECK-NEXT: vmov.u8 r2, q4[5]2297; CHECK-NEXT: vmov.16 q3[5], r22298; CHECK-NEXT: vmov.u8 r2, q4[6]2299; CHECK-NEXT: vmov.16 q3[6], r22300; CHECK-NEXT: vmov.u8 r2, q4[7]2301; CHECK-NEXT: vmov.16 q3[7], r22302; CHECK-NEXT: vcmp.i16 ne, q3, zr2303; CHECK-NEXT: vpsel q5, q2, q12304; CHECK-NEXT: vmov.u16 r2, q5[2]2305; CHECK-NEXT: vmov.u16 r3, q5[0]2306; CHECK-NEXT: vmov q3[2], q3[0], r3, r22307; CHECK-NEXT: vmov.u16 r2, q5[3]2308; CHECK-NEXT: vmov.u16 r3, q5[1]2309; CHECK-NEXT: vmov q3[3], q3[1], r3, r22310; CHECK-NEXT: vcmp.i32 ne, q3, zr2311; CHECK-NEXT: vpsel q6, q2, q12312; CHECK-NEXT: vmov r2, r3, d122313; CHECK-NEXT: vmov q3[2], q3[0], r2, r32314; CHECK-NEXT: vmov q3[3], q3[1], r2, r32315; CHECK-NEXT: vmov.s8 r2, q0[1]2316; CHECK-NEXT: vmov.s8 r3, q0[0]2317; CHECK-NEXT: vcmp.i32 ne, q3, zr2318; CHECK-NEXT: vmov q7[2], q7[0], r3, r22319; CHECK-NEXT: asrs r2, r2, #312320; CHECK-NEXT: asrs r3, r3, #312321; CHECK-NEXT: vmov.i32 q3, #0x02322; CHECK-NEXT: vmov q7[3], q7[1], r3, r22323; CHECK-NEXT: vpsel q7, q7, q32324; CHECK-NEXT: vmov lr, r12, d152325; CHECK-NEXT: vmov r3, r2, d142326; CHECK-NEXT: adds.w lr, lr, r32327; CHECK-NEXT: adc.w r12, r12, r22328; CHECK-NEXT: vmov r2, r3, d132329; CHECK-NEXT: vmov q6[2], q6[0], r2, r32330; CHECK-NEXT: vmov q6[3], q6[1], r2, r32331; CHECK-NEXT: vmov.s8 r2, q0[3]2332; CHECK-NEXT: vmov.s8 r3, q0[2]2333; CHECK-NEXT: vcmp.i32 ne, q6, zr2334; CHECK-NEXT: vmov q6[2], q6[0], r3, r22335; CHECK-NEXT: asrs r2, r2, #312336; CHECK-NEXT: asrs r3, r3, #312337; CHECK-NEXT: vmov q6[3], q6[1], r3, r22338; CHECK-NEXT: vpsel q6, q6, q32339; CHECK-NEXT: vmov r2, r3, d122340; CHECK-NEXT: adds.w lr, lr, r22341; CHECK-NEXT: adc.w r12, r12, r32342; CHECK-NEXT: vmov r2, r3, d132343; CHECK-NEXT: adds.w lr, lr, r22344; CHECK-NEXT: vmov.u16 r2, q5[6]2345; CHECK-NEXT: adc.w r12, r12, r32346; CHECK-NEXT: vmov.u16 r3, q5[4]2347; CHECK-NEXT: vmov q6[2], q6[0], r3, r22348; CHECK-NEXT: vmov.u16 r2, q5[7]2349; CHECK-NEXT: vmov.u16 r3, q5[5]2350; CHECK-NEXT: vmov q6[3], q6[1], r3, r22351; CHECK-NEXT: vcmp.i32 ne, q6, zr2352; CHECK-NEXT: vpsel q5, q2, q12353; CHECK-NEXT: vmov r2, r3, d102354; CHECK-NEXT: vmov q6[2], q6[0], r2, r32355; CHECK-NEXT: vmov q6[3], q6[1], r2, r32356; CHECK-NEXT: vmov.s8 r2, q0[5]2357; CHECK-NEXT: vmov.s8 r3, q0[4]2358; CHECK-NEXT: vcmp.i32 ne, q6, zr2359; CHECK-NEXT: vmov q6[2], q6[0], r3, r22360; CHECK-NEXT: asrs r2, r2, #312361; CHECK-NEXT: asrs r3, r3, #312362; CHECK-NEXT: vmov q6[3], q6[1], r3, r22363; CHECK-NEXT: vpsel q6, q6, q32364; CHECK-NEXT: vmov r2, r3, d122365; CHECK-NEXT: adds.w lr, lr, r22366; CHECK-NEXT: adc.w r12, r12, r32367; CHECK-NEXT: vmov r2, r3, d132368; CHECK-NEXT: adds.w lr, lr, r22369; CHECK-NEXT: adc.w r12, r12, r32370; CHECK-NEXT: vmov r2, r3, d112371; CHECK-NEXT: vmov q5[2], q5[0], r2, r32372; CHECK-NEXT: vmov q5[3], q5[1], r2, r32373; CHECK-NEXT: vmov.s8 r2, q0[7]2374; CHECK-NEXT: vmov.s8 r3, q0[6]2375; CHECK-NEXT: vcmp.i32 ne, q5, zr2376; CHECK-NEXT: vmov q5[2], q5[0], r3, r22377; CHECK-NEXT: asrs r2, r2, #312378; CHECK-NEXT: asrs r3, r3, #312379; CHECK-NEXT: vmov q5[3], q5[1], r3, r22380; CHECK-NEXT: vpsel q5, q5, q32381; CHECK-NEXT: vmov r2, r3, d102382; CHECK-NEXT: adds.w lr, lr, r22383; CHECK-NEXT: adc.w r12, r12, r32384; CHECK-NEXT: vmov r2, r3, d112385; CHECK-NEXT: adds.w lr, lr, r22386; CHECK-NEXT: vmov.u8 r2, q4[8]2387; CHECK-NEXT: vmov.16 q5[0], r22388; CHECK-NEXT: vmov.u8 r2, q4[9]2389; CHECK-NEXT: vmov.16 q5[1], r22390; CHECK-NEXT: vmov.u8 r2, q4[10]2391; CHECK-NEXT: vmov.16 q5[2], r22392; CHECK-NEXT: vmov.u8 r2, q4[11]2393; CHECK-NEXT: vmov.16 q5[3], r22394; CHECK-NEXT: vmov.u8 r2, q4[12]2395; CHECK-NEXT: vmov.16 q5[4], r22396; CHECK-NEXT: vmov.u8 r2, q4[13]2397; CHECK-NEXT: vmov.16 q5[5], r22398; CHECK-NEXT: vmov.u8 r2, q4[14]2399; CHECK-NEXT: vmov.16 q5[6], r22400; CHECK-NEXT: vmov.u8 r2, q4[15]2401; CHECK-NEXT: vmov.16 q5[7], r22402; CHECK-NEXT: adc.w r12, r12, r32403; CHECK-NEXT: vcmp.i16 ne, q5, zr2404; CHECK-NEXT: vpsel q4, q2, q12405; CHECK-NEXT: vmov.u16 r2, q4[2]2406; CHECK-NEXT: vmov.u16 r3, q4[0]2407; CHECK-NEXT: vmov q5[2], q5[0], r3, r22408; CHECK-NEXT: vmov.u16 r2, q4[3]2409; CHECK-NEXT: vmov.u16 r3, q4[1]2410; CHECK-NEXT: vmov q5[3], q5[1], r3, r22411; CHECK-NEXT: vcmp.i32 ne, q5, zr2412; CHECK-NEXT: vpsel q5, q2, q12413; CHECK-NEXT: vmov r2, r3, d102414; CHECK-NEXT: vmov q6[2], q6[0], r2, r32415; CHECK-NEXT: vmov q6[3], q6[1], r2, r32416; CHECK-NEXT: vmov.s8 r2, q0[9]2417; CHECK-NEXT: vmov.s8 r3, q0[8]2418; CHECK-NEXT: vcmp.i32 ne, q6, zr2419; CHECK-NEXT: vmov q6[2], q6[0], r3, r22420; CHECK-NEXT: asrs r2, r2, #312421; CHECK-NEXT: asrs r3, r3, #312422; CHECK-NEXT: vmov q6[3], q6[1], r3, r22423; CHECK-NEXT: vpsel q6, q6, q32424; CHECK-NEXT: vmov r2, r3, d122425; CHECK-NEXT: adds.w lr, lr, r22426; CHECK-NEXT: adc.w r12, r12, r32427; CHECK-NEXT: vmov r2, r3, d132428; CHECK-NEXT: adds.w lr, lr, r22429; CHECK-NEXT: adc.w r12, r12, r32430; CHECK-NEXT: vmov r2, r3, d112431; CHECK-NEXT: vmov q5[2], q5[0], r2, r32432; CHECK-NEXT: vmov q5[3], q5[1], r2, r32433; CHECK-NEXT: vmov.s8 r2, q0[11]2434; CHECK-NEXT: vmov.s8 r3, q0[10]2435; CHECK-NEXT: vcmp.i32 ne, q5, zr2436; CHECK-NEXT: vmov q5[2], q5[0], r3, r22437; CHECK-NEXT: asrs r2, r2, #312438; CHECK-NEXT: asrs r3, r3, #312439; CHECK-NEXT: vmov q5[3], q5[1], r3, r22440; CHECK-NEXT: vpsel q5, q5, q32441; CHECK-NEXT: vmov r2, r3, d102442; CHECK-NEXT: adds.w lr, lr, r22443; CHECK-NEXT: adc.w r12, r12, r32444; CHECK-NEXT: vmov r2, r3, d112445; CHECK-NEXT: adds.w lr, lr, r22446; CHECK-NEXT: vmov.u16 r2, q4[6]2447; CHECK-NEXT: adc.w r12, r12, r32448; CHECK-NEXT: vmov.u16 r3, q4[4]2449; CHECK-NEXT: vmov q5[2], q5[0], r3, r22450; CHECK-NEXT: vmov.u16 r2, q4[7]2451; CHECK-NEXT: vmov.u16 r3, q4[5]2452; CHECK-NEXT: vmov q5[3], q5[1], r3, r22453; CHECK-NEXT: vcmp.i32 ne, q5, zr2454; CHECK-NEXT: vpsel q1, q2, q12455; CHECK-NEXT: vmov r2, r3, d22456; CHECK-NEXT: vmov q2[2], q2[0], r2, r32457; CHECK-NEXT: vmov q2[3], q2[1], r2, r32458; CHECK-NEXT: vmov.s8 r2, q0[13]2459; CHECK-NEXT: vmov.s8 r3, q0[12]2460; CHECK-NEXT: vcmp.i32 ne, q2, zr2461; CHECK-NEXT: vmov q2[2], q2[0], r3, r22462; CHECK-NEXT: asrs r2, r2, #312463; CHECK-NEXT: asrs r3, r3, #312464; CHECK-NEXT: vmov q2[3], q2[1], r3, r22465; CHECK-NEXT: vpsel q2, q2, q32466; CHECK-NEXT: vmov r2, r3, d42467; CHECK-NEXT: adds.w lr, lr, r22468; CHECK-NEXT: adc.w r12, r12, r32469; CHECK-NEXT: vmov r2, r3, d52470; CHECK-NEXT: adds.w lr, lr, r22471; CHECK-NEXT: adc.w r12, r12, r32472; CHECK-NEXT: vmov r2, r3, d32473; CHECK-NEXT: vmov q1[2], q1[0], r2, r32474; CHECK-NEXT: vmov q1[3], q1[1], r2, r32475; CHECK-NEXT: vmov.s8 r2, q0[15]2476; CHECK-NEXT: vmov.s8 r3, q0[14]2477; CHECK-NEXT: vcmp.i32 ne, q1, zr2478; CHECK-NEXT: vmov q0[2], q0[0], r3, r22479; CHECK-NEXT: asrs r2, r2, #312480; CHECK-NEXT: asrs r3, r3, #312481; CHECK-NEXT: vmov q0[3], q0[1], r3, r22482; CHECK-NEXT: vpsel q0, q0, q32483; CHECK-NEXT: vmov r2, r3, d02484; CHECK-NEXT: adds.w lr, lr, r22485; CHECK-NEXT: adc.w r12, r12, r32486; CHECK-NEXT: vmov r2, r3, d12487; CHECK-NEXT: adds.w r2, r2, lr2488; CHECK-NEXT: adc.w r3, r3, r122489; CHECK-NEXT: adds r0, r0, r22490; CHECK-NEXT: adcs r1, r32491; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}2492; CHECK-NEXT: pop {r7, pc}2493entry:2494 %c = icmp eq <16 x i8> %b, zeroinitializer2495 %xx = sext <16 x i8> %x to <16 x i64>2496 %s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer2497 %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)2498 %r = add i64 %z, %a2499 ret i64 %r2500}2501 2502define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %b, i64 %a) {2503; CHECK-LABEL: add_v2i8_v2i64_acc_zext:2504; CHECK: @ %bb.0: @ %entry2505; CHECK-NEXT: .save {r7, lr}2506; CHECK-NEXT: push {r7, lr}2507; CHECK-NEXT: vmov.i64 q2, #0xff2508; CHECK-NEXT: movs r3, #02509; CHECK-NEXT: vand q1, q1, q22510; CHECK-NEXT: vand q0, q0, q22511; CHECK-NEXT: vmov r2, s42512; CHECK-NEXT: cmp r2, #02513; CHECK-NEXT: csetm r2, eq2514; CHECK-NEXT: bfi r3, r2, #0, #82515; CHECK-NEXT: vmov r2, s62516; CHECK-NEXT: vmov.i32 q1, #0x02517; CHECK-NEXT: cmp r2, #02518; CHECK-NEXT: csetm r2, eq2519; CHECK-NEXT: bfi r3, r2, #8, #82520; CHECK-NEXT: vmsr p0, r32521; CHECK-NEXT: vpsel q0, q0, q12522; CHECK-NEXT: vmov r12, lr, d12523; CHECK-NEXT: vmov r2, r3, d02524; CHECK-NEXT: add r2, r122525; CHECK-NEXT: orr.w r3, r3, lr2526; CHECK-NEXT: adds r0, r0, r22527; CHECK-NEXT: adcs r1, r32528; CHECK-NEXT: pop {r7, pc}2529entry:2530 %c = icmp eq <2 x i8> %b, zeroinitializer2531 %xx = zext <2 x i8> %x to <2 x i64>2532 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer2533 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)2534 %r = add i64 %z, %a2535 ret i64 %r2536}2537 2538define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %b, i64 %a) {2539; CHECK-LABEL: add_v2i8_v2i64_acc_sext:2540; CHECK: @ %bb.0: @ %entry2541; CHECK-NEXT: .save {r7, lr}2542; CHECK-NEXT: push {r7, lr}2543; CHECK-NEXT: vmov.i32 q2, #0xff2544; CHECK-NEXT: movs r3, #02545; CHECK-NEXT: vand q1, q1, q22546; CHECK-NEXT: vmov r2, s42547; CHECK-NEXT: cmp r2, #02548; CHECK-NEXT: csetm r2, eq2549; CHECK-NEXT: bfi r3, r2, #0, #82550; CHECK-NEXT: vmov r2, s62551; CHECK-NEXT: vmov.i32 q1, #0x02552; CHECK-NEXT: cmp r2, #02553; CHECK-NEXT: csetm r2, eq2554; CHECK-NEXT: bfi r3, r2, #8, #82555; CHECK-NEXT: vmov r2, s22556; CHECK-NEXT: vmsr p0, r32557; CHECK-NEXT: vmov r3, s02558; CHECK-NEXT: sxtb r2, r22559; CHECK-NEXT: sxtb r3, r32560; CHECK-NEXT: vmov q0[2], q0[0], r3, r22561; CHECK-NEXT: asrs r2, r2, #312562; CHECK-NEXT: asrs r3, r3, #312563; CHECK-NEXT: vmov q0[3], q0[1], r3, r22564; CHECK-NEXT: vpsel q0, q0, q12565; CHECK-NEXT: vmov lr, r12, d12566; CHECK-NEXT: vmov r3, r2, d02567; CHECK-NEXT: adds.w r3, r3, lr2568; CHECK-NEXT: adc.w r2, r2, r122569; CHECK-NEXT: adds r0, r0, r32570; CHECK-NEXT: adcs r1, r22571; CHECK-NEXT: pop {r7, pc}2572entry:2573 %c = icmp eq <2 x i8> %b, zeroinitializer2574 %xx = sext <2 x i8> %x to <2 x i64>2575 %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer2576 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)2577 %r = add i64 %z, %a2578 ret i64 %r2579}2580 2581define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %b, i64 %a) {2582; CHECK-LABEL: add_v2i64_v2i64_acc:2583; CHECK: @ %bb.0: @ %entry2584; CHECK-NEXT: .save {r7, lr}2585; CHECK-NEXT: push {r7, lr}2586; CHECK-NEXT: vmov r2, r3, d22587; CHECK-NEXT: mov.w r12, #02588; CHECK-NEXT: orrs r2, r32589; CHECK-NEXT: csetm r2, eq2590; CHECK-NEXT: bfi r12, r2, #0, #82591; CHECK-NEXT: vmov r2, r3, d32592; CHECK-NEXT: vmov.i32 q1, #0x02593; CHECK-NEXT: orrs r2, r32594; CHECK-NEXT: csetm r2, eq2595; CHECK-NEXT: bfi r12, r2, #8, #82596; CHECK-NEXT: vmsr p0, r122597; CHECK-NEXT: vpsel q0, q0, q12598; CHECK-NEXT: vmov lr, r12, d12599; CHECK-NEXT: vmov r3, r2, d02600; CHECK-NEXT: adds.w r3, r3, lr2601; CHECK-NEXT: adc.w r2, r2, r122602; CHECK-NEXT: adds r0, r0, r32603; CHECK-NEXT: adcs r1, r22604; CHECK-NEXT: pop {r7, pc}2605entry:2606 %c = icmp eq <2 x i64> %b, zeroinitializer2607 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer2608 %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)2609 %r = add i64 %z, %a2610 ret i64 %r2611}2612 2613declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)2614declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)2615declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)2616declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)2617declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)2618declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)2619declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)2620declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)2621declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)2622declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)2623