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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK3 4define arm_aapcs_vfpcc i32 @and_v2i32(<2 x i32> %x) {5; CHECK-LABEL: and_v2i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmov r0, s28; CHECK-NEXT: vmov r1, s09; CHECK-NEXT: ands r0, r110; CHECK-NEXT: bx lr11entry:12 %z = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %x)13 ret i32 %z14}15 16define arm_aapcs_vfpcc i32 @and_v4i32(<4 x i32> %x) {17; CHECK-LABEL: and_v4i32:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmov r0, r1, d120; CHECK-NEXT: ands r0, r121; CHECK-NEXT: vmov r1, r2, d022; CHECK-NEXT: ands r1, r223; CHECK-NEXT: ands r0, r124; CHECK-NEXT: bx lr25entry:26 %z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %x)27 ret i32 %z28}29 30define arm_aapcs_vfpcc i32 @and_v8i32(<8 x i32> %x) {31; CHECK-LABEL: and_v8i32:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vand q0, q0, q134; CHECK-NEXT: vmov r0, r1, d135; CHECK-NEXT: ands r0, r136; CHECK-NEXT: vmov r1, r2, d037; CHECK-NEXT: ands r1, r238; CHECK-NEXT: ands r0, r139; CHECK-NEXT: bx lr40entry:41 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %x)42 ret i32 %z43}44 45define arm_aapcs_vfpcc i16 @and_v4i16(<4 x i16> %x) {46; CHECK-LABEL: and_v4i16:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vmov r0, r1, d149; CHECK-NEXT: ands r0, r150; CHECK-NEXT: vmov r1, r2, d051; CHECK-NEXT: ands r1, r252; CHECK-NEXT: ands r0, r153; CHECK-NEXT: bx lr54entry:55 %z = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %x)56 ret i16 %z57}58 59define arm_aapcs_vfpcc i16 @and_v8i16(<8 x i16> %x) {60; CHECK-LABEL: and_v8i16:61; CHECK: @ %bb.0: @ %entry62; CHECK-NEXT: vrev32.16 q1, q063; CHECK-NEXT: vand q0, q0, q164; CHECK-NEXT: vmov.u16 r0, q0[6]65; CHECK-NEXT: vmov.u16 r1, q0[4]66; CHECK-NEXT: ands r0, r167; CHECK-NEXT: vmov.u16 r1, q0[2]68; CHECK-NEXT: vmov.u16 r2, q0[0]69; CHECK-NEXT: ands r1, r270; CHECK-NEXT: ands r0, r171; CHECK-NEXT: bx lr72entry:73 %z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %x)74 ret i16 %z75}76 77define arm_aapcs_vfpcc i16 @and_v16i16(<16 x i16> %x) {78; CHECK-LABEL: and_v16i16:79; CHECK: @ %bb.0: @ %entry80; CHECK-NEXT: vand q0, q0, q181; CHECK-NEXT: vrev32.16 q1, q082; CHECK-NEXT: vand q0, q0, q183; CHECK-NEXT: vmov.u16 r0, q0[6]84; CHECK-NEXT: vmov.u16 r1, q0[4]85; CHECK-NEXT: ands r0, r186; CHECK-NEXT: vmov.u16 r1, q0[2]87; CHECK-NEXT: vmov.u16 r2, q0[0]88; CHECK-NEXT: ands r1, r289; CHECK-NEXT: ands r0, r190; CHECK-NEXT: bx lr91entry:92 %z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %x)93 ret i16 %z94}95 96define arm_aapcs_vfpcc i8 @and_v8i8(<8 x i8> %x) {97; CHECK-LABEL: and_v8i8:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vrev32.16 q1, q0100; CHECK-NEXT: vand q0, q0, q1101; CHECK-NEXT: vmov.u16 r0, q0[6]102; CHECK-NEXT: vmov.u16 r1, q0[4]103; CHECK-NEXT: ands r0, r1104; CHECK-NEXT: vmov.u16 r1, q0[2]105; CHECK-NEXT: vmov.u16 r2, q0[0]106; CHECK-NEXT: ands r1, r2107; CHECK-NEXT: ands r0, r1108; CHECK-NEXT: bx lr109entry:110 %z = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %x)111 ret i8 %z112}113 114define arm_aapcs_vfpcc i8 @and_v16i8(<16 x i8> %x) {115; CHECK-LABEL: and_v16i8:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vrev16.8 q1, q0118; CHECK-NEXT: vand q0, q0, q1119; CHECK-NEXT: vrev32.8 q1, q0120; CHECK-NEXT: vand q0, q0, q1121; CHECK-NEXT: vmov.u8 r0, q0[12]122; CHECK-NEXT: vmov.u8 r1, q0[8]123; CHECK-NEXT: ands r0, r1124; CHECK-NEXT: vmov.u8 r1, q0[4]125; CHECK-NEXT: vmov.u8 r2, q0[0]126; CHECK-NEXT: ands r1, r2127; CHECK-NEXT: ands r0, r1128; CHECK-NEXT: bx lr129entry:130 %z = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %x)131 ret i8 %z132}133 134define arm_aapcs_vfpcc i8 @and_v32i8(<32 x i8> %x) {135; CHECK-LABEL: and_v32i8:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vand q0, q0, q1138; CHECK-NEXT: vrev16.8 q1, q0139; CHECK-NEXT: vand q0, q0, q1140; CHECK-NEXT: vrev32.8 q1, q0141; CHECK-NEXT: vand q0, q0, q1142; CHECK-NEXT: vmov.u8 r0, q0[12]143; CHECK-NEXT: vmov.u8 r1, q0[8]144; CHECK-NEXT: ands r0, r1145; CHECK-NEXT: vmov.u8 r1, q0[4]146; CHECK-NEXT: vmov.u8 r2, q0[0]147; CHECK-NEXT: ands r1, r2148; CHECK-NEXT: ands r0, r1149; CHECK-NEXT: bx lr150entry:151 %z = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %x)152 ret i8 %z153}154 155define arm_aapcs_vfpcc i64 @and_v1i64(<1 x i64> %x) {156; CHECK-LABEL: and_v1i64:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: bx lr159entry:160 %z = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %x)161 ret i64 %z162}163 164define arm_aapcs_vfpcc i64 @and_v2i64(<2 x i64> %x) {165; CHECK-LABEL: and_v2i64:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmov r0, r1, d1168; CHECK-NEXT: vmov r2, r3, d0169; CHECK-NEXT: ands r0, r2170; CHECK-NEXT: ands r1, r3171; CHECK-NEXT: bx lr172entry:173 %z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %x)174 ret i64 %z175}176 177define arm_aapcs_vfpcc i64 @and_v4i64(<4 x i64> %x) {178; CHECK-LABEL: and_v4i64:179; CHECK: @ %bb.0: @ %entry180; CHECK-NEXT: vand q0, q0, q1181; CHECK-NEXT: vmov r0, r1, d1182; CHECK-NEXT: vmov r2, r3, d0183; CHECK-NEXT: ands r0, r2184; CHECK-NEXT: ands r1, r3185; CHECK-NEXT: bx lr186entry:187 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %x)188 ret i64 %z189}190 191define arm_aapcs_vfpcc i32 @and_v2i32_acc(<2 x i32> %x, i32 %y) {192; CHECK-LABEL: and_v2i32_acc:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vmov r1, s2195; CHECK-NEXT: vmov r2, s0196; CHECK-NEXT: ands r1, r2197; CHECK-NEXT: ands r0, r1198; CHECK-NEXT: bx lr199entry:200 %z = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %x)201 %r = and i32 %y, %z202 ret i32 %r203}204 205define arm_aapcs_vfpcc i32 @and_v4i32_acc(<4 x i32> %x, i32 %y) {206; CHECK-LABEL: and_v4i32_acc:207; CHECK: @ %bb.0: @ %entry208; CHECK-NEXT: vmov r1, r2, d1209; CHECK-NEXT: ands r1, r2210; CHECK-NEXT: vmov r2, r3, d0211; CHECK-NEXT: ands r2, r3212; CHECK-NEXT: ands r1, r2213; CHECK-NEXT: ands r0, r1214; CHECK-NEXT: bx lr215entry:216 %z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %x)217 %r = and i32 %y, %z218 ret i32 %r219}220 221define arm_aapcs_vfpcc i32 @and_v8i32_acc(<8 x i32> %x, i32 %y) {222; CHECK-LABEL: and_v8i32_acc:223; CHECK: @ %bb.0: @ %entry224; CHECK-NEXT: vand q0, q0, q1225; CHECK-NEXT: vmov r1, r2, d1226; CHECK-NEXT: ands r1, r2227; CHECK-NEXT: vmov r2, r3, d0228; CHECK-NEXT: ands r2, r3229; CHECK-NEXT: ands r1, r2230; CHECK-NEXT: ands r0, r1231; CHECK-NEXT: bx lr232entry:233 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %x)234 %r = and i32 %y, %z235 ret i32 %r236}237 238define arm_aapcs_vfpcc i16 @and_v4i16_acc(<4 x i16> %x, i16 %y) {239; CHECK-LABEL: and_v4i16_acc:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vmov r1, r2, d1242; CHECK-NEXT: ands r1, r2243; CHECK-NEXT: vmov r2, r3, d0244; CHECK-NEXT: ands r2, r3245; CHECK-NEXT: ands r1, r2246; CHECK-NEXT: ands r0, r1247; CHECK-NEXT: bx lr248entry:249 %z = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %x)250 %r = and i16 %y, %z251 ret i16 %r252}253 254define arm_aapcs_vfpcc i16 @and_v8i16_acc(<8 x i16> %x, i16 %y) {255; CHECK-LABEL: and_v8i16_acc:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: vrev32.16 q1, q0258; CHECK-NEXT: vand q0, q0, q1259; CHECK-NEXT: vmov.u16 r1, q0[6]260; CHECK-NEXT: vmov.u16 r2, q0[4]261; CHECK-NEXT: ands r1, r2262; CHECK-NEXT: vmov.u16 r2, q0[2]263; CHECK-NEXT: vmov.u16 r3, q0[0]264; CHECK-NEXT: ands r2, r3265; CHECK-NEXT: ands r1, r2266; CHECK-NEXT: ands r0, r1267; CHECK-NEXT: bx lr268entry:269 %z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %x)270 %r = and i16 %y, %z271 ret i16 %r272}273 274define arm_aapcs_vfpcc i16 @and_v16i16_acc(<16 x i16> %x, i16 %y) {275; CHECK-LABEL: and_v16i16_acc:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vand q0, q0, q1278; CHECK-NEXT: vrev32.16 q1, q0279; CHECK-NEXT: vand q0, q0, q1280; CHECK-NEXT: vmov.u16 r1, q0[6]281; CHECK-NEXT: vmov.u16 r2, q0[4]282; CHECK-NEXT: ands r1, r2283; CHECK-NEXT: vmov.u16 r2, q0[2]284; CHECK-NEXT: vmov.u16 r3, q0[0]285; CHECK-NEXT: ands r2, r3286; CHECK-NEXT: ands r1, r2287; CHECK-NEXT: ands r0, r1288; CHECK-NEXT: bx lr289entry:290 %z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %x)291 %r = and i16 %y, %z292 ret i16 %r293}294 295define arm_aapcs_vfpcc i8 @and_v8i8_acc(<8 x i8> %x, i8 %y) {296; CHECK-LABEL: and_v8i8_acc:297; CHECK: @ %bb.0: @ %entry298; CHECK-NEXT: vrev32.16 q1, q0299; CHECK-NEXT: vand q0, q0, q1300; CHECK-NEXT: vmov.u16 r1, q0[6]301; CHECK-NEXT: vmov.u16 r2, q0[4]302; CHECK-NEXT: ands r1, r2303; CHECK-NEXT: vmov.u16 r2, q0[2]304; CHECK-NEXT: vmov.u16 r3, q0[0]305; CHECK-NEXT: ands r2, r3306; CHECK-NEXT: ands r1, r2307; CHECK-NEXT: ands r0, r1308; CHECK-NEXT: bx lr309entry:310 %z = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %x)311 %r = and i8 %y, %z312 ret i8 %r313}314 315define arm_aapcs_vfpcc i8 @and_v16i8_acc(<16 x i8> %x, i8 %y) {316; CHECK-LABEL: and_v16i8_acc:317; CHECK: @ %bb.0: @ %entry318; CHECK-NEXT: vrev16.8 q1, q0319; CHECK-NEXT: vand q0, q0, q1320; CHECK-NEXT: vrev32.8 q1, q0321; CHECK-NEXT: vand q0, q0, q1322; CHECK-NEXT: vmov.u8 r1, q0[12]323; CHECK-NEXT: vmov.u8 r2, q0[8]324; CHECK-NEXT: ands r1, r2325; CHECK-NEXT: vmov.u8 r2, q0[4]326; CHECK-NEXT: vmov.u8 r3, q0[0]327; CHECK-NEXT: ands r2, r3328; CHECK-NEXT: ands r1, r2329; CHECK-NEXT: ands r0, r1330; CHECK-NEXT: bx lr331entry:332 %z = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %x)333 %r = and i8 %y, %z334 ret i8 %r335}336 337define arm_aapcs_vfpcc i8 @and_v32i8_acc(<32 x i8> %x, i8 %y) {338; CHECK-LABEL: and_v32i8_acc:339; CHECK: @ %bb.0: @ %entry340; CHECK-NEXT: vand q0, q0, q1341; CHECK-NEXT: vrev16.8 q1, q0342; CHECK-NEXT: vand q0, q0, q1343; CHECK-NEXT: vrev32.8 q1, q0344; CHECK-NEXT: vand q0, q0, q1345; CHECK-NEXT: vmov.u8 r1, q0[12]346; CHECK-NEXT: vmov.u8 r2, q0[8]347; CHECK-NEXT: ands r1, r2348; CHECK-NEXT: vmov.u8 r2, q0[4]349; CHECK-NEXT: vmov.u8 r3, q0[0]350; CHECK-NEXT: ands r2, r3351; CHECK-NEXT: ands r1, r2352; CHECK-NEXT: ands r0, r1353; CHECK-NEXT: bx lr354entry:355 %z = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %x)356 %r = and i8 %y, %z357 ret i8 %r358}359 360define arm_aapcs_vfpcc i64 @and_v1i64_acc(<1 x i64> %x, i64 %y) {361; CHECK-LABEL: and_v1i64_acc:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: ands r0, r2364; CHECK-NEXT: ands r1, r3365; CHECK-NEXT: bx lr366entry:367 %z = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %x)368 %r = and i64 %y, %z369 ret i64 %r370}371 372define arm_aapcs_vfpcc i64 @and_v2i64_acc(<2 x i64> %x, i64 %y) {373; CHECK-LABEL: and_v2i64_acc:374; CHECK: @ %bb.0: @ %entry375; CHECK-NEXT: .save {r7, lr}376; CHECK-NEXT: push {r7, lr}377; CHECK-NEXT: vmov r2, r12, d1378; CHECK-NEXT: vmov r3, lr, d0379; CHECK-NEXT: ands r2, r3380; CHECK-NEXT: ands r0, r2381; CHECK-NEXT: and.w r2, lr, r12382; CHECK-NEXT: ands r1, r2383; CHECK-NEXT: pop {r7, pc}384entry:385 %z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %x)386 %r = and i64 %y, %z387 ret i64 %r388}389 390define arm_aapcs_vfpcc i64 @and_v4i64_acc(<4 x i64> %x, i64 %y) {391; CHECK-LABEL: and_v4i64_acc:392; CHECK: @ %bb.0: @ %entry393; CHECK-NEXT: .save {r7, lr}394; CHECK-NEXT: push {r7, lr}395; CHECK-NEXT: vand q0, q0, q1396; CHECK-NEXT: vmov r2, r12, d1397; CHECK-NEXT: vmov r3, lr, d0398; CHECK-NEXT: ands r2, r3399; CHECK-NEXT: ands r0, r2400; CHECK-NEXT: and.w r2, lr, r12401; CHECK-NEXT: ands r1, r2402; CHECK-NEXT: pop {r7, pc}403entry:404 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %x)405 %r = and i64 %y, %z406 ret i64 %r407}408 409define arm_aapcs_vfpcc i32 @or_v2i32(<2 x i32> %x) {410; CHECK-LABEL: or_v2i32:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vmov r0, s2413; CHECK-NEXT: vmov r1, s0414; CHECK-NEXT: orrs r0, r1415; CHECK-NEXT: bx lr416entry:417 %z = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %x)418 ret i32 %z419}420 421define arm_aapcs_vfpcc i32 @or_v4i32(<4 x i32> %x) {422; CHECK-LABEL: or_v4i32:423; CHECK: @ %bb.0: @ %entry424; CHECK-NEXT: vmov r0, r1, d1425; CHECK-NEXT: orrs r0, r1426; CHECK-NEXT: vmov r1, r2, d0427; CHECK-NEXT: orrs r1, r2428; CHECK-NEXT: orrs r0, r1429; CHECK-NEXT: bx lr430entry:431 %z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %x)432 ret i32 %z433}434 435define arm_aapcs_vfpcc i32 @or_v8i32(<8 x i32> %x) {436; CHECK-LABEL: or_v8i32:437; CHECK: @ %bb.0: @ %entry438; CHECK-NEXT: vorr q0, q0, q1439; CHECK-NEXT: vmov r0, r1, d1440; CHECK-NEXT: orrs r0, r1441; CHECK-NEXT: vmov r1, r2, d0442; CHECK-NEXT: orrs r1, r2443; CHECK-NEXT: orrs r0, r1444; CHECK-NEXT: bx lr445entry:446 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %x)447 ret i32 %z448}449 450define arm_aapcs_vfpcc i16 @or_v4i16(<4 x i16> %x) {451; CHECK-LABEL: or_v4i16:452; CHECK: @ %bb.0: @ %entry453; CHECK-NEXT: vmov r0, r1, d1454; CHECK-NEXT: orrs r0, r1455; CHECK-NEXT: vmov r1, r2, d0456; CHECK-NEXT: orrs r1, r2457; CHECK-NEXT: orrs r0, r1458; CHECK-NEXT: bx lr459entry:460 %z = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %x)461 ret i16 %z462}463 464define arm_aapcs_vfpcc i16 @or_v8i16(<8 x i16> %x) {465; CHECK-LABEL: or_v8i16:466; CHECK: @ %bb.0: @ %entry467; CHECK-NEXT: vrev32.16 q1, q0468; CHECK-NEXT: vorr q0, q0, q1469; CHECK-NEXT: vmov.u16 r0, q0[6]470; CHECK-NEXT: vmov.u16 r1, q0[4]471; CHECK-NEXT: orrs r0, r1472; CHECK-NEXT: vmov.u16 r1, q0[2]473; CHECK-NEXT: vmov.u16 r2, q0[0]474; CHECK-NEXT: orrs r1, r2475; CHECK-NEXT: orrs r0, r1476; CHECK-NEXT: bx lr477entry:478 %z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %x)479 ret i16 %z480}481 482define arm_aapcs_vfpcc i16 @or_v16i16(<16 x i16> %x) {483; CHECK-LABEL: or_v16i16:484; CHECK: @ %bb.0: @ %entry485; CHECK-NEXT: vorr q0, q0, q1486; CHECK-NEXT: vrev32.16 q1, q0487; CHECK-NEXT: vorr q0, q0, q1488; CHECK-NEXT: vmov.u16 r0, q0[6]489; CHECK-NEXT: vmov.u16 r1, q0[4]490; CHECK-NEXT: orrs r0, r1491; CHECK-NEXT: vmov.u16 r1, q0[2]492; CHECK-NEXT: vmov.u16 r2, q0[0]493; CHECK-NEXT: orrs r1, r2494; CHECK-NEXT: orrs r0, r1495; CHECK-NEXT: bx lr496entry:497 %z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %x)498 ret i16 %z499}500 501define arm_aapcs_vfpcc i8 @or_v8i8(<8 x i8> %x) {502; CHECK-LABEL: or_v8i8:503; CHECK: @ %bb.0: @ %entry504; CHECK-NEXT: vrev32.16 q1, q0505; CHECK-NEXT: vorr q0, q0, q1506; CHECK-NEXT: vmov.u16 r0, q0[6]507; CHECK-NEXT: vmov.u16 r1, q0[4]508; CHECK-NEXT: orrs r0, r1509; CHECK-NEXT: vmov.u16 r1, q0[2]510; CHECK-NEXT: vmov.u16 r2, q0[0]511; CHECK-NEXT: orrs r1, r2512; CHECK-NEXT: orrs r0, r1513; CHECK-NEXT: bx lr514entry:515 %z = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %x)516 ret i8 %z517}518 519define arm_aapcs_vfpcc i8 @or_v16i8(<16 x i8> %x) {520; CHECK-LABEL: or_v16i8:521; CHECK: @ %bb.0: @ %entry522; CHECK-NEXT: vrev16.8 q1, q0523; CHECK-NEXT: vorr q0, q0, q1524; CHECK-NEXT: vrev32.8 q1, q0525; CHECK-NEXT: vorr q0, q0, q1526; CHECK-NEXT: vmov.u8 r0, q0[12]527; CHECK-NEXT: vmov.u8 r1, q0[8]528; CHECK-NEXT: orrs r0, r1529; CHECK-NEXT: vmov.u8 r1, q0[4]530; CHECK-NEXT: vmov.u8 r2, q0[0]531; CHECK-NEXT: orrs r1, r2532; CHECK-NEXT: orrs r0, r1533; CHECK-NEXT: bx lr534entry:535 %z = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)536 ret i8 %z537}538 539define arm_aapcs_vfpcc i8 @or_v32i8(<32 x i8> %x) {540; CHECK-LABEL: or_v32i8:541; CHECK: @ %bb.0: @ %entry542; CHECK-NEXT: vorr q0, q0, q1543; CHECK-NEXT: vrev16.8 q1, q0544; CHECK-NEXT: vorr q0, q0, q1545; CHECK-NEXT: vrev32.8 q1, q0546; CHECK-NEXT: vorr q0, q0, q1547; CHECK-NEXT: vmov.u8 r0, q0[12]548; CHECK-NEXT: vmov.u8 r1, q0[8]549; CHECK-NEXT: orrs r0, r1550; CHECK-NEXT: vmov.u8 r1, q0[4]551; CHECK-NEXT: vmov.u8 r2, q0[0]552; CHECK-NEXT: orrs r1, r2553; CHECK-NEXT: orrs r0, r1554; CHECK-NEXT: bx lr555entry:556 %z = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %x)557 ret i8 %z558}559 560define arm_aapcs_vfpcc i64 @or_v1i64(<1 x i64> %x) {561; CHECK-LABEL: or_v1i64:562; CHECK: @ %bb.0: @ %entry563; CHECK-NEXT: bx lr564entry:565 %z = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %x)566 ret i64 %z567}568 569define arm_aapcs_vfpcc i64 @or_v2i64(<2 x i64> %x) {570; CHECK-LABEL: or_v2i64:571; CHECK: @ %bb.0: @ %entry572; CHECK-NEXT: vmov r0, r1, d1573; CHECK-NEXT: vmov r2, r3, d0574; CHECK-NEXT: orrs r0, r2575; CHECK-NEXT: orrs r1, r3576; CHECK-NEXT: bx lr577entry:578 %z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %x)579 ret i64 %z580}581 582define arm_aapcs_vfpcc i64 @or_v4i64(<4 x i64> %x) {583; CHECK-LABEL: or_v4i64:584; CHECK: @ %bb.0: @ %entry585; CHECK-NEXT: vorr q0, q0, q1586; CHECK-NEXT: vmov r0, r1, d1587; CHECK-NEXT: vmov r2, r3, d0588; CHECK-NEXT: orrs r0, r2589; CHECK-NEXT: orrs r1, r3590; CHECK-NEXT: bx lr591entry:592 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %x)593 ret i64 %z594}595 596define arm_aapcs_vfpcc i32 @or_v2i32_acc(<2 x i32> %x, i32 %y) {597; CHECK-LABEL: or_v2i32_acc:598; CHECK: @ %bb.0: @ %entry599; CHECK-NEXT: vmov r1, s2600; CHECK-NEXT: vmov r2, s0601; CHECK-NEXT: orrs r1, r2602; CHECK-NEXT: orrs r0, r1603; CHECK-NEXT: bx lr604entry:605 %z = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %x)606 %r = or i32 %y, %z607 ret i32 %r608}609 610define arm_aapcs_vfpcc i32 @or_v4i32_acc(<4 x i32> %x, i32 %y) {611; CHECK-LABEL: or_v4i32_acc:612; CHECK: @ %bb.0: @ %entry613; CHECK-NEXT: vmov r1, r2, d1614; CHECK-NEXT: orrs r1, r2615; CHECK-NEXT: vmov r2, r3, d0616; CHECK-NEXT: orrs r2, r3617; CHECK-NEXT: orrs r1, r2618; CHECK-NEXT: orrs r0, r1619; CHECK-NEXT: bx lr620entry:621 %z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %x)622 %r = or i32 %y, %z623 ret i32 %r624}625 626define arm_aapcs_vfpcc i32 @or_v8i32_acc(<8 x i32> %x, i32 %y) {627; CHECK-LABEL: or_v8i32_acc:628; CHECK: @ %bb.0: @ %entry629; CHECK-NEXT: vorr q0, q0, q1630; CHECK-NEXT: vmov r1, r2, d1631; CHECK-NEXT: orrs r1, r2632; CHECK-NEXT: vmov r2, r3, d0633; CHECK-NEXT: orrs r2, r3634; CHECK-NEXT: orrs r1, r2635; CHECK-NEXT: orrs r0, r1636; CHECK-NEXT: bx lr637entry:638 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %x)639 %r = or i32 %y, %z640 ret i32 %r641}642 643define arm_aapcs_vfpcc i16 @or_v4i16_acc(<4 x i16> %x, i16 %y) {644; CHECK-LABEL: or_v4i16_acc:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: vmov r1, r2, d1647; CHECK-NEXT: orrs r1, r2648; CHECK-NEXT: vmov r2, r3, d0649; CHECK-NEXT: orrs r2, r3650; CHECK-NEXT: orrs r1, r2651; CHECK-NEXT: orrs r0, r1652; CHECK-NEXT: bx lr653entry:654 %z = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %x)655 %r = or i16 %y, %z656 ret i16 %r657}658 659define arm_aapcs_vfpcc i16 @or_v8i16_acc(<8 x i16> %x, i16 %y) {660; CHECK-LABEL: or_v8i16_acc:661; CHECK: @ %bb.0: @ %entry662; CHECK-NEXT: vrev32.16 q1, q0663; CHECK-NEXT: vorr q0, q0, q1664; CHECK-NEXT: vmov.u16 r1, q0[6]665; CHECK-NEXT: vmov.u16 r2, q0[4]666; CHECK-NEXT: orrs r1, r2667; CHECK-NEXT: vmov.u16 r2, q0[2]668; CHECK-NEXT: vmov.u16 r3, q0[0]669; CHECK-NEXT: orrs r2, r3670; CHECK-NEXT: orrs r1, r2671; CHECK-NEXT: orrs r0, r1672; CHECK-NEXT: bx lr673entry:674 %z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %x)675 %r = or i16 %y, %z676 ret i16 %r677}678 679define arm_aapcs_vfpcc i16 @or_v16i16_acc(<16 x i16> %x, i16 %y) {680; CHECK-LABEL: or_v16i16_acc:681; CHECK: @ %bb.0: @ %entry682; CHECK-NEXT: vorr q0, q0, q1683; CHECK-NEXT: vrev32.16 q1, q0684; CHECK-NEXT: vorr q0, q0, q1685; CHECK-NEXT: vmov.u16 r1, q0[6]686; CHECK-NEXT: vmov.u16 r2, q0[4]687; CHECK-NEXT: orrs r1, r2688; CHECK-NEXT: vmov.u16 r2, q0[2]689; CHECK-NEXT: vmov.u16 r3, q0[0]690; CHECK-NEXT: orrs r2, r3691; CHECK-NEXT: orrs r1, r2692; CHECK-NEXT: orrs r0, r1693; CHECK-NEXT: bx lr694entry:695 %z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %x)696 %r = or i16 %y, %z697 ret i16 %r698}699 700define arm_aapcs_vfpcc i8 @or_v8i8_acc(<8 x i8> %x, i8 %y) {701; CHECK-LABEL: or_v8i8_acc:702; CHECK: @ %bb.0: @ %entry703; CHECK-NEXT: vrev32.16 q1, q0704; CHECK-NEXT: vorr q0, q0, q1705; CHECK-NEXT: vmov.u16 r1, q0[6]706; CHECK-NEXT: vmov.u16 r2, q0[4]707; CHECK-NEXT: orrs r1, r2708; CHECK-NEXT: vmov.u16 r2, q0[2]709; CHECK-NEXT: vmov.u16 r3, q0[0]710; CHECK-NEXT: orrs r2, r3711; CHECK-NEXT: orrs r1, r2712; CHECK-NEXT: orrs r0, r1713; CHECK-NEXT: bx lr714entry:715 %z = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %x)716 %r = or i8 %y, %z717 ret i8 %r718}719 720define arm_aapcs_vfpcc i8 @or_v16i8_acc(<16 x i8> %x, i8 %y) {721; CHECK-LABEL: or_v16i8_acc:722; CHECK: @ %bb.0: @ %entry723; CHECK-NEXT: vrev16.8 q1, q0724; CHECK-NEXT: vorr q0, q0, q1725; CHECK-NEXT: vrev32.8 q1, q0726; CHECK-NEXT: vorr q0, q0, q1727; CHECK-NEXT: vmov.u8 r1, q0[12]728; CHECK-NEXT: vmov.u8 r2, q0[8]729; CHECK-NEXT: orrs r1, r2730; CHECK-NEXT: vmov.u8 r2, q0[4]731; CHECK-NEXT: vmov.u8 r3, q0[0]732; CHECK-NEXT: orrs r2, r3733; CHECK-NEXT: orrs r1, r2734; CHECK-NEXT: orrs r0, r1735; CHECK-NEXT: bx lr736entry:737 %z = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)738 %r = or i8 %y, %z739 ret i8 %r740}741 742define arm_aapcs_vfpcc i8 @or_v32i8_acc(<32 x i8> %x, i8 %y) {743; CHECK-LABEL: or_v32i8_acc:744; CHECK: @ %bb.0: @ %entry745; CHECK-NEXT: vorr q0, q0, q1746; CHECK-NEXT: vrev16.8 q1, q0747; CHECK-NEXT: vorr q0, q0, q1748; CHECK-NEXT: vrev32.8 q1, q0749; CHECK-NEXT: vorr q0, q0, q1750; CHECK-NEXT: vmov.u8 r1, q0[12]751; CHECK-NEXT: vmov.u8 r2, q0[8]752; CHECK-NEXT: orrs r1, r2753; CHECK-NEXT: vmov.u8 r2, q0[4]754; CHECK-NEXT: vmov.u8 r3, q0[0]755; CHECK-NEXT: orrs r2, r3756; CHECK-NEXT: orrs r1, r2757; CHECK-NEXT: orrs r0, r1758; CHECK-NEXT: bx lr759entry:760 %z = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %x)761 %r = or i8 %y, %z762 ret i8 %r763}764 765define arm_aapcs_vfpcc i64 @or_v1i64_acc(<1 x i64> %x, i64 %y) {766; CHECK-LABEL: or_v1i64_acc:767; CHECK: @ %bb.0: @ %entry768; CHECK-NEXT: orrs r0, r2769; CHECK-NEXT: orrs r1, r3770; CHECK-NEXT: bx lr771entry:772 %z = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %x)773 %r = or i64 %y, %z774 ret i64 %r775}776 777define arm_aapcs_vfpcc i64 @or_v2i64_acc(<2 x i64> %x, i64 %y) {778; CHECK-LABEL: or_v2i64_acc:779; CHECK: @ %bb.0: @ %entry780; CHECK-NEXT: .save {r7, lr}781; CHECK-NEXT: push {r7, lr}782; CHECK-NEXT: vmov r2, r12, d1783; CHECK-NEXT: vmov r3, lr, d0784; CHECK-NEXT: orrs r2, r3785; CHECK-NEXT: orrs r0, r2786; CHECK-NEXT: orr.w r2, lr, r12787; CHECK-NEXT: orrs r1, r2788; CHECK-NEXT: pop {r7, pc}789entry:790 %z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %x)791 %r = or i64 %y, %z792 ret i64 %r793}794 795define arm_aapcs_vfpcc i64 @or_v4i64_acc(<4 x i64> %x, i64 %y) {796; CHECK-LABEL: or_v4i64_acc:797; CHECK: @ %bb.0: @ %entry798; CHECK-NEXT: .save {r7, lr}799; CHECK-NEXT: push {r7, lr}800; CHECK-NEXT: vorr q0, q0, q1801; CHECK-NEXT: vmov r2, r12, d1802; CHECK-NEXT: vmov r3, lr, d0803; CHECK-NEXT: orrs r2, r3804; CHECK-NEXT: orrs r0, r2805; CHECK-NEXT: orr.w r2, lr, r12806; CHECK-NEXT: orrs r1, r2807; CHECK-NEXT: pop {r7, pc}808entry:809 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %x)810 %r = or i64 %y, %z811 ret i64 %r812}813 814define arm_aapcs_vfpcc i32 @xor_v2i32(<2 x i32> %x) {815; CHECK-LABEL: xor_v2i32:816; CHECK: @ %bb.0: @ %entry817; CHECK-NEXT: vmov r0, s2818; CHECK-NEXT: vmov r1, s0819; CHECK-NEXT: eors r0, r1820; CHECK-NEXT: bx lr821entry:822 %z = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %x)823 ret i32 %z824}825 826define arm_aapcs_vfpcc i32 @xor_v4i32(<4 x i32> %x) {827; CHECK-LABEL: xor_v4i32:828; CHECK: @ %bb.0: @ %entry829; CHECK-NEXT: vmov r0, r1, d1830; CHECK-NEXT: eors r0, r1831; CHECK-NEXT: vmov r1, r2, d0832; CHECK-NEXT: eors r1, r2833; CHECK-NEXT: eors r0, r1834; CHECK-NEXT: bx lr835entry:836 %z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %x)837 ret i32 %z838}839 840define arm_aapcs_vfpcc i32 @xor_v8i32(<8 x i32> %x) {841; CHECK-LABEL: xor_v8i32:842; CHECK: @ %bb.0: @ %entry843; CHECK-NEXT: veor q0, q0, q1844; CHECK-NEXT: vmov r0, r1, d1845; CHECK-NEXT: eors r0, r1846; CHECK-NEXT: vmov r1, r2, d0847; CHECK-NEXT: eors r1, r2848; CHECK-NEXT: eors r0, r1849; CHECK-NEXT: bx lr850entry:851 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %x)852 ret i32 %z853}854 855define arm_aapcs_vfpcc i16 @xor_v4i16(<4 x i16> %x) {856; CHECK-LABEL: xor_v4i16:857; CHECK: @ %bb.0: @ %entry858; CHECK-NEXT: vmov r0, r1, d1859; CHECK-NEXT: eors r0, r1860; CHECK-NEXT: vmov r1, r2, d0861; CHECK-NEXT: eors r1, r2862; CHECK-NEXT: eors r0, r1863; CHECK-NEXT: bx lr864entry:865 %z = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %x)866 ret i16 %z867}868 869define arm_aapcs_vfpcc i16 @xor_v8i16(<8 x i16> %x) {870; CHECK-LABEL: xor_v8i16:871; CHECK: @ %bb.0: @ %entry872; CHECK-NEXT: vrev32.16 q1, q0873; CHECK-NEXT: veor q0, q0, q1874; CHECK-NEXT: vmov.u16 r0, q0[6]875; CHECK-NEXT: vmov.u16 r1, q0[4]876; CHECK-NEXT: eors r0, r1877; CHECK-NEXT: vmov.u16 r1, q0[2]878; CHECK-NEXT: vmov.u16 r2, q0[0]879; CHECK-NEXT: eors r1, r2880; CHECK-NEXT: eors r0, r1881; CHECK-NEXT: bx lr882entry:883 %z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %x)884 ret i16 %z885}886 887define arm_aapcs_vfpcc i16 @xor_v16i16(<16 x i16> %x) {888; CHECK-LABEL: xor_v16i16:889; CHECK: @ %bb.0: @ %entry890; CHECK-NEXT: veor q0, q0, q1891; CHECK-NEXT: vrev32.16 q1, q0892; CHECK-NEXT: veor q0, q0, q1893; CHECK-NEXT: vmov.u16 r0, q0[6]894; CHECK-NEXT: vmov.u16 r1, q0[4]895; CHECK-NEXT: eors r0, r1896; CHECK-NEXT: vmov.u16 r1, q0[2]897; CHECK-NEXT: vmov.u16 r2, q0[0]898; CHECK-NEXT: eors r1, r2899; CHECK-NEXT: eors r0, r1900; CHECK-NEXT: bx lr901entry:902 %z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %x)903 ret i16 %z904}905 906define arm_aapcs_vfpcc i8 @xor_v8i8(<8 x i8> %x) {907; CHECK-LABEL: xor_v8i8:908; CHECK: @ %bb.0: @ %entry909; CHECK-NEXT: vrev32.16 q1, q0910; CHECK-NEXT: veor q0, q0, q1911; CHECK-NEXT: vmov.u16 r0, q0[6]912; CHECK-NEXT: vmov.u16 r1, q0[4]913; CHECK-NEXT: eors r0, r1914; CHECK-NEXT: vmov.u16 r1, q0[2]915; CHECK-NEXT: vmov.u16 r2, q0[0]916; CHECK-NEXT: eors r1, r2917; CHECK-NEXT: eors r0, r1918; CHECK-NEXT: bx lr919entry:920 %z = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %x)921 ret i8 %z922}923 924define arm_aapcs_vfpcc i8 @xor_v16i8(<16 x i8> %x) {925; CHECK-LABEL: xor_v16i8:926; CHECK: @ %bb.0: @ %entry927; CHECK-NEXT: vrev16.8 q1, q0928; CHECK-NEXT: veor q0, q0, q1929; CHECK-NEXT: vrev32.8 q1, q0930; CHECK-NEXT: veor q0, q0, q1931; CHECK-NEXT: vmov.u8 r0, q0[12]932; CHECK-NEXT: vmov.u8 r1, q0[8]933; CHECK-NEXT: eors r0, r1934; CHECK-NEXT: vmov.u8 r1, q0[4]935; CHECK-NEXT: vmov.u8 r2, q0[0]936; CHECK-NEXT: eors r1, r2937; CHECK-NEXT: eors r0, r1938; CHECK-NEXT: bx lr939entry:940 %z = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %x)941 ret i8 %z942}943 944define arm_aapcs_vfpcc i8 @xor_v32i8(<32 x i8> %x) {945; CHECK-LABEL: xor_v32i8:946; CHECK: @ %bb.0: @ %entry947; CHECK-NEXT: veor q0, q0, q1948; CHECK-NEXT: vrev16.8 q1, q0949; CHECK-NEXT: veor q0, q0, q1950; CHECK-NEXT: vrev32.8 q1, q0951; CHECK-NEXT: veor q0, q0, q1952; CHECK-NEXT: vmov.u8 r0, q0[12]953; CHECK-NEXT: vmov.u8 r1, q0[8]954; CHECK-NEXT: eors r0, r1955; CHECK-NEXT: vmov.u8 r1, q0[4]956; CHECK-NEXT: vmov.u8 r2, q0[0]957; CHECK-NEXT: eors r1, r2958; CHECK-NEXT: eors r0, r1959; CHECK-NEXT: bx lr960entry:961 %z = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %x)962 ret i8 %z963}964 965define arm_aapcs_vfpcc i64 @xor_v1i64(<1 x i64> %x) {966; CHECK-LABEL: xor_v1i64:967; CHECK: @ %bb.0: @ %entry968; CHECK-NEXT: bx lr969entry:970 %z = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %x)971 ret i64 %z972}973 974define arm_aapcs_vfpcc i64 @xor_v2i64(<2 x i64> %x) {975; CHECK-LABEL: xor_v2i64:976; CHECK: @ %bb.0: @ %entry977; CHECK-NEXT: vmov r0, r1, d1978; CHECK-NEXT: vmov r2, r3, d0979; CHECK-NEXT: eors r0, r2980; CHECK-NEXT: eors r1, r3981; CHECK-NEXT: bx lr982entry:983 %z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %x)984 ret i64 %z985}986 987define arm_aapcs_vfpcc i64 @xor_v4i64(<4 x i64> %x) {988; CHECK-LABEL: xor_v4i64:989; CHECK: @ %bb.0: @ %entry990; CHECK-NEXT: veor q0, q0, q1991; CHECK-NEXT: vmov r0, r1, d1992; CHECK-NEXT: vmov r2, r3, d0993; CHECK-NEXT: eors r0, r2994; CHECK-NEXT: eors r1, r3995; CHECK-NEXT: bx lr996entry:997 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %x)998 ret i64 %z999}1000 1001define arm_aapcs_vfpcc i32 @xor_v2i32_acc(<2 x i32> %x, i32 %y) {1002; CHECK-LABEL: xor_v2i32_acc:1003; CHECK: @ %bb.0: @ %entry1004; CHECK-NEXT: vmov r1, s21005; CHECK-NEXT: vmov r2, s01006; CHECK-NEXT: eors r1, r21007; CHECK-NEXT: eors r0, r11008; CHECK-NEXT: bx lr1009entry:1010 %z = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %x)1011 %r = xor i32 %y, %z1012 ret i32 %r1013}1014 1015define arm_aapcs_vfpcc i32 @xor_v4i32_acc(<4 x i32> %x, i32 %y) {1016; CHECK-LABEL: xor_v4i32_acc:1017; CHECK: @ %bb.0: @ %entry1018; CHECK-NEXT: vmov r1, r2, d11019; CHECK-NEXT: eors r1, r21020; CHECK-NEXT: vmov r2, r3, d01021; CHECK-NEXT: eors r2, r31022; CHECK-NEXT: eors r1, r21023; CHECK-NEXT: eors r0, r11024; CHECK-NEXT: bx lr1025entry:1026 %z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %x)1027 %r = xor i32 %y, %z1028 ret i32 %r1029}1030 1031define arm_aapcs_vfpcc i32 @xor_v8i32_acc(<8 x i32> %x, i32 %y) {1032; CHECK-LABEL: xor_v8i32_acc:1033; CHECK: @ %bb.0: @ %entry1034; CHECK-NEXT: veor q0, q0, q11035; CHECK-NEXT: vmov r1, r2, d11036; CHECK-NEXT: eors r1, r21037; CHECK-NEXT: vmov r2, r3, d01038; CHECK-NEXT: eors r2, r31039; CHECK-NEXT: eors r1, r21040; CHECK-NEXT: eors r0, r11041; CHECK-NEXT: bx lr1042entry:1043 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %x)1044 %r = xor i32 %y, %z1045 ret i32 %r1046}1047 1048define arm_aapcs_vfpcc i16 @xor_v4i16_acc(<4 x i16> %x, i16 %y) {1049; CHECK-LABEL: xor_v4i16_acc:1050; CHECK: @ %bb.0: @ %entry1051; CHECK-NEXT: vmov r1, r2, d11052; CHECK-NEXT: eors r1, r21053; CHECK-NEXT: vmov r2, r3, d01054; CHECK-NEXT: eors r2, r31055; CHECK-NEXT: eors r1, r21056; CHECK-NEXT: eors r0, r11057; CHECK-NEXT: bx lr1058entry:1059 %z = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %x)1060 %r = xor i16 %y, %z1061 ret i16 %r1062}1063 1064define arm_aapcs_vfpcc i16 @xor_v8i16_acc(<8 x i16> %x, i16 %y) {1065; CHECK-LABEL: xor_v8i16_acc:1066; CHECK: @ %bb.0: @ %entry1067; CHECK-NEXT: vrev32.16 q1, q01068; CHECK-NEXT: veor q0, q0, q11069; CHECK-NEXT: vmov.u16 r1, q0[6]1070; CHECK-NEXT: vmov.u16 r2, q0[4]1071; CHECK-NEXT: eors r1, r21072; CHECK-NEXT: vmov.u16 r2, q0[2]1073; CHECK-NEXT: vmov.u16 r3, q0[0]1074; CHECK-NEXT: eors r2, r31075; CHECK-NEXT: eors r1, r21076; CHECK-NEXT: eors r0, r11077; CHECK-NEXT: bx lr1078entry:1079 %z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %x)1080 %r = xor i16 %y, %z1081 ret i16 %r1082}1083 1084define arm_aapcs_vfpcc i16 @xor_v16i16_acc(<16 x i16> %x, i16 %y) {1085; CHECK-LABEL: xor_v16i16_acc:1086; CHECK: @ %bb.0: @ %entry1087; CHECK-NEXT: veor q0, q0, q11088; CHECK-NEXT: vrev32.16 q1, q01089; CHECK-NEXT: veor q0, q0, q11090; CHECK-NEXT: vmov.u16 r1, q0[6]1091; CHECK-NEXT: vmov.u16 r2, q0[4]1092; CHECK-NEXT: eors r1, r21093; CHECK-NEXT: vmov.u16 r2, q0[2]1094; CHECK-NEXT: vmov.u16 r3, q0[0]1095; CHECK-NEXT: eors r2, r31096; CHECK-NEXT: eors r1, r21097; CHECK-NEXT: eors r0, r11098; CHECK-NEXT: bx lr1099entry:1100 %z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %x)1101 %r = xor i16 %y, %z1102 ret i16 %r1103}1104 1105define arm_aapcs_vfpcc i8 @xor_v8i8_acc(<8 x i8> %x, i8 %y) {1106; CHECK-LABEL: xor_v8i8_acc:1107; CHECK: @ %bb.0: @ %entry1108; CHECK-NEXT: vrev32.16 q1, q01109; CHECK-NEXT: veor q0, q0, q11110; CHECK-NEXT: vmov.u16 r1, q0[6]1111; CHECK-NEXT: vmov.u16 r2, q0[4]1112; CHECK-NEXT: eors r1, r21113; CHECK-NEXT: vmov.u16 r2, q0[2]1114; CHECK-NEXT: vmov.u16 r3, q0[0]1115; CHECK-NEXT: eors r2, r31116; CHECK-NEXT: eors r1, r21117; CHECK-NEXT: eors r0, r11118; CHECK-NEXT: bx lr1119entry:1120 %z = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %x)1121 %r = xor i8 %y, %z1122 ret i8 %r1123}1124 1125define arm_aapcs_vfpcc i8 @xor_v16i8_acc(<16 x i8> %x, i8 %y) {1126; CHECK-LABEL: xor_v16i8_acc:1127; CHECK: @ %bb.0: @ %entry1128; CHECK-NEXT: vrev16.8 q1, q01129; CHECK-NEXT: veor q0, q0, q11130; CHECK-NEXT: vrev32.8 q1, q01131; CHECK-NEXT: veor q0, q0, q11132; CHECK-NEXT: vmov.u8 r1, q0[12]1133; CHECK-NEXT: vmov.u8 r2, q0[8]1134; CHECK-NEXT: eors r1, r21135; CHECK-NEXT: vmov.u8 r2, q0[4]1136; CHECK-NEXT: vmov.u8 r3, q0[0]1137; CHECK-NEXT: eors r2, r31138; CHECK-NEXT: eors r1, r21139; CHECK-NEXT: eors r0, r11140; CHECK-NEXT: bx lr1141entry:1142 %z = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %x)1143 %r = xor i8 %y, %z1144 ret i8 %r1145}1146 1147define arm_aapcs_vfpcc i8 @xor_v32i8_acc(<32 x i8> %x, i8 %y) {1148; CHECK-LABEL: xor_v32i8_acc:1149; CHECK: @ %bb.0: @ %entry1150; CHECK-NEXT: veor q0, q0, q11151; CHECK-NEXT: vrev16.8 q1, q01152; CHECK-NEXT: veor q0, q0, q11153; CHECK-NEXT: vrev32.8 q1, q01154; CHECK-NEXT: veor q0, q0, q11155; CHECK-NEXT: vmov.u8 r1, q0[12]1156; CHECK-NEXT: vmov.u8 r2, q0[8]1157; CHECK-NEXT: eors r1, r21158; CHECK-NEXT: vmov.u8 r2, q0[4]1159; CHECK-NEXT: vmov.u8 r3, q0[0]1160; CHECK-NEXT: eors r2, r31161; CHECK-NEXT: eors r1, r21162; CHECK-NEXT: eors r0, r11163; CHECK-NEXT: bx lr1164entry:1165 %z = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %x)1166 %r = xor i8 %y, %z1167 ret i8 %r1168}1169 1170define arm_aapcs_vfpcc i64 @xor_v1i64_acc(<1 x i64> %x, i64 %y) {1171; CHECK-LABEL: xor_v1i64_acc:1172; CHECK: @ %bb.0: @ %entry1173; CHECK-NEXT: eors r0, r21174; CHECK-NEXT: eors r1, r31175; CHECK-NEXT: bx lr1176entry:1177 %z = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %x)1178 %r = xor i64 %y, %z1179 ret i64 %r1180}1181 1182define arm_aapcs_vfpcc i64 @xor_v2i64_acc(<2 x i64> %x, i64 %y) {1183; CHECK-LABEL: xor_v2i64_acc:1184; CHECK: @ %bb.0: @ %entry1185; CHECK-NEXT: .save {r7, lr}1186; CHECK-NEXT: push {r7, lr}1187; CHECK-NEXT: vmov r2, r12, d11188; CHECK-NEXT: vmov r3, lr, d01189; CHECK-NEXT: eors r2, r31190; CHECK-NEXT: eors r0, r21191; CHECK-NEXT: eor.w r2, lr, r121192; CHECK-NEXT: eors r1, r21193; CHECK-NEXT: pop {r7, pc}1194entry:1195 %z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %x)1196 %r = xor i64 %y, %z1197 ret i64 %r1198}1199 1200define arm_aapcs_vfpcc i64 @xor_v4i64_acc(<4 x i64> %x, i64 %y) {1201; CHECK-LABEL: xor_v4i64_acc:1202; CHECK: @ %bb.0: @ %entry1203; CHECK-NEXT: .save {r7, lr}1204; CHECK-NEXT: push {r7, lr}1205; CHECK-NEXT: veor q0, q0, q11206; CHECK-NEXT: vmov r2, r12, d11207; CHECK-NEXT: vmov r3, lr, d01208; CHECK-NEXT: eors r2, r31209; CHECK-NEXT: eors r0, r21210; CHECK-NEXT: eor.w r2, lr, r121211; CHECK-NEXT: eors r1, r21212; CHECK-NEXT: pop {r7, pc}1213entry:1214 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %x)1215 %r = xor i64 %y, %z1216 ret i64 %r1217}1218 1219declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)1220declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)1221declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)1222declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)1223declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)1224declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)1225declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)1226declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)1227declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)1228declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)1229declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)1230declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)1231declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)1232declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)1233declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)1234declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)1235declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)1236declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)1237declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)1238declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)1239declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)1240declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)1241declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)1242declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)1243declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)1244declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)1245declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)1246declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)1247declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)1248declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)1249declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)1250declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)1251declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)1252declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)1253declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)1254declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)1255