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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP4 5define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) {6; CHECK-LABEL: fmin_v2f32:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vminnm.f32 s0, s0, s19; CHECK-NEXT: bx lr10entry:11 %z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)12 ret float %z13}14 15define arm_aapcs_vfpcc float @fmin_v4f32(<4 x float> %x) {16; CHECK-FP-LABEL: fmin_v4f32:17; CHECK-FP: @ %bb.0: @ %entry18; CHECK-FP-NEXT: vminnm.f32 s2, s2, s319; CHECK-FP-NEXT: vminnm.f32 s0, s0, s120; CHECK-FP-NEXT: vminnm.f32 s0, s0, s221; CHECK-FP-NEXT: bx lr22;23; CHECK-NOFP-LABEL: fmin_v4f32:24; CHECK-NOFP: @ %bb.0: @ %entry25; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s126; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s227; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s328; CHECK-NOFP-NEXT: bx lr29entry:30 %z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)31 ret float %z32}33 34; FIXME fminnum (vector) -> fminnum (scalar) ?35define arm_aapcs_vfpcc float @fmin_v8f32(<8 x float> %x) {36; CHECK-FP-LABEL: fmin_v8f32:37; CHECK-FP: @ %bb.0: @ %entry38; CHECK-FP-NEXT: vminnm.f32 q0, q0, q139; CHECK-FP-NEXT: vminnm.f32 s2, s2, s340; CHECK-FP-NEXT: vminnm.f32 s0, s0, s141; CHECK-FP-NEXT: vminnm.f32 s0, s0, s242; CHECK-FP-NEXT: bx lr43;44; CHECK-NOFP-LABEL: fmin_v8f32:45; CHECK-NOFP: @ %bb.0: @ %entry46; CHECK-NOFP-NEXT: vminnm.f32 s8, s1, s547; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s448; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s849; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s650; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s251; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s752; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s253; CHECK-NOFP-NEXT: bx lr54entry:55 %z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)56 ret float %z57}58 59define arm_aapcs_vfpcc half @fmin_v4f16(<4 x half> %x) {60; CHECK-FP-LABEL: fmin_v4f16:61; CHECK-FP: @ %bb.0: @ %entry62; CHECK-FP-NEXT: vmovx.f16 s2, s163; CHECK-FP-NEXT: vmovx.f16 s4, s064; CHECK-FP-NEXT: vminnm.f16 s2, s1, s265; CHECK-FP-NEXT: vminnm.f16 s0, s0, s466; CHECK-FP-NEXT: vminnm.f16 s0, s0, s267; CHECK-FP-NEXT: bx lr68;69; CHECK-NOFP-LABEL: fmin_v4f16:70; CHECK-NOFP: @ %bb.0: @ %entry71; CHECK-NOFP-NEXT: vmovx.f16 s2, s072; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s273; CHECK-NOFP-NEXT: vmovx.f16 s2, s174; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s175; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s276; CHECK-NOFP-NEXT: bx lr77entry:78 %z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)79 ret half %z80}81 82define arm_aapcs_vfpcc half @fmin_v8f16(<8 x half> %x) {83; CHECK-FP-LABEL: fmin_v8f16:84; CHECK-FP: @ %bb.0: @ %entry85; CHECK-FP-NEXT: vrev32.16 q1, q086; CHECK-FP-NEXT: vminnm.f16 q0, q0, q187; CHECK-FP-NEXT: vminnm.f16 s2, s2, s388; CHECK-FP-NEXT: vminnm.f16 s0, s0, s189; CHECK-FP-NEXT: vminnm.f16 s0, s0, s290; CHECK-FP-NEXT: bx lr91;92; CHECK-NOFP-LABEL: fmin_v8f16:93; CHECK-NOFP: @ %bb.0: @ %entry94; CHECK-NOFP-NEXT: vmovx.f16 s4, s095; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s496; CHECK-NOFP-NEXT: vmovx.f16 s4, s197; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s198; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s499; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2100; CHECK-NOFP-NEXT: vmovx.f16 s2, s2101; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2102; CHECK-NOFP-NEXT: vmovx.f16 s2, s3103; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3104; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2105; CHECK-NOFP-NEXT: bx lr106entry:107 %z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)108 ret half %z109}110 111define arm_aapcs_vfpcc half @fmin_v16f16(<16 x half> %x) {112; CHECK-FP-LABEL: fmin_v16f16:113; CHECK-FP: @ %bb.0: @ %entry114; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1115; CHECK-FP-NEXT: vrev32.16 q1, q0116; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1117; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3118; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1119; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2120; CHECK-FP-NEXT: bx lr121;122; CHECK-NOFP-LABEL: fmin_v16f16:123; CHECK-NOFP: @ %bb.0: @ %entry124; CHECK-NOFP-NEXT: vmovx.f16 s10, s0125; CHECK-NOFP-NEXT: vmovx.f16 s8, s4126; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4127; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8128; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s8129; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5130; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4131; CHECK-NOFP-NEXT: vmovx.f16 s4, s5132; CHECK-NOFP-NEXT: vmovx.f16 s8, s1133; CHECK-NOFP-NEXT: vminnm.f16 s4, s8, s4134; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4135; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6136; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4137; CHECK-NOFP-NEXT: vmovx.f16 s4, s6138; CHECK-NOFP-NEXT: vmovx.f16 s2, s2139; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4140; CHECK-NOFP-NEXT: vmovx.f16 s4, s3141; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2142; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7143; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2144; CHECK-NOFP-NEXT: vmovx.f16 s2, s7145; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2146; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2147; CHECK-NOFP-NEXT: bx lr148entry:149 %z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)150 ret half %z151}152 153define arm_aapcs_vfpcc double @fmin_v1f64(<1 x double> %x) {154; CHECK-LABEL: fmin_v1f64:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: bx lr157entry:158 %z = call fast double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)159 ret double %z160}161 162define arm_aapcs_vfpcc double @fmin_v2f64(<2 x double> %x) {163; CHECK-LABEL: fmin_v2f64:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vminnm.f64 d0, d0, d1166; CHECK-NEXT: bx lr167entry:168 %z = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)169 ret double %z170}171 172define arm_aapcs_vfpcc double @fmin_v4f64(<4 x double> %x) {173; CHECK-LABEL: fmin_v4f64:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vcmp.f64 d3, d1176; CHECK-NEXT: vmrs APSR_nzcv, fpscr177; CHECK-NEXT: vcmp.f64 d2, d0178; CHECK-NEXT: vselgt.f64 d1, d1, d3179; CHECK-NEXT: vmrs APSR_nzcv, fpscr180; CHECK-NEXT: vselgt.f64 d0, d0, d2181; CHECK-NEXT: vminnm.f64 d0, d0, d1182; CHECK-NEXT: bx lr183entry:184 %z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)185 ret double %z186}187 188define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) {189; CHECK-LABEL: fmin_v2f32_nofast:190; CHECK: @ %bb.0: @ %entry191; CHECK-NEXT: vminnm.f32 s0, s0, s1192; CHECK-NEXT: bx lr193entry:194 %z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)195 ret float %z196}197 198define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) {199; CHECK-FP-LABEL: fmin_v4f32_nofast:200; CHECK-FP: @ %bb.0: @ %entry201; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3202; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1203; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2204; CHECK-FP-NEXT: bx lr205;206; CHECK-NOFP-LABEL: fmin_v4f32_nofast:207; CHECK-NOFP: @ %bb.0: @ %entry208; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1209; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2210; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3211; CHECK-NOFP-NEXT: bx lr212entry:213 %z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)214 ret float %z215}216 217define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) {218; CHECK-FP-LABEL: fmin_v8f32_nofast:219; CHECK-FP: @ %bb.0: @ %entry220; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1221; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3222; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1223; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2224; CHECK-FP-NEXT: bx lr225;226; CHECK-NOFP-LABEL: fmin_v8f32_nofast:227; CHECK-NOFP: @ %bb.0: @ %entry228; CHECK-NOFP-NEXT: vminnm.f32 s8, s1, s5229; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4230; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s8231; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6232; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2233; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s7234; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2235; CHECK-NOFP-NEXT: bx lr236entry:237 %z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)238 ret float %z239}240 241define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {242; CHECK-FP-LABEL: fmin_v4f16_nofast:243; CHECK-FP: @ %bb.0: @ %entry244; CHECK-FP-NEXT: vmovx.f16 s2, s1245; CHECK-FP-NEXT: vmovx.f16 s4, s0246; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2247; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4248; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2249; CHECK-FP-NEXT: bx lr250;251; CHECK-NOFP-LABEL: fmin_v4f16_nofast:252; CHECK-NOFP: @ %bb.0: @ %entry253; CHECK-NOFP-NEXT: vmovx.f16 s2, s0254; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2255; CHECK-NOFP-NEXT: vmovx.f16 s2, s1256; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1257; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2258; CHECK-NOFP-NEXT: bx lr259entry:260 %z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)261 ret half %z262}263 264define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) {265; CHECK-FP-LABEL: fmin_v8f16_nofast:266; CHECK-FP: @ %bb.0: @ %entry267; CHECK-FP-NEXT: vrev32.16 q1, q0268; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1269; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3270; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1271; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2272; CHECK-FP-NEXT: bx lr273;274; CHECK-NOFP-LABEL: fmin_v8f16_nofast:275; CHECK-NOFP: @ %bb.0: @ %entry276; CHECK-NOFP-NEXT: vmovx.f16 s4, s0277; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4278; CHECK-NOFP-NEXT: vmovx.f16 s4, s1279; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1280; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4281; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2282; CHECK-NOFP-NEXT: vmovx.f16 s2, s2283; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2284; CHECK-NOFP-NEXT: vmovx.f16 s2, s3285; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3286; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2287; CHECK-NOFP-NEXT: bx lr288entry:289 %z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)290 ret half %z291}292 293define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) {294; CHECK-FP-LABEL: fmin_v16f16_nofast:295; CHECK-FP: @ %bb.0: @ %entry296; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1297; CHECK-FP-NEXT: vrev32.16 q1, q0298; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1299; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3300; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1301; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2302; CHECK-FP-NEXT: bx lr303;304; CHECK-NOFP-LABEL: fmin_v16f16_nofast:305; CHECK-NOFP: @ %bb.0: @ %entry306; CHECK-NOFP-NEXT: vmovx.f16 s10, s0307; CHECK-NOFP-NEXT: vmovx.f16 s8, s4308; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4309; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8310; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s8311; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5312; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4313; CHECK-NOFP-NEXT: vmovx.f16 s4, s5314; CHECK-NOFP-NEXT: vmovx.f16 s8, s1315; CHECK-NOFP-NEXT: vminnm.f16 s4, s8, s4316; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4317; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6318; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4319; CHECK-NOFP-NEXT: vmovx.f16 s4, s6320; CHECK-NOFP-NEXT: vmovx.f16 s2, s2321; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4322; CHECK-NOFP-NEXT: vmovx.f16 s4, s3323; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2324; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7325; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2326; CHECK-NOFP-NEXT: vmovx.f16 s2, s7327; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2328; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2329; CHECK-NOFP-NEXT: bx lr330entry:331 %z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)332 ret half %z333}334 335define arm_aapcs_vfpcc double @fmin_v1f64_nofast(<1 x double> %x) {336; CHECK-LABEL: fmin_v1f64_nofast:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: bx lr339entry:340 %z = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)341 ret double %z342}343 344define arm_aapcs_vfpcc double @fmin_v2f64_nofast(<2 x double> %x) {345; CHECK-LABEL: fmin_v2f64_nofast:346; CHECK: @ %bb.0: @ %entry347; CHECK-NEXT: vminnm.f64 d0, d0, d1348; CHECK-NEXT: bx lr349entry:350 %z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)351 ret double %z352}353 354define arm_aapcs_vfpcc double @fmin_v4f64_nofast(<4 x double> %x) {355; CHECK-LABEL: fmin_v4f64_nofast:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vminnm.f64 d1, d1, d3358; CHECK-NEXT: vminnm.f64 d0, d0, d2359; CHECK-NEXT: vminnm.f64 d0, d0, d1360; CHECK-NEXT: bx lr361entry:362 %z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)363 ret double %z364}365 366define arm_aapcs_vfpcc float @fmin_v2f32_acc(<2 x float> %x, float %y) {367; CHECK-LABEL: fmin_v2f32_acc:368; CHECK: @ %bb.0: @ %entry369; CHECK-NEXT: vminnm.f32 s0, s0, s1370; CHECK-NEXT: vminnm.f32 s0, s4, s0371; CHECK-NEXT: bx lr372entry:373 %z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)374 %c = fcmp fast olt float %y, %z375 %r = select i1 %c, float %y, float %z376 ret float %r377}378 379define arm_aapcs_vfpcc float @fmin_v4f32_acc(<4 x float> %x, float %y) {380; CHECK-FP-LABEL: fmin_v4f32_acc:381; CHECK-FP: @ %bb.0: @ %entry382; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3383; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1384; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2385; CHECK-FP-NEXT: vminnm.f32 s0, s4, s0386; CHECK-FP-NEXT: bx lr387;388; CHECK-NOFP-LABEL: fmin_v4f32_acc:389; CHECK-NOFP: @ %bb.0: @ %entry390; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1391; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2392; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3393; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s0394; CHECK-NOFP-NEXT: bx lr395entry:396 %z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)397 %c = fcmp fast olt float %y, %z398 %r = select i1 %c, float %y, float %z399 ret float %r400}401 402define arm_aapcs_vfpcc float @fmin_v8f32_acc(<8 x float> %x, float %y) {403; CHECK-FP-LABEL: fmin_v8f32_acc:404; CHECK-FP: @ %bb.0: @ %entry405; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1406; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3407; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1408; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2409; CHECK-FP-NEXT: vminnm.f32 s0, s8, s0410; CHECK-FP-NEXT: bx lr411;412; CHECK-NOFP-LABEL: fmin_v8f32_acc:413; CHECK-NOFP: @ %bb.0: @ %entry414; CHECK-NOFP-NEXT: vminnm.f32 s10, s1, s5415; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4416; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s10417; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6418; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2419; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s7420; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2421; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0422; CHECK-NOFP-NEXT: bx lr423entry:424 %z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)425 %c = fcmp fast olt float %y, %z426 %r = select i1 %c, float %y, float %z427 ret float %r428}429 430define arm_aapcs_vfpcc half @fmin_v4f16_acc(<4 x half> %x, half %y) {431; CHECK-FP-LABEL: fmin_v4f16_acc:432; CHECK-FP: @ %bb.0: @ %entry433; CHECK-FP-NEXT: vmovx.f16 s2, s1434; CHECK-FP-NEXT: vmovx.f16 s6, s0435; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2436; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6437; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2438; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0439; CHECK-FP-NEXT: bx lr440;441; CHECK-NOFP-LABEL: fmin_v4f16_acc:442; CHECK-NOFP: @ %bb.0: @ %entry443; CHECK-NOFP-NEXT: vmovx.f16 s2, s0444; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2445; CHECK-NOFP-NEXT: vmovx.f16 s2, s1446; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1447; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2448; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0449; CHECK-NOFP-NEXT: bx lr450entry:451 %z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)452 %c = fcmp fast olt half %y, %z453 %r = select i1 %c, half %y, half %z454 ret half %r455}456 457define arm_aapcs_vfpcc half @fmin_v2f16_acc(<2 x half> %x, half %y) {458; CHECK-LABEL: fmin_v2f16_acc:459; CHECK: @ %bb.0: @ %entry460; CHECK-NEXT: vmovx.f16 s2, s0461; CHECK-NEXT: vminnm.f16 s0, s0, s2462; CHECK-NEXT: vminnm.f16 s0, s4, s0463; CHECK-NEXT: bx lr464entry:465 %z = call fast half @llvm.vector.reduce.fmin.v2f16(<2 x half> %x)466 %c = fcmp fast olt half %y, %z467 %r = select i1 %c, half %y, half %z468 ret half %r469}470 471define arm_aapcs_vfpcc half @fmin_v8f16_acc(<8 x half> %x, half %y) {472; CHECK-FP-LABEL: fmin_v8f16_acc:473; CHECK-FP: @ %bb.0: @ %entry474; CHECK-FP-NEXT: vrev32.16 q2, q0475; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2476; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3477; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1478; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2479; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0480; CHECK-FP-NEXT: bx lr481;482; CHECK-NOFP-LABEL: fmin_v8f16_acc:483; CHECK-NOFP: @ %bb.0: @ %entry484; CHECK-NOFP-NEXT: vmovx.f16 s6, s0485; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6486; CHECK-NOFP-NEXT: vmovx.f16 s6, s1487; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1488; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6489; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2490; CHECK-NOFP-NEXT: vmovx.f16 s2, s2491; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2492; CHECK-NOFP-NEXT: vmovx.f16 s2, s3493; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3494; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2495; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0496; CHECK-NOFP-NEXT: bx lr497entry:498 %z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)499 %c = fcmp fast olt half %y, %z500 %r = select i1 %c, half %y, half %z501 ret half %r502}503 504define arm_aapcs_vfpcc half @fmin_v16f16_acc(<16 x half> %x, half %y) {505; CHECK-FP-LABEL: fmin_v16f16_acc:506; CHECK-FP: @ %bb.0: @ %entry507; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1508; CHECK-FP-NEXT: vrev32.16 q1, q0509; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1510; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3511; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1512; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2513; CHECK-FP-NEXT: vminnm.f16 s0, s8, s0514; CHECK-FP-NEXT: bx lr515;516; CHECK-NOFP-LABEL: fmin_v16f16_acc:517; CHECK-NOFP: @ %bb.0: @ %entry518; CHECK-NOFP-NEXT: vmovx.f16 s12, s0519; CHECK-NOFP-NEXT: vmovx.f16 s10, s4520; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4521; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10522; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s10523; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5524; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4525; CHECK-NOFP-NEXT: vmovx.f16 s4, s5526; CHECK-NOFP-NEXT: vmovx.f16 s10, s1527; CHECK-NOFP-NEXT: vminnm.f16 s4, s10, s4528; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4529; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6530; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4531; CHECK-NOFP-NEXT: vmovx.f16 s4, s6532; CHECK-NOFP-NEXT: vmovx.f16 s2, s2533; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4534; CHECK-NOFP-NEXT: vmovx.f16 s4, s3535; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2536; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7537; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2538; CHECK-NOFP-NEXT: vmovx.f16 s2, s7539; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2540; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2541; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0542; CHECK-NOFP-NEXT: bx lr543entry:544 %z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)545 %c = fcmp fast olt half %y, %z546 %r = select i1 %c, half %y, half %z547 ret half %r548}549 550define arm_aapcs_vfpcc double @fmin_v1f64_acc(<1 x double> %x, double %y) {551; CHECK-LABEL: fmin_v1f64_acc:552; CHECK: @ %bb.0: @ %entry553; CHECK-NEXT: vminnm.f64 d0, d1, d0554; CHECK-NEXT: bx lr555entry:556 %z = call fast double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)557 %c = fcmp fast olt double %y, %z558 %r = select i1 %c, double %y, double %z559 ret double %r560}561 562define arm_aapcs_vfpcc double @fmin_v2f64_acc(<2 x double> %x, double %y) {563; CHECK-LABEL: fmin_v2f64_acc:564; CHECK: @ %bb.0: @ %entry565; CHECK-NEXT: vminnm.f64 d0, d0, d1566; CHECK-NEXT: vminnm.f64 d0, d2, d0567; CHECK-NEXT: bx lr568entry:569 %z = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)570 %c = fcmp fast olt double %y, %z571 %r = select i1 %c, double %y, double %z572 ret double %r573}574 575define arm_aapcs_vfpcc double @fmin_v4f64_acc(<4 x double> %x, double %y) {576; CHECK-LABEL: fmin_v4f64_acc:577; CHECK: @ %bb.0: @ %entry578; CHECK-NEXT: vcmp.f64 d3, d1579; CHECK-NEXT: vmrs APSR_nzcv, fpscr580; CHECK-NEXT: vcmp.f64 d2, d0581; CHECK-NEXT: vselgt.f64 d1, d1, d3582; CHECK-NEXT: vmrs APSR_nzcv, fpscr583; CHECK-NEXT: vselgt.f64 d0, d0, d2584; CHECK-NEXT: vminnm.f64 d0, d0, d1585; CHECK-NEXT: vminnm.f64 d0, d4, d0586; CHECK-NEXT: bx lr587entry:588 %z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)589 %c = fcmp fast olt double %y, %z590 %r = select i1 %c, double %y, double %z591 ret double %r592}593 594define arm_aapcs_vfpcc float @fmin_v2f32_acc_nofast(<2 x float> %x, float %y) {595; CHECK-LABEL: fmin_v2f32_acc_nofast:596; CHECK: @ %bb.0: @ %entry597; CHECK-NEXT: vminnm.f32 s0, s0, s1598; CHECK-NEXT: vcmp.f32 s0, s4599; CHECK-NEXT: vmrs APSR_nzcv, fpscr600; CHECK-NEXT: vselgt.f32 s0, s4, s0601; CHECK-NEXT: bx lr602entry:603 %z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)604 %c = fcmp olt float %y, %z605 %r = select i1 %c, float %y, float %z606 ret float %r607}608 609define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) {610; CHECK-FP-LABEL: fmin_v4f32_acc_nofast:611; CHECK-FP: @ %bb.0: @ %entry612; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3613; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1614; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2615; CHECK-FP-NEXT: vcmp.f32 s0, s4616; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr617; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0618; CHECK-FP-NEXT: bx lr619;620; CHECK-NOFP-LABEL: fmin_v4f32_acc_nofast:621; CHECK-NOFP: @ %bb.0: @ %entry622; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1623; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2624; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3625; CHECK-NOFP-NEXT: vcmp.f32 s0, s4626; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr627; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0628; CHECK-NOFP-NEXT: bx lr629entry:630 %z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)631 %c = fcmp olt float %y, %z632 %r = select i1 %c, float %y, float %z633 ret float %r634}635 636define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) {637; CHECK-FP-LABEL: fmin_v8f32_acc_nofast:638; CHECK-FP: @ %bb.0: @ %entry639; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1640; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3641; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1642; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2643; CHECK-FP-NEXT: vcmp.f32 s0, s8644; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr645; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0646; CHECK-FP-NEXT: bx lr647;648; CHECK-NOFP-LABEL: fmin_v8f32_acc_nofast:649; CHECK-NOFP: @ %bb.0: @ %entry650; CHECK-NOFP-NEXT: vminnm.f32 s10, s1, s5651; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4652; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s10653; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6654; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2655; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s7656; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2657; CHECK-NOFP-NEXT: vcmp.f32 s0, s8658; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr659; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0660; CHECK-NOFP-NEXT: bx lr661entry:662 %z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)663 %c = fcmp olt float %y, %z664 %r = select i1 %c, float %y, float %z665 ret float %r666}667 668define arm_aapcs_vfpcc half @fmin_v4f16_acc_nofast(<4 x half> %x, half %y) {669; CHECK-FP-LABEL: fmin_v4f16_acc_nofast:670; CHECK-FP: @ %bb.0: @ %entry671; CHECK-FP-NEXT: vmovx.f16 s2, s1672; CHECK-FP-NEXT: vmovx.f16 s6, s0673; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2674; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6675; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2676; CHECK-FP-NEXT: vcmp.f16 s0, s4677; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr678; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0679; CHECK-FP-NEXT: bx lr680;681; CHECK-NOFP-LABEL: fmin_v4f16_acc_nofast:682; CHECK-NOFP: @ %bb.0: @ %entry683; CHECK-NOFP-NEXT: vmovx.f16 s2, s0684; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2685; CHECK-NOFP-NEXT: vmovx.f16 s2, s1686; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1687; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2688; CHECK-NOFP-NEXT: vcmp.f16 s0, s4689; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr690; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0691; CHECK-NOFP-NEXT: bx lr692entry:693 %z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)694 %c = fcmp olt half %y, %z695 %r = select i1 %c, half %y, half %z696 ret half %r697}698 699define arm_aapcs_vfpcc half @fmin_v8f16_acc_nofast(<8 x half> %x, half %y) {700; CHECK-FP-LABEL: fmin_v8f16_acc_nofast:701; CHECK-FP: @ %bb.0: @ %entry702; CHECK-FP-NEXT: vrev32.16 q2, q0703; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2704; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3705; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1706; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2707; CHECK-FP-NEXT: vcmp.f16 s0, s4708; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr709; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0710; CHECK-FP-NEXT: bx lr711;712; CHECK-NOFP-LABEL: fmin_v8f16_acc_nofast:713; CHECK-NOFP: @ %bb.0: @ %entry714; CHECK-NOFP-NEXT: vmovx.f16 s6, s0715; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6716; CHECK-NOFP-NEXT: vmovx.f16 s6, s1717; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1718; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6719; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2720; CHECK-NOFP-NEXT: vmovx.f16 s2, s2721; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2722; CHECK-NOFP-NEXT: vmovx.f16 s2, s3723; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3724; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2725; CHECK-NOFP-NEXT: vcmp.f16 s0, s4726; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr727; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0728; CHECK-NOFP-NEXT: bx lr729entry:730 %z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)731 %c = fcmp olt half %y, %z732 %r = select i1 %c, half %y, half %z733 ret half %r734}735 736define arm_aapcs_vfpcc half @fmin_v16f16_acc_nofast(<16 x half> %x, half %y) {737; CHECK-FP-LABEL: fmin_v16f16_acc_nofast:738; CHECK-FP: @ %bb.0: @ %entry739; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1740; CHECK-FP-NEXT: vrev32.16 q1, q0741; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1742; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3743; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1744; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2745; CHECK-FP-NEXT: vcmp.f16 s0, s8746; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr747; CHECK-FP-NEXT: vselgt.f16 s0, s8, s0748; CHECK-FP-NEXT: bx lr749;750; CHECK-NOFP-LABEL: fmin_v16f16_acc_nofast:751; CHECK-NOFP: @ %bb.0: @ %entry752; CHECK-NOFP-NEXT: vmovx.f16 s12, s0753; CHECK-NOFP-NEXT: vmovx.f16 s10, s4754; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4755; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10756; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s10757; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5758; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4759; CHECK-NOFP-NEXT: vmovx.f16 s4, s5760; CHECK-NOFP-NEXT: vmovx.f16 s10, s1761; CHECK-NOFP-NEXT: vminnm.f16 s4, s10, s4762; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4763; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6764; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4765; CHECK-NOFP-NEXT: vmovx.f16 s4, s6766; CHECK-NOFP-NEXT: vmovx.f16 s2, s2767; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4768; CHECK-NOFP-NEXT: vmovx.f16 s4, s3769; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2770; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7771; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2772; CHECK-NOFP-NEXT: vmovx.f16 s2, s7773; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2774; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2775; CHECK-NOFP-NEXT: vcmp.f16 s0, s8776; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr777; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s0778; CHECK-NOFP-NEXT: bx lr779entry:780 %z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)781 %c = fcmp olt half %y, %z782 %r = select i1 %c, half %y, half %z783 ret half %r784}785 786define arm_aapcs_vfpcc double @fmin_v1f64_acc_nofast(<1 x double> %x, double %y) {787; CHECK-LABEL: fmin_v1f64_acc_nofast:788; CHECK: @ %bb.0: @ %entry789; CHECK-NEXT: vcmp.f64 d0, d1790; CHECK-NEXT: vmrs APSR_nzcv, fpscr791; CHECK-NEXT: vselgt.f64 d0, d1, d0792; CHECK-NEXT: bx lr793entry:794 %z = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)795 %c = fcmp olt double %y, %z796 %r = select i1 %c, double %y, double %z797 ret double %r798}799 800define arm_aapcs_vfpcc double @fmin_v2f64_acc_nofast(<2 x double> %x, double %y) {801; CHECK-LABEL: fmin_v2f64_acc_nofast:802; CHECK: @ %bb.0: @ %entry803; CHECK-NEXT: vminnm.f64 d0, d0, d1804; CHECK-NEXT: vcmp.f64 d0, d2805; CHECK-NEXT: vmrs APSR_nzcv, fpscr806; CHECK-NEXT: vselgt.f64 d0, d2, d0807; CHECK-NEXT: bx lr808entry:809 %z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)810 %c = fcmp olt double %y, %z811 %r = select i1 %c, double %y, double %z812 ret double %r813}814 815define arm_aapcs_vfpcc double @fmin_v4f64_acc_nofast(<4 x double> %x, double %y) {816; CHECK-LABEL: fmin_v4f64_acc_nofast:817; CHECK: @ %bb.0: @ %entry818; CHECK-NEXT: vminnm.f64 d1, d1, d3819; CHECK-NEXT: vminnm.f64 d0, d0, d2820; CHECK-NEXT: vminnm.f64 d0, d0, d1821; CHECK-NEXT: vcmp.f64 d0, d4822; CHECK-NEXT: vmrs APSR_nzcv, fpscr823; CHECK-NEXT: vselgt.f64 d0, d4, d0824; CHECK-NEXT: bx lr825entry:826 %z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)827 %c = fcmp olt double %y, %z828 %r = select i1 %c, double %y, double %z829 ret double %r830}831 832define arm_aapcs_vfpcc float @fmax_v2f32(<2 x float> %x) {833; CHECK-LABEL: fmax_v2f32:834; CHECK: @ %bb.0: @ %entry835; CHECK-NEXT: vmaxnm.f32 s0, s0, s1836; CHECK-NEXT: bx lr837entry:838 %z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)839 ret float %z840}841 842define arm_aapcs_vfpcc float @fmax_v4f32(<4 x float> %x) {843; CHECK-FP-LABEL: fmax_v4f32:844; CHECK-FP: @ %bb.0: @ %entry845; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3846; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1847; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2848; CHECK-FP-NEXT: bx lr849;850; CHECK-NOFP-LABEL: fmax_v4f32:851; CHECK-NOFP: @ %bb.0: @ %entry852; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s1853; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2854; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s3855; CHECK-NOFP-NEXT: bx lr856entry:857 %z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)858 ret float %z859}860 861define arm_aapcs_vfpcc float @fmax_v8f32(<8 x float> %x) {862; CHECK-FP-LABEL: fmax_v8f32:863; CHECK-FP: @ %bb.0: @ %entry864; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1865; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3866; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1867; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2868; CHECK-FP-NEXT: bx lr869;870; CHECK-NOFP-LABEL: fmax_v8f32:871; CHECK-NOFP: @ %bb.0: @ %entry872; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s1, s5873; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s4874; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s8875; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s6876; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2877; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s7878; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2879; CHECK-NOFP-NEXT: bx lr880entry:881 %z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)882 ret float %z883}884 885define arm_aapcs_vfpcc half @fmax_v4f16(<4 x half> %x) {886; CHECK-FP-LABEL: fmax_v4f16:887; CHECK-FP: @ %bb.0: @ %entry888; CHECK-FP-NEXT: vmovx.f16 s2, s1889; CHECK-FP-NEXT: vmovx.f16 s4, s0890; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s2891; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4892; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2893; CHECK-FP-NEXT: bx lr894;895; CHECK-NOFP-LABEL: fmax_v4f16:896; CHECK-NOFP: @ %bb.0: @ %entry897; CHECK-NOFP-NEXT: vmovx.f16 s2, s0898; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2899; CHECK-NOFP-NEXT: vmovx.f16 s2, s1900; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1901; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2902; CHECK-NOFP-NEXT: bx lr903entry:904 %z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)905 ret half %z906}907 908define arm_aapcs_vfpcc half @fmax_v8f16(<8 x half> %x) {909; CHECK-FP-LABEL: fmax_v8f16:910; CHECK-FP: @ %bb.0: @ %entry911; CHECK-FP-NEXT: vrev32.16 q1, q0912; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1913; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3914; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1915; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2916; CHECK-FP-NEXT: bx lr917;918; CHECK-NOFP-LABEL: fmax_v8f16:919; CHECK-NOFP: @ %bb.0: @ %entry920; CHECK-NOFP-NEXT: vmovx.f16 s4, s0921; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4922; CHECK-NOFP-NEXT: vmovx.f16 s4, s1923; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1924; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4925; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2926; CHECK-NOFP-NEXT: vmovx.f16 s2, s2927; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2928; CHECK-NOFP-NEXT: vmovx.f16 s2, s3929; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s3930; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2931; CHECK-NOFP-NEXT: bx lr932entry:933 %z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)934 ret half %z935}936 937define arm_aapcs_vfpcc half @fmax_v16f16(<16 x half> %x) {938; CHECK-FP-LABEL: fmax_v16f16:939; CHECK-FP: @ %bb.0: @ %entry940; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1941; CHECK-FP-NEXT: vrev32.16 q1, q0942; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1943; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3944; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1945; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2946; CHECK-FP-NEXT: bx lr947;948; CHECK-NOFP-LABEL: fmax_v16f16:949; CHECK-NOFP: @ %bb.0: @ %entry950; CHECK-NOFP-NEXT: vmovx.f16 s10, s0951; CHECK-NOFP-NEXT: vmovx.f16 s8, s4952; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4953; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s8954; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s8955; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s5956; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4957; CHECK-NOFP-NEXT: vmovx.f16 s4, s5958; CHECK-NOFP-NEXT: vmovx.f16 s8, s1959; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s8, s4960; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4961; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s6962; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4963; CHECK-NOFP-NEXT: vmovx.f16 s4, s6964; CHECK-NOFP-NEXT: vmovx.f16 s2, s2965; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s4966; CHECK-NOFP-NEXT: vmovx.f16 s4, s3967; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2968; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s7969; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2970; CHECK-NOFP-NEXT: vmovx.f16 s2, s7971; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s2972; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2973; CHECK-NOFP-NEXT: bx lr974entry:975 %z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)976 ret half %z977}978 979define arm_aapcs_vfpcc double @fmax_v1f64(<1 x double> %x) {980; CHECK-LABEL: fmax_v1f64:981; CHECK: @ %bb.0: @ %entry982; CHECK-NEXT: bx lr983entry:984 %z = call fast double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)985 ret double %z986}987 988define arm_aapcs_vfpcc double @fmax_v2f64(<2 x double> %x) {989; CHECK-LABEL: fmax_v2f64:990; CHECK: @ %bb.0: @ %entry991; CHECK-NEXT: vmaxnm.f64 d0, d0, d1992; CHECK-NEXT: bx lr993entry:994 %z = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)995 ret double %z996}997 998define arm_aapcs_vfpcc double @fmax_v4f64(<4 x double> %x) {999; CHECK-LABEL: fmax_v4f64:1000; CHECK: @ %bb.0: @ %entry1001; CHECK-NEXT: vcmp.f64 d1, d31002; CHECK-NEXT: vmrs APSR_nzcv, fpscr1003; CHECK-NEXT: vcmp.f64 d0, d21004; CHECK-NEXT: vselgt.f64 d1, d1, d31005; CHECK-NEXT: vmrs APSR_nzcv, fpscr1006; CHECK-NEXT: vselgt.f64 d0, d0, d21007; CHECK-NEXT: vmaxnm.f64 d0, d0, d11008; CHECK-NEXT: bx lr1009entry:1010 %z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)1011 ret double %z1012}1013 1014define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) {1015; CHECK-LABEL: fmax_v2f32_nofast:1016; CHECK: @ %bb.0: @ %entry1017; CHECK-NEXT: vmaxnm.f32 s0, s0, s11018; CHECK-NEXT: bx lr1019entry:1020 %z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)1021 ret float %z1022}1023 1024define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) {1025; CHECK-FP-LABEL: fmax_v4f32_nofast:1026; CHECK-FP: @ %bb.0: @ %entry1027; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31028; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11029; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21030; CHECK-FP-NEXT: bx lr1031;1032; CHECK-NOFP-LABEL: fmax_v4f32_nofast:1033; CHECK-NOFP: @ %bb.0: @ %entry1034; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s11035; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21036; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s31037; CHECK-NOFP-NEXT: bx lr1038entry:1039 %z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)1040 ret float %z1041}1042 1043define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) {1044; CHECK-FP-LABEL: fmax_v8f32_nofast:1045; CHECK-FP: @ %bb.0: @ %entry1046; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q11047; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31048; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11049; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21050; CHECK-FP-NEXT: bx lr1051;1052; CHECK-NOFP-LABEL: fmax_v8f32_nofast:1053; CHECK-NOFP: @ %bb.0: @ %entry1054; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s1, s51055; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s41056; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s81057; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s61058; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21059; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s71060; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21061; CHECK-NOFP-NEXT: bx lr1062entry:1063 %z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)1064 ret float %z1065}1066 1067define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) {1068; CHECK-FP-LABEL: fmax_v4f16_nofast:1069; CHECK-FP: @ %bb.0: @ %entry1070; CHECK-FP-NEXT: vmovx.f16 s2, s11071; CHECK-FP-NEXT: vmovx.f16 s4, s01072; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s21073; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s41074; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21075; CHECK-FP-NEXT: bx lr1076;1077; CHECK-NOFP-LABEL: fmax_v4f16_nofast:1078; CHECK-NOFP: @ %bb.0: @ %entry1079; CHECK-NOFP-NEXT: vmovx.f16 s2, s01080; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21081; CHECK-NOFP-NEXT: vmovx.f16 s2, s11082; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11083; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21084; CHECK-NOFP-NEXT: bx lr1085entry:1086 %z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)1087 ret half %z1088}1089 1090define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) {1091; CHECK-FP-LABEL: fmax_v8f16_nofast:1092; CHECK-FP: @ %bb.0: @ %entry1093; CHECK-FP-NEXT: vrev32.16 q1, q01094; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11095; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31096; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11097; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21098; CHECK-FP-NEXT: bx lr1099;1100; CHECK-NOFP-LABEL: fmax_v8f16_nofast:1101; CHECK-NOFP: @ %bb.0: @ %entry1102; CHECK-NOFP-NEXT: vmovx.f16 s4, s01103; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41104; CHECK-NOFP-NEXT: vmovx.f16 s4, s11105; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11106; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41107; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21108; CHECK-NOFP-NEXT: vmovx.f16 s2, s21109; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21110; CHECK-NOFP-NEXT: vmovx.f16 s2, s31111; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s31112; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21113; CHECK-NOFP-NEXT: bx lr1114entry:1115 %z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)1116 ret half %z1117}1118 1119define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) {1120; CHECK-FP-LABEL: fmax_v16f16_nofast:1121; CHECK-FP: @ %bb.0: @ %entry1122; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11123; CHECK-FP-NEXT: vrev32.16 q1, q01124; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11125; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31126; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11127; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21128; CHECK-FP-NEXT: bx lr1129;1130; CHECK-NOFP-LABEL: fmax_v16f16_nofast:1131; CHECK-NOFP: @ %bb.0: @ %entry1132; CHECK-NOFP-NEXT: vmovx.f16 s10, s01133; CHECK-NOFP-NEXT: vmovx.f16 s8, s41134; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41135; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s81136; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s81137; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s51138; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41139; CHECK-NOFP-NEXT: vmovx.f16 s4, s51140; CHECK-NOFP-NEXT: vmovx.f16 s8, s11141; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s8, s41142; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41143; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s61144; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41145; CHECK-NOFP-NEXT: vmovx.f16 s4, s61146; CHECK-NOFP-NEXT: vmovx.f16 s2, s21147; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s41148; CHECK-NOFP-NEXT: vmovx.f16 s4, s31149; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21150; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s71151; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21152; CHECK-NOFP-NEXT: vmovx.f16 s2, s71153; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s21154; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21155; CHECK-NOFP-NEXT: bx lr1156entry:1157 %z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)1158 ret half %z1159}1160 1161define arm_aapcs_vfpcc double @fmax_v1f64_nofast(<1 x double> %x) {1162; CHECK-LABEL: fmax_v1f64_nofast:1163; CHECK: @ %bb.0: @ %entry1164; CHECK-NEXT: bx lr1165entry:1166 %z = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)1167 ret double %z1168}1169 1170define arm_aapcs_vfpcc double @fmax_v2f64_nofast(<2 x double> %x) {1171; CHECK-LABEL: fmax_v2f64_nofast:1172; CHECK: @ %bb.0: @ %entry1173; CHECK-NEXT: vmaxnm.f64 d0, d0, d11174; CHECK-NEXT: bx lr1175entry:1176 %z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)1177 ret double %z1178}1179 1180define arm_aapcs_vfpcc double @fmax_v4f64_nofast(<4 x double> %x) {1181; CHECK-LABEL: fmax_v4f64_nofast:1182; CHECK: @ %bb.0: @ %entry1183; CHECK-NEXT: vmaxnm.f64 d1, d1, d31184; CHECK-NEXT: vmaxnm.f64 d0, d0, d21185; CHECK-NEXT: vmaxnm.f64 d0, d0, d11186; CHECK-NEXT: bx lr1187entry:1188 %z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)1189 ret double %z1190}1191 1192define arm_aapcs_vfpcc float @fmax_v2f32_acc(<2 x float> %x, float %y) {1193; CHECK-LABEL: fmax_v2f32_acc:1194; CHECK: @ %bb.0: @ %entry1195; CHECK-NEXT: vmaxnm.f32 s0, s0, s11196; CHECK-NEXT: vmaxnm.f32 s0, s4, s01197; CHECK-NEXT: bx lr1198entry:1199 %z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)1200 %c = fcmp fast ogt float %y, %z1201 %r = select i1 %c, float %y, float %z1202 ret float %r1203}1204 1205define arm_aapcs_vfpcc float @fmax_v4f32_acc(<4 x float> %x, float %y) {1206; CHECK-FP-LABEL: fmax_v4f32_acc:1207; CHECK-FP: @ %bb.0: @ %entry1208; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31209; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11210; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21211; CHECK-FP-NEXT: vmaxnm.f32 s0, s4, s01212; CHECK-FP-NEXT: bx lr1213;1214; CHECK-NOFP-LABEL: fmax_v4f32_acc:1215; CHECK-NOFP: @ %bb.0: @ %entry1216; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s11217; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21218; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s31219; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s01220; CHECK-NOFP-NEXT: bx lr1221entry:1222 %z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)1223 %c = fcmp fast ogt float %y, %z1224 %r = select i1 %c, float %y, float %z1225 ret float %r1226}1227 1228define arm_aapcs_vfpcc float @fmax_v8f32_acc(<8 x float> %x, float %y) {1229; CHECK-FP-LABEL: fmax_v8f32_acc:1230; CHECK-FP: @ %bb.0: @ %entry1231; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q11232; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31233; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11234; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21235; CHECK-FP-NEXT: vmaxnm.f32 s0, s8, s01236; CHECK-FP-NEXT: bx lr1237;1238; CHECK-NOFP-LABEL: fmax_v8f32_acc:1239; CHECK-NOFP: @ %bb.0: @ %entry1240; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s1, s51241; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s41242; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s101243; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s61244; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21245; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s71246; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21247; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s01248; CHECK-NOFP-NEXT: bx lr1249entry:1250 %z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)1251 %c = fcmp fast ogt float %y, %z1252 %r = select i1 %c, float %y, float %z1253 ret float %r1254}1255 1256define arm_aapcs_vfpcc half @fmax_v2f16_acc(<2 x half> %x, half %y) {1257; CHECK-LABEL: fmax_v2f16_acc:1258; CHECK: @ %bb.0: @ %entry1259; CHECK-NEXT: vmovx.f16 s2, s01260; CHECK-NEXT: vmaxnm.f16 s0, s0, s21261; CHECK-NEXT: vmaxnm.f16 s0, s4, s01262; CHECK-NEXT: bx lr1263entry:1264 %z = call fast half @llvm.vector.reduce.fmax.v2f16(<2 x half> %x)1265 %c = fcmp fast ogt half %y, %z1266 %r = select i1 %c, half %y, half %z1267 ret half %r1268}1269 1270define arm_aapcs_vfpcc half @fmax_v4f16_acc(<4 x half> %x, half %y) {1271; CHECK-FP-LABEL: fmax_v4f16_acc:1272; CHECK-FP: @ %bb.0: @ %entry1273; CHECK-FP-NEXT: vmovx.f16 s2, s11274; CHECK-FP-NEXT: vmovx.f16 s6, s01275; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s21276; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s61277; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21278; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s01279; CHECK-FP-NEXT: bx lr1280;1281; CHECK-NOFP-LABEL: fmax_v4f16_acc:1282; CHECK-NOFP: @ %bb.0: @ %entry1283; CHECK-NOFP-NEXT: vmovx.f16 s2, s01284; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21285; CHECK-NOFP-NEXT: vmovx.f16 s2, s11286; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11287; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21288; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s01289; CHECK-NOFP-NEXT: bx lr1290entry:1291 %z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)1292 %c = fcmp fast ogt half %y, %z1293 %r = select i1 %c, half %y, half %z1294 ret half %r1295}1296 1297define arm_aapcs_vfpcc half @fmax_v8f16_acc(<8 x half> %x, half %y) {1298; CHECK-FP-LABEL: fmax_v8f16_acc:1299; CHECK-FP: @ %bb.0: @ %entry1300; CHECK-FP-NEXT: vrev32.16 q2, q01301; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q21302; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31303; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11304; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21305; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s01306; CHECK-FP-NEXT: bx lr1307;1308; CHECK-NOFP-LABEL: fmax_v8f16_acc:1309; CHECK-NOFP: @ %bb.0: @ %entry1310; CHECK-NOFP-NEXT: vmovx.f16 s6, s01311; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s61312; CHECK-NOFP-NEXT: vmovx.f16 s6, s11313; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11314; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s61315; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21316; CHECK-NOFP-NEXT: vmovx.f16 s2, s21317; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21318; CHECK-NOFP-NEXT: vmovx.f16 s2, s31319; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s31320; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21321; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s01322; CHECK-NOFP-NEXT: bx lr1323entry:1324 %z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)1325 %c = fcmp fast ogt half %y, %z1326 %r = select i1 %c, half %y, half %z1327 ret half %r1328}1329 1330define arm_aapcs_vfpcc half @fmax_v16f16_acc(<16 x half> %x, half %y) {1331; CHECK-FP-LABEL: fmax_v16f16_acc:1332; CHECK-FP: @ %bb.0: @ %entry1333; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11334; CHECK-FP-NEXT: vrev32.16 q1, q01335; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11336; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31337; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11338; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21339; CHECK-FP-NEXT: vmaxnm.f16 s0, s8, s01340; CHECK-FP-NEXT: bx lr1341;1342; CHECK-NOFP-LABEL: fmax_v16f16_acc:1343; CHECK-NOFP: @ %bb.0: @ %entry1344; CHECK-NOFP-NEXT: vmovx.f16 s12, s01345; CHECK-NOFP-NEXT: vmovx.f16 s10, s41346; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41347; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s101348; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s101349; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s51350; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41351; CHECK-NOFP-NEXT: vmovx.f16 s4, s51352; CHECK-NOFP-NEXT: vmovx.f16 s10, s11353; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s10, s41354; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41355; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s61356; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41357; CHECK-NOFP-NEXT: vmovx.f16 s4, s61358; CHECK-NOFP-NEXT: vmovx.f16 s2, s21359; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s41360; CHECK-NOFP-NEXT: vmovx.f16 s4, s31361; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21362; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s71363; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21364; CHECK-NOFP-NEXT: vmovx.f16 s2, s71365; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s21366; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21367; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s01368; CHECK-NOFP-NEXT: bx lr1369entry:1370 %z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)1371 %c = fcmp fast ogt half %y, %z1372 %r = select i1 %c, half %y, half %z1373 ret half %r1374}1375 1376define arm_aapcs_vfpcc double @fmax_v1f64_acc(<1 x double> %x, double %y) {1377; CHECK-LABEL: fmax_v1f64_acc:1378; CHECK: @ %bb.0: @ %entry1379; CHECK-NEXT: vmaxnm.f64 d0, d1, d01380; CHECK-NEXT: bx lr1381entry:1382 %z = call fast double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)1383 %c = fcmp fast ogt double %y, %z1384 %r = select i1 %c, double %y, double %z1385 ret double %r1386}1387 1388define arm_aapcs_vfpcc double @fmax_v2f64_acc(<2 x double> %x, double %y) {1389; CHECK-LABEL: fmax_v2f64_acc:1390; CHECK: @ %bb.0: @ %entry1391; CHECK-NEXT: vmaxnm.f64 d0, d0, d11392; CHECK-NEXT: vmaxnm.f64 d0, d2, d01393; CHECK-NEXT: bx lr1394entry:1395 %z = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)1396 %c = fcmp fast ogt double %y, %z1397 %r = select i1 %c, double %y, double %z1398 ret double %r1399}1400 1401define arm_aapcs_vfpcc double @fmax_v4f64_acc(<4 x double> %x, double %y) {1402; CHECK-LABEL: fmax_v4f64_acc:1403; CHECK: @ %bb.0: @ %entry1404; CHECK-NEXT: vcmp.f64 d1, d31405; CHECK-NEXT: vmrs APSR_nzcv, fpscr1406; CHECK-NEXT: vcmp.f64 d0, d21407; CHECK-NEXT: vselgt.f64 d1, d1, d31408; CHECK-NEXT: vmrs APSR_nzcv, fpscr1409; CHECK-NEXT: vselgt.f64 d0, d0, d21410; CHECK-NEXT: vmaxnm.f64 d0, d0, d11411; CHECK-NEXT: vmaxnm.f64 d0, d4, d01412; CHECK-NEXT: bx lr1413entry:1414 %z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)1415 %c = fcmp fast ogt double %y, %z1416 %r = select i1 %c, double %y, double %z1417 ret double %r1418}1419 1420define arm_aapcs_vfpcc float @fmax_v2f32_acc_nofast(<2 x float> %x, float %y) {1421; CHECK-LABEL: fmax_v2f32_acc_nofast:1422; CHECK: @ %bb.0: @ %entry1423; CHECK-NEXT: vmaxnm.f32 s0, s0, s11424; CHECK-NEXT: vcmp.f32 s4, s01425; CHECK-NEXT: vmrs APSR_nzcv, fpscr1426; CHECK-NEXT: vselgt.f32 s0, s4, s01427; CHECK-NEXT: bx lr1428entry:1429 %z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)1430 %c = fcmp ogt float %y, %z1431 %r = select i1 %c, float %y, float %z1432 ret float %r1433}1434 1435define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) {1436; CHECK-FP-LABEL: fmax_v4f32_acc_nofast:1437; CHECK-FP: @ %bb.0: @ %entry1438; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31439; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11440; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21441; CHECK-FP-NEXT: vcmp.f32 s4, s01442; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr1443; CHECK-FP-NEXT: vselgt.f32 s0, s4, s01444; CHECK-FP-NEXT: bx lr1445;1446; CHECK-NOFP-LABEL: fmax_v4f32_acc_nofast:1447; CHECK-NOFP: @ %bb.0: @ %entry1448; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s11449; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21450; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s31451; CHECK-NOFP-NEXT: vcmp.f32 s4, s01452; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr1453; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s01454; CHECK-NOFP-NEXT: bx lr1455entry:1456 %z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)1457 %c = fcmp ogt float %y, %z1458 %r = select i1 %c, float %y, float %z1459 ret float %r1460}1461 1462define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) {1463; CHECK-FP-LABEL: fmax_v8f32_acc_nofast:1464; CHECK-FP: @ %bb.0: @ %entry1465; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q11466; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s31467; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s11468; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s21469; CHECK-FP-NEXT: vcmp.f32 s8, s01470; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr1471; CHECK-FP-NEXT: vselgt.f32 s0, s8, s01472; CHECK-FP-NEXT: bx lr1473;1474; CHECK-NOFP-LABEL: fmax_v8f32_acc_nofast:1475; CHECK-NOFP: @ %bb.0: @ %entry1476; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s1, s51477; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s41478; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s101479; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s61480; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21481; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s71482; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s21483; CHECK-NOFP-NEXT: vcmp.f32 s8, s01484; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr1485; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s01486; CHECK-NOFP-NEXT: bx lr1487entry:1488 %z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)1489 %c = fcmp ogt float %y, %z1490 %r = select i1 %c, float %y, float %z1491 ret float %r1492}1493 1494define arm_aapcs_vfpcc half @fmax_v4f16_acc_nofast(<4 x half> %x, half %y) {1495; CHECK-FP-LABEL: fmax_v4f16_acc_nofast:1496; CHECK-FP: @ %bb.0: @ %entry1497; CHECK-FP-NEXT: vmovx.f16 s2, s11498; CHECK-FP-NEXT: vmovx.f16 s6, s01499; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s21500; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s61501; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21502; CHECK-FP-NEXT: vcmp.f16 s4, s01503; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr1504; CHECK-FP-NEXT: vselgt.f16 s0, s4, s01505; CHECK-FP-NEXT: bx lr1506;1507; CHECK-NOFP-LABEL: fmax_v4f16_acc_nofast:1508; CHECK-NOFP: @ %bb.0: @ %entry1509; CHECK-NOFP-NEXT: vmovx.f16 s2, s01510; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21511; CHECK-NOFP-NEXT: vmovx.f16 s2, s11512; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11513; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21514; CHECK-NOFP-NEXT: vcmp.f16 s4, s01515; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr1516; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s01517; CHECK-NOFP-NEXT: bx lr1518entry:1519 %z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)1520 %c = fcmp ogt half %y, %z1521 %r = select i1 %c, half %y, half %z1522 ret half %r1523}1524 1525define arm_aapcs_vfpcc half @fmax_v8f16_acc_nofast(<8 x half> %x, half %y) {1526; CHECK-FP-LABEL: fmax_v8f16_acc_nofast:1527; CHECK-FP: @ %bb.0: @ %entry1528; CHECK-FP-NEXT: vrev32.16 q2, q01529; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q21530; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31531; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11532; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21533; CHECK-FP-NEXT: vcmp.f16 s4, s01534; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr1535; CHECK-FP-NEXT: vselgt.f16 s0, s4, s01536; CHECK-FP-NEXT: bx lr1537;1538; CHECK-NOFP-LABEL: fmax_v8f16_acc_nofast:1539; CHECK-NOFP: @ %bb.0: @ %entry1540; CHECK-NOFP-NEXT: vmovx.f16 s6, s01541; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s61542; CHECK-NOFP-NEXT: vmovx.f16 s6, s11543; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s11544; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s61545; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21546; CHECK-NOFP-NEXT: vmovx.f16 s2, s21547; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21548; CHECK-NOFP-NEXT: vmovx.f16 s2, s31549; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s31550; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21551; CHECK-NOFP-NEXT: vcmp.f16 s4, s01552; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr1553; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s01554; CHECK-NOFP-NEXT: bx lr1555entry:1556 %z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)1557 %c = fcmp ogt half %y, %z1558 %r = select i1 %c, half %y, half %z1559 ret half %r1560}1561 1562define arm_aapcs_vfpcc half @fmax_v16f16_acc_nofast(<16 x half> %x, half %y) {1563; CHECK-FP-LABEL: fmax_v16f16_acc_nofast:1564; CHECK-FP: @ %bb.0: @ %entry1565; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11566; CHECK-FP-NEXT: vrev32.16 q1, q01567; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q11568; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s31569; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s11570; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s21571; CHECK-FP-NEXT: vcmp.f16 s8, s01572; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr1573; CHECK-FP-NEXT: vselgt.f16 s0, s8, s01574; CHECK-FP-NEXT: bx lr1575;1576; CHECK-NOFP-LABEL: fmax_v16f16_acc_nofast:1577; CHECK-NOFP: @ %bb.0: @ %entry1578; CHECK-NOFP-NEXT: vmovx.f16 s12, s01579; CHECK-NOFP-NEXT: vmovx.f16 s10, s41580; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41581; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s101582; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s101583; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s51584; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41585; CHECK-NOFP-NEXT: vmovx.f16 s4, s51586; CHECK-NOFP-NEXT: vmovx.f16 s10, s11587; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s10, s41588; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41589; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s61590; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s41591; CHECK-NOFP-NEXT: vmovx.f16 s4, s61592; CHECK-NOFP-NEXT: vmovx.f16 s2, s21593; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s41594; CHECK-NOFP-NEXT: vmovx.f16 s4, s31595; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21596; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s71597; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21598; CHECK-NOFP-NEXT: vmovx.f16 s2, s71599; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s21600; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s21601; CHECK-NOFP-NEXT: vcmp.f16 s8, s01602; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr1603; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s01604; CHECK-NOFP-NEXT: bx lr1605entry:1606 %z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)1607 %c = fcmp ogt half %y, %z1608 %r = select i1 %c, half %y, half %z1609 ret half %r1610}1611 1612define arm_aapcs_vfpcc double @fmax_v1f64_acc_nofast(<1 x double> %x, double %y) {1613; CHECK-LABEL: fmax_v1f64_acc_nofast:1614; CHECK: @ %bb.0: @ %entry1615; CHECK-NEXT: vcmp.f64 d1, d01616; CHECK-NEXT: vmrs APSR_nzcv, fpscr1617; CHECK-NEXT: vselgt.f64 d0, d1, d01618; CHECK-NEXT: bx lr1619entry:1620 %z = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)1621 %c = fcmp ogt double %y, %z1622 %r = select i1 %c, double %y, double %z1623 ret double %r1624}1625 1626define arm_aapcs_vfpcc double @fmax_v2f64_acc_nofast(<2 x double> %x, double %y) {1627; CHECK-LABEL: fmax_v2f64_acc_nofast:1628; CHECK: @ %bb.0: @ %entry1629; CHECK-NEXT: vmaxnm.f64 d0, d0, d11630; CHECK-NEXT: vcmp.f64 d2, d01631; CHECK-NEXT: vmrs APSR_nzcv, fpscr1632; CHECK-NEXT: vselgt.f64 d0, d2, d01633; CHECK-NEXT: bx lr1634entry:1635 %z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)1636 %c = fcmp ogt double %y, %z1637 %r = select i1 %c, double %y, double %z1638 ret double %r1639}1640 1641define arm_aapcs_vfpcc double @fmax_v4f64_acc_nofast(<4 x double> %x, double %y) {1642; CHECK-LABEL: fmax_v4f64_acc_nofast:1643; CHECK: @ %bb.0: @ %entry1644; CHECK-NEXT: vmaxnm.f64 d1, d1, d31645; CHECK-NEXT: vmaxnm.f64 d0, d0, d21646; CHECK-NEXT: vmaxnm.f64 d0, d0, d11647; CHECK-NEXT: vcmp.f64 d4, d01648; CHECK-NEXT: vmrs APSR_nzcv, fpscr1649; CHECK-NEXT: vselgt.f64 d0, d4, d01650; CHECK-NEXT: bx lr1651entry:1652 %z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)1653 %c = fcmp ogt double %y, %z1654 %r = select i1 %c, double %y, double %z1655 ret double %r1656}1657 1658declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>)1659declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)1660declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)1661declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)1662declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)1663declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)1664declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)1665declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)1666declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)1667declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)1668declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)1669declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)1670declare half @llvm.vector.reduce.fmax.v16f16(<16 x half>)1671declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)1672declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)1673declare half @llvm.vector.reduce.fmax.v8f16(<8 x half>)1674declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>)1675declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)1676declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)1677declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>)1678