375 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP4 5define arm_aapcs_vfpcc float @fmul_v2f32(<2 x float> %x, float %y) {6; CHECK-LABEL: fmul_v2f32:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmul.f32 s0, s0, s19; CHECK-NEXT: vmul.f32 s0, s4, s010; CHECK-NEXT: bx lr11entry:12 %z = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)13 ret float %z14}15 16define arm_aapcs_vfpcc float @fmul_v4f32(<4 x float> %x, float %y) {17; CHECK-FP-LABEL: fmul_v4f32:18; CHECK-FP: @ %bb.0: @ %entry19; CHECK-FP-NEXT: vmul.f32 s2, s2, s320; CHECK-FP-NEXT: vmul.f32 s0, s0, s121; CHECK-FP-NEXT: vmul.f32 s0, s0, s222; CHECK-FP-NEXT: vmul.f32 s0, s4, s023; CHECK-FP-NEXT: bx lr24;25; CHECK-NOFP-LABEL: fmul_v4f32:26; CHECK-NOFP: @ %bb.0: @ %entry27; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s128; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s229; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s330; CHECK-NOFP-NEXT: vmul.f32 s0, s4, s031; CHECK-NOFP-NEXT: bx lr32entry:33 %z = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)34 ret float %z35}36 37define arm_aapcs_vfpcc float @fmul_v8f32(<8 x float> %x, float %y) {38; CHECK-FP-LABEL: fmul_v8f32:39; CHECK-FP: @ %bb.0: @ %entry40; CHECK-FP-NEXT: vmul.f32 q0, q0, q141; CHECK-FP-NEXT: vmul.f32 s2, s2, s342; CHECK-FP-NEXT: vmul.f32 s0, s0, s143; CHECK-FP-NEXT: vmul.f32 s0, s0, s244; CHECK-FP-NEXT: vmul.f32 s0, s8, s045; CHECK-FP-NEXT: bx lr46;47; CHECK-NOFP-LABEL: fmul_v8f32:48; CHECK-NOFP: @ %bb.0: @ %entry49; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s450; CHECK-NOFP-NEXT: vmul.f32 s10, s1, s551; CHECK-NOFP-NEXT: vmul.f32 s2, s2, s652; CHECK-NOFP-NEXT: vmul.f32 s4, s3, s753; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s1054; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s255; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s456; CHECK-NOFP-NEXT: vmul.f32 s0, s8, s057; CHECK-NOFP-NEXT: bx lr58entry:59 %z = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)60 ret float %z61}62 63define arm_aapcs_vfpcc half @fmul_v2f16(<2 x half> %x, half %y) {64; CHECK-LABEL: fmul_v2f16:65; CHECK: @ %bb.0: @ %entry66; CHECK-NEXT: vmovx.f16 s2, s067; CHECK-NEXT: vmul.f16 s0, s0, s268; CHECK-NEXT: vmul.f16 s0, s4, s069; CHECK-NEXT: bx lr70entry:71 %z = call fast half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)72 ret half %z73}74 75define arm_aapcs_vfpcc half @fmul_v4f16(<4 x half> %x, half %y) {76; CHECK-FP-LABEL: fmul_v4f16:77; CHECK-FP: @ %bb.0: @ %entry78; CHECK-FP-NEXT: vmovx.f16 s2, s179; CHECK-FP-NEXT: vmovx.f16 s6, s080; CHECK-FP-NEXT: vmul.f16 s2, s1, s281; CHECK-FP-NEXT: vmul.f16 s0, s0, s682; CHECK-FP-NEXT: vmul.f16 s0, s0, s283; CHECK-FP-NEXT: vmul.f16 s0, s4, s084; CHECK-FP-NEXT: bx lr85;86; CHECK-NOFP-LABEL: fmul_v4f16:87; CHECK-NOFP: @ %bb.0: @ %entry88; CHECK-NOFP-NEXT: vmovx.f16 s2, s089; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s290; CHECK-NOFP-NEXT: vmovx.f16 s2, s191; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s192; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s293; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s094; CHECK-NOFP-NEXT: bx lr95entry:96 %z = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)97 ret half %z98}99 100define arm_aapcs_vfpcc half @fmul_v8f16(<8 x half> %x, half %y) {101; CHECK-FP-LABEL: fmul_v8f16:102; CHECK-FP: @ %bb.0: @ %entry103; CHECK-FP-NEXT: vrev32.16 q2, q0104; CHECK-FP-NEXT: vmul.f16 q0, q0, q2105; CHECK-FP-NEXT: vmul.f16 s2, s2, s3106; CHECK-FP-NEXT: vmul.f16 s0, s0, s1107; CHECK-FP-NEXT: vmul.f16 s0, s0, s2108; CHECK-FP-NEXT: vmul.f16 s0, s4, s0109; CHECK-FP-NEXT: bx lr110;111; CHECK-NOFP-LABEL: fmul_v8f16:112; CHECK-NOFP: @ %bb.0: @ %entry113; CHECK-NOFP-NEXT: vmovx.f16 s6, s0114; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s6115; CHECK-NOFP-NEXT: vmovx.f16 s6, s1116; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s1117; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s6118; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2119; CHECK-NOFP-NEXT: vmovx.f16 s2, s2120; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2121; CHECK-NOFP-NEXT: vmovx.f16 s2, s3122; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s3123; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2124; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s0125; CHECK-NOFP-NEXT: bx lr126entry:127 %z = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)128 ret half %z129}130 131define arm_aapcs_vfpcc half @fmul_v16f16(<16 x half> %x, half %y) {132; CHECK-FP-LABEL: fmul_v16f16:133; CHECK-FP: @ %bb.0: @ %entry134; CHECK-FP-NEXT: vmul.f16 q0, q0, q1135; CHECK-FP-NEXT: vrev32.16 q1, q0136; CHECK-FP-NEXT: vmul.f16 q0, q0, q1137; CHECK-FP-NEXT: vmul.f16 s2, s2, s3138; CHECK-FP-NEXT: vmul.f16 s0, s0, s1139; CHECK-FP-NEXT: vmul.f16 s0, s0, s2140; CHECK-FP-NEXT: vmul.f16 s0, s8, s0141; CHECK-FP-NEXT: bx lr142;143; CHECK-NOFP-LABEL: fmul_v16f16:144; CHECK-NOFP: @ %bb.0: @ %entry145; CHECK-NOFP-NEXT: vmovx.f16 s12, s0146; CHECK-NOFP-NEXT: vmovx.f16 s10, s4147; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4148; CHECK-NOFP-NEXT: vmul.f16 s10, s12, s10149; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s10150; CHECK-NOFP-NEXT: vmul.f16 s4, s1, s5151; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4152; CHECK-NOFP-NEXT: vmovx.f16 s4, s5153; CHECK-NOFP-NEXT: vmovx.f16 s10, s1154; CHECK-NOFP-NEXT: vmul.f16 s4, s10, s4155; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4156; CHECK-NOFP-NEXT: vmul.f16 s4, s2, s6157; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4158; CHECK-NOFP-NEXT: vmovx.f16 s4, s6159; CHECK-NOFP-NEXT: vmovx.f16 s2, s2160; CHECK-NOFP-NEXT: vmul.f16 s2, s2, s4161; CHECK-NOFP-NEXT: vmovx.f16 s4, s3162; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2163; CHECK-NOFP-NEXT: vmul.f16 s2, s3, s7164; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2165; CHECK-NOFP-NEXT: vmovx.f16 s2, s7166; CHECK-NOFP-NEXT: vmul.f16 s2, s4, s2167; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2168; CHECK-NOFP-NEXT: vmul.f16 s0, s8, s0169; CHECK-NOFP-NEXT: bx lr170entry:171 %z = call fast half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x)172 ret half %z173}174 175define arm_aapcs_vfpcc double @fmul_v1f64(<1 x double> %x, double %y) {176; CHECK-LABEL: fmul_v1f64:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: vmul.f64 d0, d1, d0179; CHECK-NEXT: bx lr180entry:181 %z = call fast double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x)182 ret double %z183}184 185define arm_aapcs_vfpcc double @fmul_v2f64(<2 x double> %x, double %y) {186; CHECK-LABEL: fmul_v2f64:187; CHECK: @ %bb.0: @ %entry188; CHECK-NEXT: vmul.f64 d0, d0, d1189; CHECK-NEXT: vmul.f64 d0, d2, d0190; CHECK-NEXT: bx lr191entry:192 %z = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)193 ret double %z194}195 196define arm_aapcs_vfpcc double @fmul_v4f64(<4 x double> %x, double %y) {197; CHECK-LABEL: fmul_v4f64:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vmul.f64 d1, d1, d3200; CHECK-NEXT: vmul.f64 d0, d0, d2201; CHECK-NEXT: vmul.f64 d0, d0, d1202; CHECK-NEXT: vmul.f64 d0, d4, d0203; CHECK-NEXT: bx lr204entry:205 %z = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)206 ret double %z207}208 209define arm_aapcs_vfpcc float @fmul_v2f32_nofast(<2 x float> %x, float %y) {210; CHECK-LABEL: fmul_v2f32_nofast:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: vmul.f32 s0, s4, s0213; CHECK-NEXT: vmul.f32 s0, s0, s1214; CHECK-NEXT: bx lr215entry:216 %z = call float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)217 ret float %z218}219 220define arm_aapcs_vfpcc float @fmul_v4f32_nofast(<4 x float> %x, float %y) {221; CHECK-LABEL: fmul_v4f32_nofast:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmul.f32 s0, s4, s0224; CHECK-NEXT: vmul.f32 s0, s0, s1225; CHECK-NEXT: vmul.f32 s0, s0, s2226; CHECK-NEXT: vmul.f32 s0, s0, s3227; CHECK-NEXT: bx lr228entry:229 %z = call float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)230 ret float %z231}232 233define arm_aapcs_vfpcc float @fmul_v8f32_nofast(<8 x float> %x, float %y) {234; CHECK-LABEL: fmul_v8f32_nofast:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: vmul.f32 s0, s8, s0237; CHECK-NEXT: vmul.f32 s0, s0, s1238; CHECK-NEXT: vmul.f32 s0, s0, s2239; CHECK-NEXT: vmul.f32 s0, s0, s3240; CHECK-NEXT: vmul.f32 s0, s0, s4241; CHECK-NEXT: vmul.f32 s0, s0, s5242; CHECK-NEXT: vmul.f32 s0, s0, s6243; CHECK-NEXT: vmul.f32 s0, s0, s7244; CHECK-NEXT: bx lr245entry:246 %z = call float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)247 ret float %z248}249 250define arm_aapcs_vfpcc half @fmul_v2f16_nofast(<2 x half> %x, half %y) {251; CHECK-LABEL: fmul_v2f16_nofast:252; CHECK: @ %bb.0: @ %entry253; CHECK-NEXT: vmul.f16 s2, s4, s0254; CHECK-NEXT: vmovx.f16 s0, s0255; CHECK-NEXT: vmul.f16 s0, s2, s0256; CHECK-NEXT: bx lr257entry:258 %z = call half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)259 ret half %z260}261 262define arm_aapcs_vfpcc half @fmul_v4f16_nofast(<4 x half> %x, half %y) {263; CHECK-LABEL: fmul_v4f16_nofast:264; CHECK: @ %bb.0: @ %entry265; CHECK-NEXT: vmul.f16 s2, s4, s0266; CHECK-NEXT: vmovx.f16 s0, s0267; CHECK-NEXT: vmul.f16 s0, s2, s0268; CHECK-NEXT: vmovx.f16 s2, s1269; CHECK-NEXT: vmul.f16 s0, s0, s1270; CHECK-NEXT: vmul.f16 s0, s0, s2271; CHECK-NEXT: bx lr272entry:273 %z = call half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)274 ret half %z275}276 277define arm_aapcs_vfpcc half @fmul_v8f16_nofast(<8 x half> %x, half %y) {278; CHECK-LABEL: fmul_v8f16_nofast:279; CHECK: @ %bb.0: @ %entry280; CHECK-NEXT: vmul.f16 s4, s4, s0281; CHECK-NEXT: vmovx.f16 s0, s0282; CHECK-NEXT: vmul.f16 s0, s4, s0283; CHECK-NEXT: vmovx.f16 s4, s1284; CHECK-NEXT: vmul.f16 s0, s0, s1285; CHECK-NEXT: vmul.f16 s0, s0, s4286; CHECK-NEXT: vmul.f16 s0, s0, s2287; CHECK-NEXT: vmovx.f16 s2, s2288; CHECK-NEXT: vmul.f16 s0, s0, s2289; CHECK-NEXT: vmovx.f16 s2, s3290; CHECK-NEXT: vmul.f16 s0, s0, s3291; CHECK-NEXT: vmul.f16 s0, s0, s2292; CHECK-NEXT: bx lr293entry:294 %z = call half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)295 ret half %z296}297 298define arm_aapcs_vfpcc half @fmul_v16f16_nofast(<16 x half> %x, half %y) {299; CHECK-LABEL: fmul_v16f16_nofast:300; CHECK: @ %bb.0: @ %entry301; CHECK-NEXT: vmul.f16 s8, s8, s0302; CHECK-NEXT: vmovx.f16 s0, s0303; CHECK-NEXT: vmul.f16 s0, s8, s0304; CHECK-NEXT: vmovx.f16 s8, s1305; CHECK-NEXT: vmul.f16 s0, s0, s1306; CHECK-NEXT: vmul.f16 s0, s0, s8307; CHECK-NEXT: vmul.f16 s0, s0, s2308; CHECK-NEXT: vmovx.f16 s2, s2309; CHECK-NEXT: vmul.f16 s0, s0, s2310; CHECK-NEXT: vmovx.f16 s2, s3311; CHECK-NEXT: vmul.f16 s0, s0, s3312; CHECK-NEXT: vmul.f16 s0, s0, s2313; CHECK-NEXT: vmovx.f16 s2, s4314; CHECK-NEXT: vmul.f16 s0, s0, s4315; CHECK-NEXT: vmul.f16 s0, s0, s2316; CHECK-NEXT: vmovx.f16 s2, s5317; CHECK-NEXT: vmul.f16 s0, s0, s5318; CHECK-NEXT: vmul.f16 s0, s0, s2319; CHECK-NEXT: vmovx.f16 s2, s6320; CHECK-NEXT: vmul.f16 s0, s0, s6321; CHECK-NEXT: vmul.f16 s0, s0, s2322; CHECK-NEXT: vmovx.f16 s2, s7323; CHECK-NEXT: vmul.f16 s0, s0, s7324; CHECK-NEXT: vmul.f16 s0, s0, s2325; CHECK-NEXT: bx lr326entry:327 %z = call half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x)328 ret half %z329}330 331define arm_aapcs_vfpcc double @fmul_v1f64_nofast(<1 x double> %x, double %y) {332; CHECK-LABEL: fmul_v1f64_nofast:333; CHECK: @ %bb.0: @ %entry334; CHECK-NEXT: vmul.f64 d0, d1, d0335; CHECK-NEXT: bx lr336entry:337 %z = call double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x)338 ret double %z339}340 341define arm_aapcs_vfpcc double @fmul_v2f64_nofast(<2 x double> %x, double %y) {342; CHECK-LABEL: fmul_v2f64_nofast:343; CHECK: @ %bb.0: @ %entry344; CHECK-NEXT: vmul.f64 d0, d2, d0345; CHECK-NEXT: vmul.f64 d0, d0, d1346; CHECK-NEXT: bx lr347entry:348 %z = call double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)349 ret double %z350}351 352define arm_aapcs_vfpcc double @fmul_v4f64_nofast(<4 x double> %x, double %y) {353; CHECK-LABEL: fmul_v4f64_nofast:354; CHECK: @ %bb.0: @ %entry355; CHECK-NEXT: vmul.f64 d0, d4, d0356; CHECK-NEXT: vmul.f64 d0, d0, d1357; CHECK-NEXT: vmul.f64 d0, d0, d2358; CHECK-NEXT: vmul.f64 d0, d0, d3359; CHECK-NEXT: bx lr360entry:361 %z = call double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)362 ret double %z363}364 365declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)366declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)367declare double @llvm.vector.reduce.fmul.f64.v4f64(double, <4 x double>)368declare float @llvm.vector.reduce.fmul.f32.v2f32(float, <2 x float>)369declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)370declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)371declare half @llvm.vector.reduce.fmul.f16.v16f16(half, <16 x half>)372declare half @llvm.vector.reduce.fmul.f16.v2f16(half, <2 x half>)373declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)374declare half @llvm.vector.reduce.fmul.f16.v8f16(half, <8 x half>)375