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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @add_ashr_v16i8(<16 x i8> %src1, <16 x i8> %src2) {5; CHECK-LABEL: add_ashr_v16i8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vadd.i8 q0, q0, q18; CHECK-NEXT: vshr.s8 q0, q0, #19; CHECK-NEXT: bx lr10entry:11 %0 = add <16 x i8> %src1, %src212 %1 = ashr <16 x i8> %0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>13 ret <16 x i8> %114}15 16define arm_aapcs_vfpcc <8 x i16> @add_ashr_v8i16(<8 x i16> %src1, <8 x i16> %src2) {17; CHECK-LABEL: add_ashr_v8i16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vadd.i16 q0, q0, q120; CHECK-NEXT: vshr.s16 q0, q0, #121; CHECK-NEXT: bx lr22entry:23 %0 = add <8 x i16> %src1, %src224 %1 = ashr <8 x i16> %0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>25 ret <8 x i16> %126}27 28define arm_aapcs_vfpcc <4 x i32> @add_ashr_v4i32(<4 x i32> %src1, <4 x i32> %src2) {29; CHECK-LABEL: add_ashr_v4i32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vhadd.s32 q0, q0, q132; CHECK-NEXT: bx lr33entry:34 %0 = add nsw <4 x i32> %src1, %src235 %1 = ashr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>36 ret <4 x i32> %137}38 39define arm_aapcs_vfpcc <16 x i8> @add_lshr_v16i8(<16 x i8> %src1, <16 x i8> %src2) {40; CHECK-LABEL: add_lshr_v16i8:41; CHECK: @ %bb.0: @ %entry42; CHECK-NEXT: vadd.i8 q0, q0, q143; CHECK-NEXT: vshr.u8 q0, q0, #144; CHECK-NEXT: bx lr45entry:46 %0 = add <16 x i8> %src1, %src247 %1 = lshr <16 x i8> %0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>48 ret <16 x i8> %149}50 51define arm_aapcs_vfpcc <8 x i16> @add_lshr_v8i16(<8 x i16> %src1, <8 x i16> %src2) {52; CHECK-LABEL: add_lshr_v8i16:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: vadd.i16 q0, q0, q155; CHECK-NEXT: vshr.u16 q0, q0, #156; CHECK-NEXT: bx lr57entry:58 %0 = add <8 x i16> %src1, %src259 %1 = lshr <8 x i16> %0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>60 ret <8 x i16> %161}62 63define arm_aapcs_vfpcc <4 x i32> @add_lshr_v4i32(<4 x i32> %src1, <4 x i32> %src2) {64; CHECK-LABEL: add_lshr_v4i32:65; CHECK: @ %bb.0: @ %entry66; CHECK-NEXT: vadd.i32 q0, q0, q167; CHECK-NEXT: vshr.u32 q0, q0, #168; CHECK-NEXT: bx lr69entry:70 %0 = add nsw <4 x i32> %src1, %src271 %1 = lshr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>72 ret <4 x i32> %173}74 75define arm_aapcs_vfpcc <16 x i8> @sub_ashr_v16i8(<16 x i8> %src1, <16 x i8> %src2) {76; CHECK-LABEL: sub_ashr_v16i8:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vsub.i8 q0, q0, q179; CHECK-NEXT: vshr.s8 q0, q0, #180; CHECK-NEXT: bx lr81entry:82 %0 = sub <16 x i8> %src1, %src283 %1 = ashr <16 x i8> %0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>84 ret <16 x i8> %185}86 87define arm_aapcs_vfpcc <8 x i16> @sub_ashr_v8i16(<8 x i16> %src1, <8 x i16> %src2) {88; CHECK-LABEL: sub_ashr_v8i16:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: vsub.i16 q0, q0, q191; CHECK-NEXT: vshr.s16 q0, q0, #192; CHECK-NEXT: bx lr93entry:94 %0 = sub <8 x i16> %src1, %src295 %1 = ashr <8 x i16> %0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>96 ret <8 x i16> %197}98 99define arm_aapcs_vfpcc <4 x i32> @sub_ashr_v4i32(<4 x i32> %src1, <4 x i32> %src2) {100; CHECK-LABEL: sub_ashr_v4i32:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: vhsub.s32 q0, q0, q1103; CHECK-NEXT: bx lr104entry:105 %0 = sub nsw <4 x i32> %src1, %src2106 %1 = ashr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>107 ret <4 x i32> %1108}109 110define arm_aapcs_vfpcc <16 x i8> @sub_lshr_v16i8(<16 x i8> %src1, <16 x i8> %src2) {111; CHECK-LABEL: sub_lshr_v16i8:112; CHECK: @ %bb.0: @ %entry113; CHECK-NEXT: vsub.i8 q0, q0, q1114; CHECK-NEXT: vshr.u8 q0, q0, #1115; CHECK-NEXT: bx lr116entry:117 %0 = sub <16 x i8> %src1, %src2118 %1 = lshr <16 x i8> %0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>119 ret <16 x i8> %1120}121 122define arm_aapcs_vfpcc <8 x i16> @sub_lshr_v8i16(<8 x i16> %src1, <8 x i16> %src2) {123; CHECK-LABEL: sub_lshr_v8i16:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vsub.i16 q0, q0, q1126; CHECK-NEXT: vshr.u16 q0, q0, #1127; CHECK-NEXT: bx lr128entry:129 %0 = sub <8 x i16> %src1, %src2130 %1 = lshr <8 x i16> %0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>131 ret <8 x i16> %1132}133 134define arm_aapcs_vfpcc <4 x i32> @sub_lshr_v4i32(<4 x i32> %src1, <4 x i32> %src2) {135; CHECK-LABEL: sub_lshr_v4i32:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vsub.i32 q0, q0, q1138; CHECK-NEXT: vshr.u32 q0, q0, #1139; CHECK-NEXT: bx lr140entry:141 %0 = sub nsw <4 x i32> %src1, %src2142 %1 = lshr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>143 ret <4 x i32> %1144}145 146 147 148define arm_aapcs_vfpcc <16 x i8> @add_sdiv_v16i8(<16 x i8> %src1, <16 x i8> %src2) {149; CHECK-LABEL: add_sdiv_v16i8:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vadd.i8 q0, q0, q1152; CHECK-NEXT: vshr.u8 q1, q0, #7153; CHECK-NEXT: vadd.i8 q0, q0, q1154; CHECK-NEXT: vshr.s8 q0, q0, #1155; CHECK-NEXT: bx lr156entry:157 %0 = add <16 x i8> %src1, %src2158 %1 = sdiv <16 x i8> %0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>159 ret <16 x i8> %1160}161 162define arm_aapcs_vfpcc <8 x i16> @add_sdiv_v8i16(<8 x i16> %src1, <8 x i16> %src2) {163; CHECK-LABEL: add_sdiv_v8i16:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vadd.i16 q0, q0, q1166; CHECK-NEXT: vshr.u16 q1, q0, #15167; CHECK-NEXT: vadd.i16 q0, q0, q1168; CHECK-NEXT: vshr.s16 q0, q0, #1169; CHECK-NEXT: bx lr170entry:171 %0 = add <8 x i16> %src1, %src2172 %1 = sdiv <8 x i16> %0, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>173 ret <8 x i16> %1174}175 176define arm_aapcs_vfpcc <4 x i32> @add_sdiv_v4i32(<4 x i32> %src1, <4 x i32> %src2) {177; CHECK-LABEL: add_sdiv_v4i32:178; CHECK: @ %bb.0: @ %entry179; CHECK-NEXT: vadd.i32 q0, q0, q1180; CHECK-NEXT: vshr.u32 q1, q0, #31181; CHECK-NEXT: vadd.i32 q0, q0, q1182; CHECK-NEXT: vshr.s32 q0, q0, #1183; CHECK-NEXT: bx lr184entry:185 %0 = add nsw <4 x i32> %src1, %src2186 %1 = sdiv <4 x i32> %0, <i32 2, i32 2, i32 2, i32 2>187 ret <4 x i32> %1188}189 190define arm_aapcs_vfpcc <16 x i8> @add_udiv_v16i8(<16 x i8> %src1, <16 x i8> %src2) {191; CHECK-LABEL: add_udiv_v16i8:192; CHECK: @ %bb.0: @ %entry193; CHECK-NEXT: vadd.i8 q0, q0, q1194; CHECK-NEXT: vshr.u8 q0, q0, #1195; CHECK-NEXT: bx lr196entry:197 %0 = add <16 x i8> %src1, %src2198 %1 = udiv <16 x i8> %0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>199 ret <16 x i8> %1200}201 202define arm_aapcs_vfpcc <8 x i16> @add_udiv_v8i16(<8 x i16> %src1, <8 x i16> %src2) {203; CHECK-LABEL: add_udiv_v8i16:204; CHECK: @ %bb.0: @ %entry205; CHECK-NEXT: vadd.i16 q0, q0, q1206; CHECK-NEXT: vshr.u16 q0, q0, #1207; CHECK-NEXT: bx lr208entry:209 %0 = add <8 x i16> %src1, %src2210 %1 = udiv <8 x i16> %0, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>211 ret <8 x i16> %1212}213 214define arm_aapcs_vfpcc <4 x i32> @add_udiv_v4i32(<4 x i32> %src1, <4 x i32> %src2) {215; CHECK-LABEL: add_udiv_v4i32:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vadd.i32 q0, q0, q1218; CHECK-NEXT: vshr.u32 q0, q0, #1219; CHECK-NEXT: bx lr220entry:221 %0 = add nsw <4 x i32> %src1, %src2222 %1 = udiv <4 x i32> %0, <i32 2, i32 2, i32 2, i32 2>223 ret <4 x i32> %1224}225 226define arm_aapcs_vfpcc <16 x i8> @sub_sdiv_v16i8(<16 x i8> %src1, <16 x i8> %src2) {227; CHECK-LABEL: sub_sdiv_v16i8:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: vsub.i8 q0, q0, q1230; CHECK-NEXT: vshr.u8 q1, q0, #7231; CHECK-NEXT: vadd.i8 q0, q0, q1232; CHECK-NEXT: vshr.s8 q0, q0, #1233; CHECK-NEXT: bx lr234entry:235 %0 = sub <16 x i8> %src1, %src2236 %1 = sdiv <16 x i8> %0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>237 ret <16 x i8> %1238}239 240define arm_aapcs_vfpcc <8 x i16> @sub_sdiv_v8i16(<8 x i16> %src1, <8 x i16> %src2) {241; CHECK-LABEL: sub_sdiv_v8i16:242; CHECK: @ %bb.0: @ %entry243; CHECK-NEXT: vsub.i16 q0, q0, q1244; CHECK-NEXT: vshr.u16 q1, q0, #15245; CHECK-NEXT: vadd.i16 q0, q0, q1246; CHECK-NEXT: vshr.s16 q0, q0, #1247; CHECK-NEXT: bx lr248entry:249 %0 = sub <8 x i16> %src1, %src2250 %1 = sdiv <8 x i16> %0, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>251 ret <8 x i16> %1252}253 254define arm_aapcs_vfpcc <4 x i32> @sub_sdiv_v4i32(<4 x i32> %src1, <4 x i32> %src2) {255; CHECK-LABEL: sub_sdiv_v4i32:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: vsub.i32 q0, q0, q1258; CHECK-NEXT: vshr.u32 q1, q0, #31259; CHECK-NEXT: vadd.i32 q0, q0, q1260; CHECK-NEXT: vshr.s32 q0, q0, #1261; CHECK-NEXT: bx lr262entry:263 %0 = sub nsw <4 x i32> %src1, %src2264 %1 = sdiv <4 x i32> %0, <i32 2, i32 2, i32 2, i32 2>265 ret <4 x i32> %1266}267 268define arm_aapcs_vfpcc <16 x i8> @sub_udiv_v16i8(<16 x i8> %src1, <16 x i8> %src2) {269; CHECK-LABEL: sub_udiv_v16i8:270; CHECK: @ %bb.0: @ %entry271; CHECK-NEXT: vsub.i8 q0, q0, q1272; CHECK-NEXT: vshr.u8 q0, q0, #1273; CHECK-NEXT: bx lr274entry:275 %0 = sub <16 x i8> %src1, %src2276 %1 = udiv <16 x i8> %0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>277 ret <16 x i8> %1278}279 280define arm_aapcs_vfpcc <8 x i16> @sub_udiv_v8i16(<8 x i16> %src1, <8 x i16> %src2) {281; CHECK-LABEL: sub_udiv_v8i16:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: vsub.i16 q0, q0, q1284; CHECK-NEXT: vshr.u16 q0, q0, #1285; CHECK-NEXT: bx lr286entry:287 %0 = sub <8 x i16> %src1, %src2288 %1 = udiv <8 x i16> %0, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>289 ret <8 x i16> %1290}291 292define arm_aapcs_vfpcc <4 x i32> @sub_udiv_v4i32(<4 x i32> %src1, <4 x i32> %src2) {293; CHECK-LABEL: sub_udiv_v4i32:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vsub.i32 q0, q0, q1296; CHECK-NEXT: vshr.u32 q0, q0, #1297; CHECK-NEXT: bx lr298entry:299 %0 = sub nsw <4 x i32> %src1, %src2300 %1 = udiv <4 x i32> %0, <i32 2, i32 2, i32 2, i32 2>301 ret <4 x i32> %1302}303 304