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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s3 4; i325 6define ptr @vld2_v4i32(ptr %src, ptr %dst) {7; CHECK-LABEL: vld2_v4i32:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vld20.32 {q0, q1}, [r0]10; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!11; CHECK-NEXT: vadd.i32 q0, q0, q112; CHECK-NEXT: vstrw.32 q0, [r1]13; CHECK-NEXT: bx lr14entry:15 %l1 = load <8 x i32>, ptr %src, align 416 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>17 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>18 %a = add <4 x i32> %s1, %s219 store <4 x i32> %a, ptr %dst20 %ret = getelementptr inbounds <8 x i32>, ptr %src, i32 121 ret ptr %ret22}23 24; i1625 26define ptr @vld2_v8i16(ptr %src, ptr %dst) {27; CHECK-LABEL: vld2_v8i16:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vld20.16 {q0, q1}, [r0]30; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!31; CHECK-NEXT: vadd.i16 q0, q0, q132; CHECK-NEXT: vstrw.32 q0, [r1]33; CHECK-NEXT: bx lr34entry:35 %l1 = load <16 x i16>, ptr %src, align 436 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>37 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>38 %a = add <8 x i16> %s1, %s239 store <8 x i16> %a, ptr %dst40 %ret = getelementptr inbounds <16 x i16>, ptr %src, i32 141 ret ptr %ret42}43 44; i845 46define ptr @vld2_v16i8(ptr %src, ptr %dst) {47; CHECK-LABEL: vld2_v16i8:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vld20.8 {q0, q1}, [r0]50; CHECK-NEXT: vld21.8 {q0, q1}, [r0]!51; CHECK-NEXT: vadd.i8 q0, q0, q152; CHECK-NEXT: vstrw.32 q0, [r1]53; CHECK-NEXT: bx lr54entry:55 %l1 = load <32 x i8>, ptr %src, align 456 %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>57 %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>58 %a = add <16 x i8> %s1, %s259 store <16 x i8> %a, ptr %dst60 %ret = getelementptr inbounds <32 x i8>, ptr %src, i32 161 ret ptr %ret62}63 64; i6465 66define ptr @vld2_v2i64(ptr %src, ptr %dst) {67; CHECK-LABEL: vld2_v2i64:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: .save {r4, r5, r6, r7, lr}70; CHECK-NEXT: push {r4, r5, r6, r7, lr}71; CHECK-NEXT: vldrw.u32 q0, [r0, #16]72; CHECK-NEXT: vmov r2, r12, d173; CHECK-NEXT: vmov r3, lr, d074; CHECK-NEXT: vldrw.u32 q0, [r0], #3275; CHECK-NEXT: vmov r4, r7, d176; CHECK-NEXT: adds r2, r2, r377; CHECK-NEXT: vmov r3, r6, d078; CHECK-NEXT: adc.w r5, lr, r1279; CHECK-NEXT: adds r3, r3, r480; CHECK-NEXT: adcs r7, r681; CHECK-NEXT: vmov q0[2], q0[0], r3, r282; CHECK-NEXT: vmov q0[3], q0[1], r7, r583; CHECK-NEXT: vstrw.32 q0, [r1]84; CHECK-NEXT: pop {r4, r5, r6, r7, pc}85entry:86 %l1 = load <4 x i64>, ptr %src, align 487 %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>88 %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>89 %a = add <2 x i64> %s1, %s290 store <2 x i64> %a, ptr %dst91 %ret = getelementptr inbounds <4 x i64>, ptr %src, i32 192 ret ptr %ret93}94 95; f3296 97define ptr @vld2_v4f32(ptr %src, ptr %dst) {98; CHECK-LABEL: vld2_v4f32:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vld20.32 {q0, q1}, [r0]101; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!102; CHECK-NEXT: vadd.f32 q0, q0, q1103; CHECK-NEXT: vstrw.32 q0, [r1]104; CHECK-NEXT: bx lr105entry:106 %l1 = load <8 x float>, ptr %src, align 4107 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>108 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>109 %a = fadd <4 x float> %s1, %s2110 store <4 x float> %a, ptr %dst111 %ret = getelementptr inbounds <8 x float>, ptr %src, i32 1112 ret ptr %ret113}114 115; f16116 117define ptr @vld2_v8f16(ptr %src, ptr %dst) {118; CHECK-LABEL: vld2_v8f16:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vld20.16 {q0, q1}, [r0]121; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!122; CHECK-NEXT: vadd.f16 q0, q0, q1123; CHECK-NEXT: vstrw.32 q0, [r1]124; CHECK-NEXT: bx lr125entry:126 %l1 = load <16 x half>, ptr %src, align 4127 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>128 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>129 %a = fadd <8 x half> %s1, %s2130 store <8 x half> %a, ptr %dst131 %ret = getelementptr inbounds <16 x half>, ptr %src, i32 1132 ret ptr %ret133}134 135; f64136 137define ptr @vld2_v2f64(ptr %src, ptr %dst) {138; CHECK-LABEL: vld2_v2f64:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vldrw.u32 q0, [r0, #16]141; CHECK-NEXT: vldrw.u32 q1, [r0], #32142; CHECK-NEXT: vadd.f64 d1, d0, d1143; CHECK-NEXT: vadd.f64 d0, d2, d3144; CHECK-NEXT: vstrw.32 q0, [r1]145; CHECK-NEXT: bx lr146entry:147 %l1 = load <4 x double>, ptr %src, align 4148 %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>149 %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>150 %a = fadd <2 x double> %s1, %s2151 store <2 x double> %a, ptr %dst152 %ret = getelementptr inbounds <4 x double>, ptr %src, i32 1153 ret ptr %ret154}155