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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s3 4; i325 6define void @vld2_v2i32(ptr %src, ptr %dst) {7; CHECK-LABEL: vld2_v2i32:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vldrw.u32 q0, [r0]10; CHECK-NEXT: vrev64.32 q1, q011; CHECK-NEXT: vmov r2, s212; CHECK-NEXT: vmov r0, s613; CHECK-NEXT: vmov r3, s014; CHECK-NEXT: add r0, r215; CHECK-NEXT: vmov r2, s416; CHECK-NEXT: add r2, r317; CHECK-NEXT: strd r2, r0, [r1]18; CHECK-NEXT: bx lr19entry:20 %l1 = load <4 x i32>, ptr %src, align 421 %s1 = shufflevector <4 x i32> %l1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>22 %s2 = shufflevector <4 x i32> %l1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>23 %a = add <2 x i32> %s1, %s224 store <2 x i32> %a, ptr %dst25 ret void26}27 28define void @vld2_v4i32(ptr %src, ptr %dst) {29; CHECK-LABEL: vld2_v4i32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vld20.32 {q0, q1}, [r0]32; CHECK-NEXT: vld21.32 {q0, q1}, [r0]33; CHECK-NEXT: vadd.i32 q0, q0, q134; CHECK-NEXT: vstrw.32 q0, [r1]35; CHECK-NEXT: bx lr36entry:37 %l1 = load <8 x i32>, ptr %src, align 438 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>39 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>40 %a = add <4 x i32> %s1, %s241 store <4 x i32> %a, ptr %dst42 ret void43}44 45define void @vld2_v8i32(ptr %src, ptr %dst) {46; CHECK-LABEL: vld2_v8i32:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vld20.32 {q0, q1}, [r0]49; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!50; CHECK-NEXT: vld20.32 {q2, q3}, [r0]51; CHECK-NEXT: vadd.i32 q0, q0, q152; CHECK-NEXT: vld21.32 {q2, q3}, [r0]53; CHECK-NEXT: vstrw.32 q0, [r1]54; CHECK-NEXT: vadd.i32 q1, q2, q355; CHECK-NEXT: vstrw.32 q1, [r1, #16]56; CHECK-NEXT: bx lr57entry:58 %l1 = load <16 x i32>, ptr %src, align 459 %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>60 %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>61 %a = add <8 x i32> %s1, %s262 store <8 x i32> %a, ptr %dst63 ret void64}65 66define void @vld2_v16i32(ptr %src, ptr %dst) {67; CHECK-LABEL: vld2_v16i32:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}70; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}71; CHECK-NEXT: vld20.32 {q0, q1}, [r0]72; CHECK-NEXT: add.w r2, r0, #9673; CHECK-NEXT: add.w r3, r0, #6474; CHECK-NEXT: vld20.32 {q3, q4}, [r2]75; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!76; CHECK-NEXT: vld21.32 {q3, q4}, [r2]77; CHECK-NEXT: vld20.32 {q5, q6}, [r0]78; CHECK-NEXT: vadd.i32 q0, q0, q179; CHECK-NEXT: vld20.32 {q1, q2}, [r3]80; CHECK-NEXT: vadd.i32 q3, q3, q481; CHECK-NEXT: vld21.32 {q5, q6}, [r0]82; CHECK-NEXT: vld21.32 {q1, q2}, [r3]83; CHECK-NEXT: vstrw.32 q3, [r1, #48]84; CHECK-NEXT: vadd.i32 q5, q5, q685; CHECK-NEXT: vstrw.32 q0, [r1]86; CHECK-NEXT: vadd.i32 q1, q1, q287; CHECK-NEXT: vstrw.32 q5, [r1, #16]88; CHECK-NEXT: vstrw.32 q1, [r1, #32]89; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}90; CHECK-NEXT: bx lr91entry:92 %l1 = load <32 x i32>, ptr %src, align 493 %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>94 %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>95 %a = add <16 x i32> %s1, %s296 store <16 x i32> %a, ptr %dst97 ret void98}99 100define void @vld2_v4i32_align1(ptr %src, ptr %dst) {101; CHECK-LABEL: vld2_v4i32_align1:102; CHECK: @ %bb.0: @ %entry103; CHECK-NEXT: vldrb.u8 q0, [r0, #16]104; CHECK-NEXT: vldrb.u8 q1, [r0]105; CHECK-NEXT: vmov.f32 s8, s5106; CHECK-NEXT: vmov.f32 s9, s7107; CHECK-NEXT: vmov.f32 s5, s6108; CHECK-NEXT: vmov.f32 s10, s1109; CHECK-NEXT: vmov.f32 s11, s3110; CHECK-NEXT: vmov.f32 s6, s0111; CHECK-NEXT: vmov.f32 s7, s2112; CHECK-NEXT: vadd.i32 q0, q1, q2113; CHECK-NEXT: vstrw.32 q0, [r1]114; CHECK-NEXT: bx lr115entry:116 %l1 = load <8 x i32>, ptr %src, align 1117 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>118 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>119 %a = add <4 x i32> %s1, %s2120 store <4 x i32> %a, ptr %dst121 ret void122}123 124; i16125 126define void @vld2_v2i16(ptr %src, ptr %dst) {127; CHECK-LABEL: vld2_v2i16:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vldrh.u32 q0, [r0]130; CHECK-NEXT: vrev64.32 q1, q0131; CHECK-NEXT: vmov r2, s2132; CHECK-NEXT: vmov r0, s6133; CHECK-NEXT: add r0, r2134; CHECK-NEXT: strh r0, [r1, #2]135; CHECK-NEXT: vmov r0, s4136; CHECK-NEXT: vmov r2, s0137; CHECK-NEXT: add r0, r2138; CHECK-NEXT: strh r0, [r1]139; CHECK-NEXT: bx lr140entry:141 %l1 = load <4 x i16>, ptr %src, align 2142 %s1 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 0, i32 2>143 %s2 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 1, i32 3>144 %a = add <2 x i16> %s1, %s2145 store <2 x i16> %a, ptr %dst146 ret void147}148 149define void @vld2_v4i16(ptr %src, ptr %dst) {150; CHECK-LABEL: vld2_v4i16:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vldrh.u16 q0, [r0]153; CHECK-NEXT: vrev32.16 q1, q0154; CHECK-NEXT: vadd.i32 q0, q0, q1155; CHECK-NEXT: vstrh.32 q0, [r1]156; CHECK-NEXT: bx lr157entry:158 %l1 = load <8 x i16>, ptr %src, align 2159 %s1 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>160 %s2 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>161 %a = add <4 x i16> %s1, %s2162 store <4 x i16> %a, ptr %dst163 ret void164}165 166define void @vld2_v8i16(ptr %src, ptr %dst) {167; CHECK-LABEL: vld2_v8i16:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: vld20.16 {q0, q1}, [r0]170; CHECK-NEXT: vld21.16 {q0, q1}, [r0]171; CHECK-NEXT: vadd.i16 q0, q0, q1172; CHECK-NEXT: vstrw.32 q0, [r1]173; CHECK-NEXT: bx lr174entry:175 %l1 = load <16 x i16>, ptr %src, align 2176 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>177 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>178 %a = add <8 x i16> %s1, %s2179 store <8 x i16> %a, ptr %dst180 ret void181}182 183define void @vld2_v16i16(ptr %src, ptr %dst) {184; CHECK-LABEL: vld2_v16i16:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: vld20.16 {q0, q1}, [r0]187; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!188; CHECK-NEXT: vld20.16 {q2, q3}, [r0]189; CHECK-NEXT: vadd.i16 q0, q0, q1190; CHECK-NEXT: vld21.16 {q2, q3}, [r0]191; CHECK-NEXT: vstrw.32 q0, [r1]192; CHECK-NEXT: vadd.i16 q1, q2, q3193; CHECK-NEXT: vstrw.32 q1, [r1, #16]194; CHECK-NEXT: bx lr195entry:196 %l1 = load <32 x i16>, ptr %src, align 2197 %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>198 %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>199 %a = add <16 x i16> %s1, %s2200 store <16 x i16> %a, ptr %dst201 ret void202}203 204define void @vld2_v8i16_align1(ptr %src, ptr %dst) {205; CHECK-LABEL: vld2_v8i16_align1:206; CHECK: @ %bb.0: @ %entry207; CHECK-NEXT: .pad #32208; CHECK-NEXT: sub sp, #32209; CHECK-NEXT: vldrb.u8 q0, [r0, #16]210; CHECK-NEXT: add r2, sp, #16211; CHECK-NEXT: vshr.u32 q1, q0, #16212; CHECK-NEXT: vstrh.32 q1, [r2, #8]213; CHECK-NEXT: vldrb.u8 q1, [r0]214; CHECK-NEXT: mov r0, sp215; CHECK-NEXT: vshr.u32 q2, q1, #16216; CHECK-NEXT: vstrh.32 q2, [r2]217; CHECK-NEXT: vstrh.32 q0, [r0, #8]218; CHECK-NEXT: vstrh.32 q1, [r0]219; CHECK-NEXT: vldrw.u32 q0, [r2]220; CHECK-NEXT: vldrw.u32 q1, [r0]221; CHECK-NEXT: vadd.i16 q0, q1, q0222; CHECK-NEXT: vstrw.32 q0, [r1]223; CHECK-NEXT: add sp, #32224; CHECK-NEXT: bx lr225entry:226 %l1 = load <16 x i16>, ptr %src, align 1227 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>228 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>229 %a = add <8 x i16> %s1, %s2230 store <8 x i16> %a, ptr %dst231 ret void232}233 234; i8235 236define void @vld2_v2i8(ptr %src, ptr %dst) {237; CHECK-LABEL: vld2_v2i8:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vldrb.u32 q0, [r0]240; CHECK-NEXT: vrev64.32 q1, q0241; CHECK-NEXT: vmov r2, s2242; CHECK-NEXT: vmov r0, s6243; CHECK-NEXT: add r0, r2244; CHECK-NEXT: strb r0, [r1, #1]245; CHECK-NEXT: vmov r0, s4246; CHECK-NEXT: vmov r2, s0247; CHECK-NEXT: add r0, r2248; CHECK-NEXT: strb r0, [r1]249; CHECK-NEXT: bx lr250entry:251 %l1 = load <4 x i8>, ptr %src, align 1252 %s1 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 0, i32 2>253 %s2 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 1, i32 3>254 %a = add <2 x i8> %s1, %s2255 store <2 x i8> %a, ptr %dst256 ret void257}258 259define void @vld2_v4i8(ptr %src, ptr %dst) {260; CHECK-LABEL: vld2_v4i8:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vldrb.u16 q0, [r0]263; CHECK-NEXT: vrev32.16 q1, q0264; CHECK-NEXT: vadd.i32 q0, q0, q1265; CHECK-NEXT: vstrb.32 q0, [r1]266; CHECK-NEXT: bx lr267entry:268 %l1 = load <8 x i8>, ptr %src, align 1269 %s1 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>270 %s2 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>271 %a = add <4 x i8> %s1, %s2272 store <4 x i8> %a, ptr %dst273 ret void274}275 276define void @vld2_v8i8(ptr %src, ptr %dst) {277; CHECK-LABEL: vld2_v8i8:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vldrb.u8 q0, [r0]280; CHECK-NEXT: vrev16.8 q1, q0281; CHECK-NEXT: vadd.i16 q0, q0, q1282; CHECK-NEXT: vstrb.16 q0, [r1]283; CHECK-NEXT: bx lr284entry:285 %l1 = load <16 x i8>, ptr %src, align 1286 %s1 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>287 %s2 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>288 %a = add <8 x i8> %s1, %s2289 store <8 x i8> %a, ptr %dst290 ret void291}292 293define void @vld2_v16i8(ptr %src, ptr %dst) {294; CHECK-LABEL: vld2_v16i8:295; CHECK: @ %bb.0: @ %entry296; CHECK-NEXT: vld20.8 {q0, q1}, [r0]297; CHECK-NEXT: vld21.8 {q0, q1}, [r0]298; CHECK-NEXT: vadd.i8 q0, q0, q1299; CHECK-NEXT: vstrw.32 q0, [r1]300; CHECK-NEXT: bx lr301entry:302 %l1 = load <32 x i8>, ptr %src, align 1303 %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>304 %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>305 %a = add <16 x i8> %s1, %s2306 store <16 x i8> %a, ptr %dst307 ret void308}309 310; i64311 312define void @vld2_v2i64(ptr %src, ptr %dst) {313; CHECK-LABEL: vld2_v2i64:314; CHECK: @ %bb.0: @ %entry315; CHECK-NEXT: .save {r4, r5, r6, lr}316; CHECK-NEXT: push {r4, r5, r6, lr}317; CHECK-NEXT: vldrw.u32 q0, [r0, #16]318; CHECK-NEXT: vmov lr, r12, d1319; CHECK-NEXT: vmov r3, r2, d0320; CHECK-NEXT: vldrw.u32 q0, [r0]321; CHECK-NEXT: vmov r0, r4, d1322; CHECK-NEXT: vmov r5, r6, d0323; CHECK-NEXT: adds.w r3, r3, lr324; CHECK-NEXT: adc.w r2, r2, r12325; CHECK-NEXT: adds r0, r0, r5326; CHECK-NEXT: adcs r6, r4327; CHECK-NEXT: vmov q0[2], q0[0], r0, r3328; CHECK-NEXT: vmov q0[3], q0[1], r6, r2329; CHECK-NEXT: vstrw.32 q0, [r1]330; CHECK-NEXT: pop {r4, r5, r6, pc}331entry:332 %l1 = load <4 x i64>, ptr %src, align 8333 %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>334 %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>335 %a = add <2 x i64> %s1, %s2336 store <2 x i64> %a, ptr %dst337 ret void338}339 340define void @vld2_v4i64(ptr %src, ptr %dst) {341; CHECK-LABEL: vld2_v4i64:342; CHECK: @ %bb.0: @ %entry343; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}344; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}345; CHECK-NEXT: .vsave {d8}346; CHECK-NEXT: vpush {d8}347; CHECK-NEXT: vldrw.u32 q0, [r0]348; CHECK-NEXT: vldrw.u32 q2, [r0, #16]349; CHECK-NEXT: vldrw.u32 q3, [r0, #32]350; CHECK-NEXT: vmov.f32 s4, s2351; CHECK-NEXT: vmov.f32 s5, s3352; CHECK-NEXT: vmov.f32 s2, s8353; CHECK-NEXT: vmov.f32 s3, s9354; CHECK-NEXT: vmov.f32 s16, s14355; CHECK-NEXT: vmov.f32 s17, s15356; CHECK-NEXT: vmov lr, r12, d5357; CHECK-NEXT: vldrw.u32 q2, [r0, #48]358; CHECK-NEXT: vmov r5, r6, d6359; CHECK-NEXT: vmov r2, r3, d1360; CHECK-NEXT: vmov.f32 s2, s8361; CHECK-NEXT: vmov r0, r7, d8362; CHECK-NEXT: vmov.f32 s3, s9363; CHECK-NEXT: adds.w lr, lr, r2364; CHECK-NEXT: adc.w r12, r12, r3365; CHECK-NEXT: vmov r3, r4, d5366; CHECK-NEXT: adds r0, r0, r5367; CHECK-NEXT: adc.w r8, r6, r7368; CHECK-NEXT: vmov r6, r5, d1369; CHECK-NEXT: vmov r2, r7, d0370; CHECK-NEXT: adds r3, r3, r6371; CHECK-NEXT: adc.w r6, r5, r4372; CHECK-NEXT: vmov r5, r4, d2373; CHECK-NEXT: vmov q1[2], q1[0], r0, r3374; CHECK-NEXT: vmov q1[3], q1[1], r8, r6375; CHECK-NEXT: vstrw.32 q1, [r1, #16]376; CHECK-NEXT: adds r2, r2, r5377; CHECK-NEXT: vmov q0[2], q0[0], r2, lr378; CHECK-NEXT: adc.w r0, r7, r4379; CHECK-NEXT: vmov q0[3], q0[1], r0, r12380; CHECK-NEXT: vstrw.32 q0, [r1]381; CHECK-NEXT: vpop {d8}382; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}383entry:384 %l1 = load <8 x i64>, ptr %src, align 8385 %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>386 %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>387 %a = add <4 x i64> %s1, %s2388 store <4 x i64> %a, ptr %dst389 ret void390}391 392; f32393 394define void @vld2_v2f32(ptr %src, ptr %dst) {395; CHECK-LABEL: vld2_v2f32:396; CHECK: @ %bb.0: @ %entry397; CHECK-NEXT: vldrw.u32 q0, [r0]398; CHECK-NEXT: vmov.f32 s4, s1399; CHECK-NEXT: vmov.f32 s5, s3400; CHECK-NEXT: vmov.f32 s1, s2401; CHECK-NEXT: vadd.f32 q0, q0, q1402; CHECK-NEXT: vstmia r1, {s0, s1}403; CHECK-NEXT: bx lr404entry:405 %l1 = load <4 x float>, ptr %src, align 4406 %s1 = shufflevector <4 x float> %l1, <4 x float> undef, <2 x i32> <i32 0, i32 2>407 %s2 = shufflevector <4 x float> %l1, <4 x float> undef, <2 x i32> <i32 1, i32 3>408 %a = fadd <2 x float> %s1, %s2409 store <2 x float> %a, ptr %dst410 ret void411}412 413define void @vld2_v4f32(ptr %src, ptr %dst) {414; CHECK-LABEL: vld2_v4f32:415; CHECK: @ %bb.0: @ %entry416; CHECK-NEXT: vld20.32 {q0, q1}, [r0]417; CHECK-NEXT: vld21.32 {q0, q1}, [r0]418; CHECK-NEXT: vadd.f32 q0, q0, q1419; CHECK-NEXT: vstrw.32 q0, [r1]420; CHECK-NEXT: bx lr421entry:422 %l1 = load <8 x float>, ptr %src, align 4423 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>424 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>425 %a = fadd <4 x float> %s1, %s2426 store <4 x float> %a, ptr %dst427 ret void428}429 430define void @vld2_v8f32(ptr %src, ptr %dst) {431; CHECK-LABEL: vld2_v8f32:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vld20.32 {q0, q1}, [r0]434; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!435; CHECK-NEXT: vld20.32 {q2, q3}, [r0]436; CHECK-NEXT: vadd.f32 q0, q0, q1437; CHECK-NEXT: vld21.32 {q2, q3}, [r0]438; CHECK-NEXT: vstrw.32 q0, [r1]439; CHECK-NEXT: vadd.f32 q1, q2, q3440; CHECK-NEXT: vstrw.32 q1, [r1, #16]441; CHECK-NEXT: bx lr442entry:443 %l1 = load <16 x float>, ptr %src, align 4444 %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>445 %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>446 %a = fadd <8 x float> %s1, %s2447 store <8 x float> %a, ptr %dst448 ret void449}450 451define void @vld2_v16f32(ptr %src, ptr %dst) {452; CHECK-LABEL: vld2_v16f32:453; CHECK: @ %bb.0: @ %entry454; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}455; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}456; CHECK-NEXT: vld20.32 {q0, q1}, [r0]457; CHECK-NEXT: add.w r2, r0, #96458; CHECK-NEXT: add.w r3, r0, #64459; CHECK-NEXT: vld20.32 {q3, q4}, [r2]460; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!461; CHECK-NEXT: vld21.32 {q3, q4}, [r2]462; CHECK-NEXT: vld20.32 {q5, q6}, [r0]463; CHECK-NEXT: vadd.f32 q0, q0, q1464; CHECK-NEXT: vld20.32 {q1, q2}, [r3]465; CHECK-NEXT: vadd.f32 q3, q3, q4466; CHECK-NEXT: vld21.32 {q5, q6}, [r0]467; CHECK-NEXT: vld21.32 {q1, q2}, [r3]468; CHECK-NEXT: vstrw.32 q3, [r1, #48]469; CHECK-NEXT: vadd.f32 q5, q5, q6470; CHECK-NEXT: vstrw.32 q0, [r1]471; CHECK-NEXT: vadd.f32 q1, q1, q2472; CHECK-NEXT: vstrw.32 q5, [r1, #16]473; CHECK-NEXT: vstrw.32 q1, [r1, #32]474; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}475; CHECK-NEXT: bx lr476entry:477 %l1 = load <32 x float>, ptr %src, align 4478 %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>479 %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>480 %a = fadd <16 x float> %s1, %s2481 store <16 x float> %a, ptr %dst482 ret void483}484 485define void @vld2_v4f32_align1(ptr %src, ptr %dst) {486; CHECK-LABEL: vld2_v4f32_align1:487; CHECK: @ %bb.0: @ %entry488; CHECK-NEXT: vldrb.u8 q0, [r0, #16]489; CHECK-NEXT: vldrb.u8 q1, [r0]490; CHECK-NEXT: vmov.f32 s8, s5491; CHECK-NEXT: vmov.f32 s9, s7492; CHECK-NEXT: vmov.f32 s5, s6493; CHECK-NEXT: vmov.f32 s10, s1494; CHECK-NEXT: vmov.f32 s11, s3495; CHECK-NEXT: vmov.f32 s6, s0496; CHECK-NEXT: vmov.f32 s7, s2497; CHECK-NEXT: vadd.f32 q0, q1, q2498; CHECK-NEXT: vstrw.32 q0, [r1]499; CHECK-NEXT: bx lr500entry:501 %l1 = load <8 x float>, ptr %src, align 1502 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>503 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>504 %a = fadd <4 x float> %s1, %s2505 store <4 x float> %a, ptr %dst506 ret void507}508 509; f16510 511define void @vld2_v2f16(ptr %src, ptr %dst) {512; CHECK-LABEL: vld2_v2f16:513; CHECK: @ %bb.0: @ %entry514; CHECK-NEXT: ldr r2, [r0]515; CHECK-NEXT: ldr r0, [r0, #4]516; CHECK-NEXT: vmov.32 q0[0], r2517; CHECK-NEXT: vmov q1, q0518; CHECK-NEXT: vmov.32 q1[1], r0519; CHECK-NEXT: vmovx.f16 s4, s0520; CHECK-NEXT: vmovx.f16 s2, s5521; CHECK-NEXT: vins.f16 s4, s2522; CHECK-NEXT: vins.f16 s0, s5523; CHECK-NEXT: vadd.f16 q0, q0, q1524; CHECK-NEXT: vmov r0, s0525; CHECK-NEXT: str r0, [r1]526; CHECK-NEXT: bx lr527entry:528 %l1 = load <4 x half>, ptr %src, align 2529 %s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2>530 %s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3>531 %a = fadd <2 x half> %s1, %s2532 store <2 x half> %a, ptr %dst533 ret void534}535 536define void @vld2_v4f16(ptr %src, ptr %dst) {537; CHECK-LABEL: vld2_v4f16:538; CHECK: @ %bb.0: @ %entry539; CHECK-NEXT: vldrh.u16 q0, [r0]540; CHECK-NEXT: vmovx.f16 s4, s0541; CHECK-NEXT: vmovx.f16 s6, s1542; CHECK-NEXT: vins.f16 s4, s6543; CHECK-NEXT: vmovx.f16 s5, s2544; CHECK-NEXT: vmovx.f16 s6, s3545; CHECK-NEXT: vins.f16 s2, s3546; CHECK-NEXT: vins.f16 s0, s1547; CHECK-NEXT: vins.f16 s5, s6548; CHECK-NEXT: vmov.f32 s1, s2549; CHECK-NEXT: vadd.f16 q0, q0, q1550; CHECK-NEXT: vmov r0, r2, d0551; CHECK-NEXT: strd r0, r2, [r1]552; CHECK-NEXT: bx lr553entry:554 %l1 = load <8 x half>, ptr %src, align 2555 %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>556 %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>557 %a = fadd <4 x half> %s1, %s2558 store <4 x half> %a, ptr %dst559 ret void560}561 562define void @vld2_v8f16(ptr %src, ptr %dst) {563; CHECK-LABEL: vld2_v8f16:564; CHECK: @ %bb.0: @ %entry565; CHECK-NEXT: vld20.16 {q0, q1}, [r0]566; CHECK-NEXT: vld21.16 {q0, q1}, [r0]567; CHECK-NEXT: vadd.f16 q0, q0, q1568; CHECK-NEXT: vstrw.32 q0, [r1]569; CHECK-NEXT: bx lr570entry:571 %l1 = load <16 x half>, ptr %src, align 2572 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>573 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>574 %a = fadd <8 x half> %s1, %s2575 store <8 x half> %a, ptr %dst576 ret void577}578 579define void @vld2_v16f16(ptr %src, ptr %dst) {580; CHECK-LABEL: vld2_v16f16:581; CHECK: @ %bb.0: @ %entry582; CHECK-NEXT: vld20.16 {q0, q1}, [r0]583; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!584; CHECK-NEXT: vld20.16 {q2, q3}, [r0]585; CHECK-NEXT: vadd.f16 q0, q0, q1586; CHECK-NEXT: vld21.16 {q2, q3}, [r0]587; CHECK-NEXT: vstrw.32 q0, [r1]588; CHECK-NEXT: vadd.f16 q2, q2, q3589; CHECK-NEXT: vstrw.32 q2, [r1, #16]590; CHECK-NEXT: bx lr591entry:592 %l1 = load <32 x half>, ptr %src, align 2593 %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>594 %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>595 %a = fadd <16 x half> %s1, %s2596 store <16 x half> %a, ptr %dst597 ret void598}599 600define void @vld2_v8f16_align1(ptr %src, ptr %dst) {601; CHECK-LABEL: vld2_v8f16_align1:602; CHECK: @ %bb.0: @ %entry603; CHECK-NEXT: vldrb.u8 q0, [r0]604; CHECK-NEXT: vldrb.u8 q2, [r0, #16]605; CHECK-NEXT: vmovx.f16 s4, s0606; CHECK-NEXT: vmovx.f16 s6, s1607; CHECK-NEXT: vins.f16 s4, s6608; CHECK-NEXT: vmovx.f16 s5, s2609; CHECK-NEXT: vmovx.f16 s6, s3610; CHECK-NEXT: vmovx.f16 s12, s9611; CHECK-NEXT: vins.f16 s5, s6612; CHECK-NEXT: vmovx.f16 s6, s8613; CHECK-NEXT: vins.f16 s6, s12614; CHECK-NEXT: vmovx.f16 s7, s10615; CHECK-NEXT: vmovx.f16 s12, s11616; CHECK-NEXT: vins.f16 s2, s3617; CHECK-NEXT: vins.f16 s10, s11618; CHECK-NEXT: vins.f16 s8, s9619; CHECK-NEXT: vins.f16 s0, s1620; CHECK-NEXT: vmov.f32 s1, s2621; CHECK-NEXT: vins.f16 s7, s12622; CHECK-NEXT: vmov.f32 s2, s8623; CHECK-NEXT: vmov.f32 s3, s10624; CHECK-NEXT: vadd.f16 q0, q0, q1625; CHECK-NEXT: vstrw.32 q0, [r1]626; CHECK-NEXT: bx lr627entry:628 %l1 = load <16 x half>, ptr %src, align 1629 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>630 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>631 %a = fadd <8 x half> %s1, %s2632 store <8 x half> %a, ptr %dst633 ret void634}635 636; f64637 638define void @vld2_v2f64(ptr %src, ptr %dst) {639; CHECK-LABEL: vld2_v2f64:640; CHECK: @ %bb.0: @ %entry641; CHECK-NEXT: vldrw.u32 q0, [r0, #16]642; CHECK-NEXT: vldrw.u32 q1, [r0]643; CHECK-NEXT: vadd.f64 d1, d0, d1644; CHECK-NEXT: vadd.f64 d0, d2, d3645; CHECK-NEXT: vstrw.32 q0, [r1]646; CHECK-NEXT: bx lr647entry:648 %l1 = load <4 x double>, ptr %src, align 8649 %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>650 %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>651 %a = fadd <2 x double> %s1, %s2652 store <2 x double> %a, ptr %dst653 ret void654}655 656define void @vld2_v4f64(ptr %src, ptr %dst) {657; CHECK-LABEL: vld2_v4f64:658; CHECK: @ %bb.0: @ %entry659; CHECK-NEXT: vldrw.u32 q0, [r0, #48]660; CHECK-NEXT: vldrw.u32 q1, [r0, #32]661; CHECK-NEXT: vldrw.u32 q2, [r0]662; CHECK-NEXT: vadd.f64 d1, d0, d1663; CHECK-NEXT: vadd.f64 d0, d2, d3664; CHECK-NEXT: vldrw.u32 q1, [r0, #16]665; CHECK-NEXT: vadd.f64 d3, d2, d3666; CHECK-NEXT: vstrw.32 q0, [r1, #16]667; CHECK-NEXT: vadd.f64 d2, d4, d5668; CHECK-NEXT: vstrw.32 q1, [r1]669; CHECK-NEXT: bx lr670entry:671 %l1 = load <8 x double>, ptr %src, align 8672 %s1 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>673 %s2 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>674 %a = fadd <4 x double> %s1, %s2675 store <4 x double> %a, ptr %dst676 ret void677}678