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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-LV3; RUN: llc -early-live-intervals -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-LIS4 5; i326 7define void @vld3_v2i32(ptr %src, ptr %dst) {8; CHECK-LABEL: vld3_v2i32:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: .save {r7, lr}11; CHECK-NEXT: push {r7, lr}12; CHECK-NEXT: vldrw.u32 q0, [r0]13; CHECK-NEXT: ldrd r0, r2, [r0, #16]14; CHECK-NEXT: vmov.f32 s6, s315; CHECK-NEXT: vmov r12, lr, d016; CHECK-NEXT: vmov r3, s617; CHECK-NEXT: add r0, r318; CHECK-NEXT: add.w r3, r12, lr19; CHECK-NEXT: add r0, r220; CHECK-NEXT: vmov r2, s221; CHECK-NEXT: add r2, r322; CHECK-NEXT: strd r2, r0, [r1]23; CHECK-NEXT: pop {r7, pc}24entry:25 %l1 = load <6 x i32>, ptr %src, align 426 %s1 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 0, i32 3>27 %s2 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 1, i32 4>28 %s3 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 2, i32 5>29 %a1 = add <2 x i32> %s1, %s230 %a = add <2 x i32> %a1, %s331 store <2 x i32> %a, ptr %dst32 ret void33}34 35define void @vld3_v4i32(ptr %src, ptr %dst) {36; CHECK-LABEL: vld3_v4i32:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: .vsave {d8, d9}39; CHECK-NEXT: vpush {d8, d9}40; CHECK-NEXT: vldrw.u32 q0, [r0, #16]41; CHECK-NEXT: vldrw.u32 q1, [r0]42; CHECK-NEXT: vldrw.u32 q4, [r0, #32]43; CHECK-NEXT: vmov.f32 s10, s244; CHECK-NEXT: vmov.f32 s13, s045; CHECK-NEXT: vmov.f32 s14, s346; CHECK-NEXT: vmov.f32 s8, s447; CHECK-NEXT: vmov.f32 s9, s748; CHECK-NEXT: vmov.f32 s12, s549; CHECK-NEXT: vmov.f32 s15, s1850; CHECK-NEXT: vmov.f32 s11, s1751; CHECK-NEXT: vadd.i32 q2, q2, q352; CHECK-NEXT: vmov.f32 s0, s653; CHECK-NEXT: vmov.f32 s2, s1654; CHECK-NEXT: vmov.f32 s3, s1955; CHECK-NEXT: vadd.i32 q0, q2, q056; CHECK-NEXT: vstrw.32 q0, [r1]57; CHECK-NEXT: vpop {d8, d9}58; CHECK-NEXT: bx lr59 60entry:61 %l1 = load <12 x i32>, ptr %src, align 462 %s1 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>63 %s2 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>64 %s3 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>65 %a1 = add <4 x i32> %s1, %s266 %a = add <4 x i32> %a1, %s367 store <4 x i32> %a, ptr %dst68 ret void69}70 71define void @vld3_v8i32(ptr %src, ptr %dst) {72; CHECK-LABEL: vld3_v8i32:73; CHECK: @ %bb.0: @ %entry74; CHECK-NEXT: .vsave {d8, d9, d10, d11}75; CHECK-NEXT: vpush {d8, d9, d10, d11}76; CHECK-NEXT: vldrw.u32 q0, [r0, #64]77; CHECK-NEXT: vldrw.u32 q1, [r0, #48]78; CHECK-NEXT: vldrw.u32 q4, [r0, #80]79; CHECK-NEXT: vmov.f32 s10, s280; CHECK-NEXT: vmov.f32 s13, s081; CHECK-NEXT: vmov.f32 s14, s382; CHECK-NEXT: vmov.f32 s8, s483; CHECK-NEXT: vmov.f32 s9, s784; CHECK-NEXT: vmov.f32 s12, s585; CHECK-NEXT: vmov.f32 s15, s1886; CHECK-NEXT: vmov.f32 s11, s1787; CHECK-NEXT: vadd.i32 q2, q2, q388; CHECK-NEXT: vmov.f32 s0, s689; CHECK-NEXT: vmov.f32 s2, s1690; CHECK-NEXT: vldrw.u32 q1, [r0, #16]91; CHECK-NEXT: vmov.f32 s3, s1992; CHECK-NEXT: vldrw.u32 q3, [r0, #32]93; CHECK-NEXT: vadd.i32 q0, q2, q094; CHECK-NEXT: vldrw.u32 q2, [r0]95; CHECK-NEXT: vmov.f32 s17, s496; CHECK-NEXT: vstrw.32 q0, [r1, #16]97; CHECK-NEXT: vmov.f32 s18, s798; CHECK-NEXT: vmov.f32 s22, s699; CHECK-NEXT: vmov.f32 s16, s9100; CHECK-NEXT: vmov.f32 s19, s14101; CHECK-NEXT: vmov.f32 s20, s8102; CHECK-NEXT: vmov.f32 s21, s11103; CHECK-NEXT: vmov.f32 s23, s13104; CHECK-NEXT: vadd.i32 q4, q5, q4105; CHECK-NEXT: vmov.f32 s4, s10106; CHECK-NEXT: vmov.f32 s6, s12107; CHECK-NEXT: vmov.f32 s7, s15108; CHECK-NEXT: vadd.i32 q1, q4, q1109; CHECK-NEXT: vstrw.32 q1, [r1]110; CHECK-NEXT: vpop {d8, d9, d10, d11}111; CHECK-NEXT: bx lr112 113entry:114 %l1 = load <24 x i32>, ptr %src, align 4115 %s1 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>116 %s2 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>117 %s3 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>118 %a1 = add <8 x i32> %s1, %s2119 %a = add <8 x i32> %a1, %s3120 store <8 x i32> %a, ptr %dst121 ret void122}123 124define void @vld3_v16i32(ptr %src, ptr %dst) {125; CHECK-LABEL: vld3_v16i32:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}128; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}129; CHECK-NEXT: vldrw.u32 q0, [r0, #64]130; CHECK-NEXT: vldrw.u32 q1, [r0, #48]131; CHECK-NEXT: vldrw.u32 q4, [r0, #80]132; CHECK-NEXT: vldrw.u32 q6, [r0, #176]133; CHECK-NEXT: vmov.f32 s10, s2134; CHECK-NEXT: vmov.f32 s13, s0135; CHECK-NEXT: vmov.f32 s14, s3136; CHECK-NEXT: vmov.f32 s8, s4137; CHECK-NEXT: vmov.f32 s9, s7138; CHECK-NEXT: vmov.f32 s12, s5139; CHECK-NEXT: vmov.f32 s15, s18140; CHECK-NEXT: vmov.f32 s11, s17141; CHECK-NEXT: vadd.i32 q2, q2, q3142; CHECK-NEXT: vmov.f32 s0, s6143; CHECK-NEXT: vmov.f32 s2, s16144; CHECK-NEXT: vldrw.u32 q1, [r0, #16]145; CHECK-NEXT: vmov.f32 s3, s19146; CHECK-NEXT: vldrw.u32 q3, [r0, #32]147; CHECK-NEXT: vadd.i32 q0, q2, q0148; CHECK-NEXT: vldrw.u32 q2, [r0]149; CHECK-NEXT: vmov.f32 s17, s4150; CHECK-NEXT: vmov.f32 s18, s7151; CHECK-NEXT: vmov.f32 s22, s6152; CHECK-NEXT: vmov.f32 s16, s9153; CHECK-NEXT: vmov.f32 s19, s14154; CHECK-NEXT: vmov.f32 s20, s8155; CHECK-NEXT: vmov.f32 s21, s11156; CHECK-NEXT: vmov.f32 s23, s13157; CHECK-NEXT: vmov.f32 s4, s10158; CHECK-NEXT: vldrw.u32 q2, [r0, #160]159; CHECK-NEXT: vmov.f32 s6, s12160; CHECK-NEXT: vadd.i32 q4, q5, q4161; CHECK-NEXT: vmov.f32 s7, s15162; CHECK-NEXT: vldrw.u32 q3, [r0, #144]163; CHECK-NEXT: vadd.i32 q1, q4, q1164; CHECK-NEXT: vmov.f32 s18, s10165; CHECK-NEXT: vmov.f32 s21, s8166; CHECK-NEXT: vmov.f32 s22, s11167; CHECK-NEXT: vmov.f32 s16, s12168; CHECK-NEXT: vmov.f32 s17, s15169; CHECK-NEXT: vmov.f32 s20, s13170; CHECK-NEXT: vmov.f32 s23, s26171; CHECK-NEXT: vmov.f32 s19, s25172; CHECK-NEXT: vadd.i32 q4, q4, q5173; CHECK-NEXT: vmov.f32 s8, s14174; CHECK-NEXT: vmov.f32 s10, s24175; CHECK-NEXT: vldrw.u32 q3, [r0, #112]176; CHECK-NEXT: vmov.f32 s11, s27177; CHECK-NEXT: vldrw.u32 q5, [r0, #128]178; CHECK-NEXT: vadd.i32 q2, q4, q2179; CHECK-NEXT: vldrw.u32 q4, [r0, #96]180; CHECK-NEXT: vmov.f32 s25, s12181; CHECK-NEXT: vstrw.32 q2, [r1, #48]182; CHECK-NEXT: vmov.f32 s26, s15183; CHECK-NEXT: vstrw.32 q0, [r1, #16]184; CHECK-NEXT: vmov.f32 s30, s14185; CHECK-NEXT: vstrw.32 q1, [r1]186; CHECK-NEXT: vmov.f32 s24, s17187; CHECK-NEXT: vmov.f32 s27, s22188; CHECK-NEXT: vmov.f32 s28, s16189; CHECK-NEXT: vmov.f32 s29, s19190; CHECK-NEXT: vmov.f32 s31, s21191; CHECK-NEXT: vadd.i32 q6, q7, q6192; CHECK-NEXT: vmov.f32 s12, s18193; CHECK-NEXT: vmov.f32 s14, s20194; CHECK-NEXT: vmov.f32 s15, s23195; CHECK-NEXT: vadd.i32 q3, q6, q3196; CHECK-NEXT: vstrw.32 q3, [r1, #32]197; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}198; CHECK-NEXT: bx lr199 200entry:201 %l1 = load <48 x i32>, ptr %src, align 4202 %s1 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>203 %s2 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>204 %s3 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>205 %a1 = add <16 x i32> %s1, %s2206 %a = add <16 x i32> %a1, %s3207 store <16 x i32> %a, ptr %dst208 ret void209}210 211; i16212 213define void @vld3_v2i16(ptr %src, ptr %dst) {214; CHECK-LABEL: vld3_v2i16:215; CHECK: @ %bb.0: @ %entry216; CHECK-NEXT: .pad #8217; CHECK-NEXT: sub sp, #8218; CHECK-NEXT: vldrh.u32 q0, [r0]219; CHECK-NEXT: ldr r2, [r0, #8]220; CHECK-NEXT: mov r3, sp221; CHECK-NEXT: str r2, [sp]222; CHECK-NEXT: vmov.f32 s6, s3223; CHECK-NEXT: vmov.f32 s8, s1224; CHECK-NEXT: vmov r0, s6225; CHECK-NEXT: vldrh.u32 q1, [r3]226; CHECK-NEXT: vmov.f32 s6, s4227; CHECK-NEXT: vmov.f32 s4, s2228; CHECK-NEXT: vmov.f32 s2, s5229; CHECK-NEXT: vmov r2, s6230; CHECK-NEXT: add r0, r2231; CHECK-NEXT: vmov r2, s2232; CHECK-NEXT: add r0, r2233; CHECK-NEXT: strh r0, [r1, #2]234; CHECK-NEXT: vmov r0, s8235; CHECK-NEXT: vmov r2, s0236; CHECK-NEXT: add r0, r2237; CHECK-NEXT: vmov r2, s4238; CHECK-NEXT: add r0, r2239; CHECK-NEXT: strh r0, [r1]240; CHECK-NEXT: add sp, #8241; CHECK-NEXT: bx lr242entry:243 %l1 = load <6 x i16>, ptr %src, align 4244 %s1 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 0, i32 3>245 %s2 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 1, i32 4>246 %s3 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 2, i32 5>247 %a1 = add <2 x i16> %s1, %s2248 %a = add <2 x i16> %a1, %s3249 store <2 x i16> %a, ptr %dst250 ret void251}252 253define void @vld3_v4i16(ptr %src, ptr %dst) {254; CHECK-LABEL: vld3_v4i16:255; CHECK: @ %bb.0: @ %entry256; CHECK-NEXT: .save {r4, r5, r6, lr}257; CHECK-NEXT: push {r4, r5, r6, lr}258; CHECK-NEXT: vldrw.u32 q0, [r0]259; CHECK-NEXT: vldrh.u32 q1, [r0, #16]260; CHECK-NEXT: vmov.u16 r5, q0[6]261; CHECK-NEXT: vmov.u16 r6, q0[0]262; CHECK-NEXT: vmov r0, r3, d2263; CHECK-NEXT: vmov.u16 lr, q0[2]264; CHECK-NEXT: vmov r2, r4, d3265; CHECK-NEXT: vmov q1[2], q1[0], r6, r5266; CHECK-NEXT: vmov.u16 r5, q0[7]267; CHECK-NEXT: vmov.u16 r6, q0[1]268; CHECK-NEXT: vmov q2[2], q2[0], r6, r5269; CHECK-NEXT: vmov.u16 r5, q0[3]270; CHECK-NEXT: vmov.u16 r6, q0[4]271; CHECK-NEXT: vmov q1[3], q1[1], r5, r3272; CHECK-NEXT: vmov q2[3], q2[1], r6, r2273; CHECK-NEXT: vmov.u16 r12, q0[5]274; CHECK-NEXT: vadd.i32 q0, q1, q2275; CHECK-NEXT: vmov q1[2], q1[0], lr, r0276; CHECK-NEXT: vmov q1[3], q1[1], r12, r4277; CHECK-NEXT: vadd.i32 q0, q0, q1278; CHECK-NEXT: vstrh.32 q0, [r1]279; CHECK-NEXT: pop {r4, r5, r6, pc}280entry:281 %l1 = load <12 x i16>, ptr %src, align 4282 %s1 = shufflevector <12 x i16> %l1, <12 x i16> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>283 %s2 = shufflevector <12 x i16> %l1, <12 x i16> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>284 %s3 = shufflevector <12 x i16> %l1, <12 x i16> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>285 %a1 = add <4 x i16> %s1, %s2286 %a = add <4 x i16> %a1, %s3287 store <4 x i16> %a, ptr %dst288 ret void289}290 291define void @vld3_v8i16(ptr %src, ptr %dst) {292; CHECK-LABEL: vld3_v8i16:293; CHECK: @ %bb.0: @ %entry294; CHECK-NEXT: .vsave {d8, d9}295; CHECK-NEXT: vpush {d8, d9}296; CHECK-NEXT: vldrw.u32 q0, [r0]297; CHECK-NEXT: vldrw.u32 q2, [r0, #16]298; CHECK-NEXT: vldrw.u32 q3, [r0, #32]299; CHECK-NEXT: vmovx.f16 s6, s2300; CHECK-NEXT: vmov.f32 s4, s1301; CHECK-NEXT: vins.f16 s4, s6302; CHECK-NEXT: vmovx.f16 s6, s9303; CHECK-NEXT: vmov.f32 s5, s8304; CHECK-NEXT: vmovx.f16 s7, s12305; CHECK-NEXT: vins.f16 s5, s6306; CHECK-NEXT: vmov.f32 s6, s11307; CHECK-NEXT: vins.f16 s6, s7308; CHECK-NEXT: vmovx.f16 s16, s15309; CHECK-NEXT: vmov.f32 s7, s14310; CHECK-NEXT: vmovx.f16 s17, s3311; CHECK-NEXT: vins.f16 s7, s16312; CHECK-NEXT: vmovx.f16 s16, s0313; CHECK-NEXT: vins.f16 s16, s2314; CHECK-NEXT: vmovx.f16 s2, s1315; CHECK-NEXT: vins.f16 s0, s2316; CHECK-NEXT: vmovx.f16 s2, s8317; CHECK-NEXT: vins.f16 s3, s2318; CHECK-NEXT: vmovx.f16 s2, s11319; CHECK-NEXT: vmovx.f16 s18, s10320; CHECK-NEXT: vins.f16 s10, s2321; CHECK-NEXT: vmovx.f16 s2, s14322; CHECK-NEXT: vmovx.f16 s19, s13323; CHECK-NEXT: vins.f16 s13, s2324; CHECK-NEXT: vmov.f32 s1, s3325; CHECK-NEXT: vins.f16 s18, s12326; CHECK-NEXT: vins.f16 s19, s15327; CHECK-NEXT: vins.f16 s17, s9328; CHECK-NEXT: vmov.f32 s2, s10329; CHECK-NEXT: vmov.f32 s3, s13330; CHECK-NEXT: vadd.i16 q0, q0, q4331; CHECK-NEXT: vadd.i16 q0, q0, q1332; CHECK-NEXT: vstrw.32 q0, [r1]333; CHECK-NEXT: vpop {d8, d9}334; CHECK-NEXT: bx lr335entry:336 %l1 = load <24 x i16>, ptr %src, align 4337 %s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>338 %s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>339 %s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>340 %a1 = add <8 x i16> %s1, %s2341 %a = add <8 x i16> %a1, %s3342 store <8 x i16> %a, ptr %dst343 ret void344}345 346define void @vld3_v16i16(ptr %src, ptr %dst) {347; CHECK-LV-LABEL: vld3_v16i16:348; CHECK-LV: @ %bb.0: @ %entry349; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11}350; CHECK-LV-NEXT: vpush {d8, d9, d10, d11}351; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #48]352; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #64]353; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #80]354; CHECK-LV-NEXT: vmovx.f16 s6, s2355; CHECK-LV-NEXT: vmov.f32 s4, s1356; CHECK-LV-NEXT: vins.f16 s4, s6357; CHECK-LV-NEXT: vmovx.f16 s6, s9358; CHECK-LV-NEXT: vmov.f32 s5, s8359; CHECK-LV-NEXT: vmovx.f16 s7, s12360; CHECK-LV-NEXT: vins.f16 s5, s6361; CHECK-LV-NEXT: vmov.f32 s6, s11362; CHECK-LV-NEXT: vins.f16 s6, s7363; CHECK-LV-NEXT: vmovx.f16 s16, s15364; CHECK-LV-NEXT: vmov.f32 s7, s14365; CHECK-LV-NEXT: vmovx.f16 s17, s3366; CHECK-LV-NEXT: vins.f16 s7, s16367; CHECK-LV-NEXT: vmovx.f16 s16, s0368; CHECK-LV-NEXT: vins.f16 s16, s2369; CHECK-LV-NEXT: vmovx.f16 s2, s1370; CHECK-LV-NEXT: vins.f16 s0, s2371; CHECK-LV-NEXT: vmovx.f16 s2, s8372; CHECK-LV-NEXT: vins.f16 s3, s2373; CHECK-LV-NEXT: vmovx.f16 s2, s11374; CHECK-LV-NEXT: vmovx.f16 s18, s10375; CHECK-LV-NEXT: vins.f16 s10, s2376; CHECK-LV-NEXT: vmovx.f16 s2, s14377; CHECK-LV-NEXT: vmovx.f16 s19, s13378; CHECK-LV-NEXT: vins.f16 s13, s2379; CHECK-LV-NEXT: vmov.f32 s1, s3380; CHECK-LV-NEXT: vins.f16 s18, s12381; CHECK-LV-NEXT: vins.f16 s19, s15382; CHECK-LV-NEXT: vins.f16 s17, s9383; CHECK-LV-NEXT: vmov.f32 s2, s10384; CHECK-LV-NEXT: vmov.f32 s3, s13385; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #16]386; CHECK-LV-NEXT: vadd.i16 q0, q0, q4387; CHECK-LV-NEXT: vldrw.u32 q4, [r0]388; CHECK-LV-NEXT: vadd.i16 q0, q0, q1389; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #32]390; CHECK-LV-NEXT: vmovx.f16 s14, s10391; CHECK-LV-NEXT: vmov.f32 s22, s11392; CHECK-LV-NEXT: vins.f16 s14, s4393; CHECK-LV-NEXT: vmovx.f16 s4, s4394; CHECK-LV-NEXT: vmovx.f16 s15, s5395; CHECK-LV-NEXT: vins.f16 s22, s4396; CHECK-LV-NEXT: vmovx.f16 s4, s7397; CHECK-LV-NEXT: vins.f16 s15, s7398; CHECK-LV-NEXT: vmovx.f16 s7, s6399; CHECK-LV-NEXT: vins.f16 s6, s4400; CHECK-LV-NEXT: vmovx.f16 s4, s17401; CHECK-LV-NEXT: vmovx.f16 s12, s16402; CHECK-LV-NEXT: vins.f16 s16, s4403; CHECK-LV-NEXT: vmovx.f16 s4, s8404; CHECK-LV-NEXT: vmovx.f16 s13, s19405; CHECK-LV-NEXT: vins.f16 s19, s4406; CHECK-LV-NEXT: vmovx.f16 s4, s11407; CHECK-LV-NEXT: vins.f16 s12, s18408; CHECK-LV-NEXT: vmov.f32 s20, s17409; CHECK-LV-NEXT: vmovx.f16 s18, s18410; CHECK-LV-NEXT: vins.f16 s10, s4411; CHECK-LV-NEXT: vins.f16 s5, s7412; CHECK-LV-NEXT: vins.f16 s13, s9413; CHECK-LV-NEXT: vins.f16 s20, s18414; CHECK-LV-NEXT: vmov.f32 s17, s19415; CHECK-LV-NEXT: vmovx.f16 s9, s9416; CHECK-LV-NEXT: vmov.f32 s21, s8417; CHECK-LV-NEXT: vstrw.32 q0, [r1, #16]418; CHECK-LV-NEXT: vmov.f32 s18, s10419; CHECK-LV-NEXT: vins.f16 s21, s9420; CHECK-LV-NEXT: vmov.f32 s19, s5421; CHECK-LV-NEXT: vmov.f32 s23, s6422; CHECK-LV-NEXT: vadd.i16 q1, q4, q3423; CHECK-LV-NEXT: vadd.i16 q1, q1, q5424; CHECK-LV-NEXT: vstrw.32 q1, [r1]425; CHECK-LV-NEXT: vpop {d8, d9, d10, d11}426; CHECK-LV-NEXT: bx lr427;428; CHECK-LIS-LABEL: vld3_v16i16:429; CHECK-LIS: @ %bb.0: @ %entry430; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11}431; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11}432; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #48]433; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #64]434; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #80]435; CHECK-LIS-NEXT: vmovx.f16 s6, s2436; CHECK-LIS-NEXT: vmov.f32 s4, s1437; CHECK-LIS-NEXT: vins.f16 s4, s6438; CHECK-LIS-NEXT: vmovx.f16 s6, s9439; CHECK-LIS-NEXT: vmov.f32 s5, s8440; CHECK-LIS-NEXT: vmovx.f16 s7, s12441; CHECK-LIS-NEXT: vins.f16 s5, s6442; CHECK-LIS-NEXT: vmov.f32 s6, s11443; CHECK-LIS-NEXT: vins.f16 s6, s7444; CHECK-LIS-NEXT: vmovx.f16 s16, s15445; CHECK-LIS-NEXT: vmov.f32 s7, s14446; CHECK-LIS-NEXT: vmovx.f16 s17, s3447; CHECK-LIS-NEXT: vins.f16 s7, s16448; CHECK-LIS-NEXT: vmovx.f16 s16, s0449; CHECK-LIS-NEXT: vins.f16 s16, s2450; CHECK-LIS-NEXT: vmovx.f16 s2, s1451; CHECK-LIS-NEXT: vins.f16 s0, s2452; CHECK-LIS-NEXT: vmovx.f16 s2, s8453; CHECK-LIS-NEXT: vins.f16 s3, s2454; CHECK-LIS-NEXT: vmovx.f16 s2, s11455; CHECK-LIS-NEXT: vmovx.f16 s18, s10456; CHECK-LIS-NEXT: vins.f16 s10, s2457; CHECK-LIS-NEXT: vmovx.f16 s2, s14458; CHECK-LIS-NEXT: vmovx.f16 s19, s13459; CHECK-LIS-NEXT: vins.f16 s13, s2460; CHECK-LIS-NEXT: vmov.f32 s1, s3461; CHECK-LIS-NEXT: vins.f16 s18, s12462; CHECK-LIS-NEXT: vins.f16 s19, s15463; CHECK-LIS-NEXT: vmov.f32 s3, s13464; CHECK-LIS-NEXT: vins.f16 s17, s9465; CHECK-LIS-NEXT: vmov.f32 s2, s10466; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #16]467; CHECK-LIS-NEXT: vadd.i16 q0, q0, q4468; CHECK-LIS-NEXT: vldrw.u32 q4, [r0]469; CHECK-LIS-NEXT: vadd.i16 q0, q0, q1470; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #32]471; CHECK-LIS-NEXT: vmovx.f16 s10, s14472; CHECK-LIS-NEXT: vmov.f32 s22, s15473; CHECK-LIS-NEXT: vins.f16 s10, s4474; CHECK-LIS-NEXT: vmovx.f16 s4, s4475; CHECK-LIS-NEXT: vmovx.f16 s11, s5476; CHECK-LIS-NEXT: vins.f16 s22, s4477; CHECK-LIS-NEXT: vmovx.f16 s4, s7478; CHECK-LIS-NEXT: vins.f16 s11, s7479; CHECK-LIS-NEXT: vmovx.f16 s7, s6480; CHECK-LIS-NEXT: vins.f16 s6, s4481; CHECK-LIS-NEXT: vmovx.f16 s4, s17482; CHECK-LIS-NEXT: vmovx.f16 s8, s16483; CHECK-LIS-NEXT: vins.f16 s16, s4484; CHECK-LIS-NEXT: vmovx.f16 s4, s12485; CHECK-LIS-NEXT: vmovx.f16 s9, s19486; CHECK-LIS-NEXT: vins.f16 s19, s4487; CHECK-LIS-NEXT: vmovx.f16 s4, s15488; CHECK-LIS-NEXT: vins.f16 s8, s18489; CHECK-LIS-NEXT: vmov.f32 s20, s17490; CHECK-LIS-NEXT: vmovx.f16 s18, s18491; CHECK-LIS-NEXT: vins.f16 s14, s4492; CHECK-LIS-NEXT: vins.f16 s5, s7493; CHECK-LIS-NEXT: vins.f16 s9, s13494; CHECK-LIS-NEXT: vins.f16 s20, s18495; CHECK-LIS-NEXT: vmov.f32 s17, s19496; CHECK-LIS-NEXT: vmovx.f16 s13, s13497; CHECK-LIS-NEXT: vmov.f32 s21, s12498; CHECK-LIS-NEXT: vstrw.32 q0, [r1, #16]499; CHECK-LIS-NEXT: vmov.f32 s18, s14500; CHECK-LIS-NEXT: vins.f16 s21, s13501; CHECK-LIS-NEXT: vmov.f32 s19, s5502; CHECK-LIS-NEXT: vmov.f32 s23, s6503; CHECK-LIS-NEXT: vadd.i16 q1, q4, q2504; CHECK-LIS-NEXT: vadd.i16 q1, q1, q5505; CHECK-LIS-NEXT: vstrw.32 q1, [r1]506; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11}507; CHECK-LIS-NEXT: bx lr508entry:509 %l1 = load <48 x i16>, ptr %src, align 4510 %s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>511 %s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>512 %s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>513 %a1 = add <16 x i16> %s1, %s2514 %a = add <16 x i16> %a1, %s3515 store <16 x i16> %a, ptr %dst516 ret void517}518 519; i8520 521define void @vld3_v2i8(ptr %src, ptr %dst) {522; CHECK-LABEL: vld3_v2i8:523; CHECK: @ %bb.0: @ %entry524; CHECK-NEXT: .pad #8525; CHECK-NEXT: sub sp, #8526; CHECK-NEXT: ldrd r0, r2, [r0]527; CHECK-NEXT: strd r0, r2, [sp]528; CHECK-NEXT: mov r0, sp529; CHECK-NEXT: vldrb.u16 q0, [r0]530; CHECK-NEXT: vmov.u16 r0, q0[4]531; CHECK-NEXT: vmov.u16 r2, q0[3]532; CHECK-NEXT: add r0, r2533; CHECK-NEXT: vmov.u16 r2, q0[5]534; CHECK-NEXT: add r0, r2535; CHECK-NEXT: strb r0, [r1, #1]536; CHECK-NEXT: vmov.u16 r0, q0[1]537; CHECK-NEXT: vmov.u16 r2, q0[0]538; CHECK-NEXT: add r0, r2539; CHECK-NEXT: vmov.u16 r2, q0[2]540; CHECK-NEXT: add r0, r2541; CHECK-NEXT: strb r0, [r1]542; CHECK-NEXT: add sp, #8543; CHECK-NEXT: bx lr544entry:545 %l1 = load <6 x i8>, ptr %src, align 4546 %s1 = shufflevector <6 x i8> %l1, <6 x i8> undef, <2 x i32> <i32 0, i32 3>547 %s2 = shufflevector <6 x i8> %l1, <6 x i8> undef, <2 x i32> <i32 1, i32 4>548 %s3 = shufflevector <6 x i8> %l1, <6 x i8> undef, <2 x i32> <i32 2, i32 5>549 %a1 = add <2 x i8> %s1, %s2550 %a = add <2 x i8> %a1, %s3551 store <2 x i8> %a, ptr %dst552 ret void553}554 555define void @vld3_v4i8(ptr %src, ptr %dst) {556; CHECK-LABEL: vld3_v4i8:557; CHECK: @ %bb.0: @ %entry558; CHECK-NEXT: .save {r4, lr}559; CHECK-NEXT: push {r4, lr}560; CHECK-NEXT: .pad #8561; CHECK-NEXT: sub sp, #8562; CHECK-NEXT: vldrb.u16 q0, [r0]563; CHECK-NEXT: ldr r0, [r0, #8]564; CHECK-NEXT: str r0, [sp]565; CHECK-NEXT: vmov.u16 r3, q0[6]566; CHECK-NEXT: vmov.u16 r4, q0[0]567; CHECK-NEXT: vmov q1[2], q1[0], r4, r3568; CHECK-NEXT: vmov.u16 r3, q0[7]569; CHECK-NEXT: vmov.u16 r4, q0[1]570; CHECK-NEXT: vmov.u16 r12, q0[5]571; CHECK-NEXT: vmov q2[2], q2[0], r4, r3572; CHECK-NEXT: mov r3, sp573; CHECK-NEXT: vmov.u16 lr, q0[2]574; CHECK-NEXT: vmov.u16 r2, q0[3]575; CHECK-NEXT: vmov.u16 r0, q0[4]576; CHECK-NEXT: vldrb.u16 q0, [r3]577; CHECK-NEXT: vmov.u16 r3, q0[2]578; CHECK-NEXT: vmov q2[3], q2[1], r0, r3579; CHECK-NEXT: vmov.u16 r0, q0[1]580; CHECK-NEXT: vmov q1[3], q1[1], r2, r0581; CHECK-NEXT: vmov.u16 r0, q0[0]582; CHECK-NEXT: vadd.i32 q1, q1, q2583; CHECK-NEXT: vmov q2[2], q2[0], lr, r0584; CHECK-NEXT: vmov.u16 r0, q0[3]585; CHECK-NEXT: vmov q2[3], q2[1], r12, r0586; CHECK-NEXT: vadd.i32 q0, q1, q2587; CHECK-NEXT: vstrb.32 q0, [r1]588; CHECK-NEXT: add sp, #8589; CHECK-NEXT: pop {r4, pc}590entry:591 %l1 = load <12 x i8>, ptr %src, align 4592 %s1 = shufflevector <12 x i8> %l1, <12 x i8> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>593 %s2 = shufflevector <12 x i8> %l1, <12 x i8> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>594 %s3 = shufflevector <12 x i8> %l1, <12 x i8> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>595 %a1 = add <4 x i8> %s1, %s2596 %a = add <4 x i8> %a1, %s3597 store <4 x i8> %a, ptr %dst598 ret void599}600 601define void @vld3_v8i8(ptr %src, ptr %dst) {602; CHECK-LABEL: vld3_v8i8:603; CHECK: @ %bb.0: @ %entry604; CHECK-NEXT: .vsave {d8, d9}605; CHECK-NEXT: vpush {d8, d9}606; CHECK-NEXT: vldrw.u32 q0, [r0]607; CHECK-NEXT: vldrb.u16 q1, [r0, #16]608; CHECK-NEXT: vmov.u8 r2, q0[1]609; CHECK-NEXT: vmov.u8 r0, q0[0]610; CHECK-NEXT: vmov.16 q2[0], r2611; CHECK-NEXT: vmov.u8 r2, q0[4]612; CHECK-NEXT: vmov.16 q3[0], r0613; CHECK-NEXT: vmov.u8 r0, q0[3]614; CHECK-NEXT: vmov.16 q2[1], r2615; CHECK-NEXT: vmov.u8 r2, q0[7]616; CHECK-NEXT: vmov.16 q3[1], r0617; CHECK-NEXT: vmov.u8 r0, q0[6]618; CHECK-NEXT: vmov.16 q2[2], r2619; CHECK-NEXT: vmov.u8 r2, q0[10]620; CHECK-NEXT: vmov.16 q3[2], r0621; CHECK-NEXT: vmov.u8 r0, q0[9]622; CHECK-NEXT: vmov.16 q2[3], r2623; CHECK-NEXT: vmov.u8 r2, q0[13]624; CHECK-NEXT: vmov.16 q3[3], r0625; CHECK-NEXT: vmov.u8 r0, q0[12]626; CHECK-NEXT: vmov.16 q2[4], r2627; CHECK-NEXT: vmov.16 q3[4], r0628; CHECK-NEXT: vmov.u8 r0, q0[15]629; CHECK-NEXT: vmovx.f16 s16, s6630; CHECK-NEXT: vmov.f32 s18, s5631; CHECK-NEXT: vmovx.f16 s11, s5632; CHECK-NEXT: vmov.16 q3[5], r0633; CHECK-NEXT: vins.f16 s18, s16634; CHECK-NEXT: vins.f16 s10, s4635; CHECK-NEXT: vins.f16 s11, s7636; CHECK-NEXT: vmov.f32 s15, s18637; CHECK-NEXT: vmov.u8 r0, q0[2]638; CHECK-NEXT: vadd.i16 q2, q3, q2639; CHECK-NEXT: vmov.16 q3[0], r0640; CHECK-NEXT: vmov.u8 r0, q0[5]641; CHECK-NEXT: vmov.16 q3[1], r0642; CHECK-NEXT: vmov.u8 r0, q0[8]643; CHECK-NEXT: vmov.16 q3[2], r0644; CHECK-NEXT: vmov.u8 r0, q0[11]645; CHECK-NEXT: vmov.16 q3[3], r0646; CHECK-NEXT: vmov.u8 r0, q0[14]647; CHECK-NEXT: vmov.16 q3[4], r0648; CHECK-NEXT: vmov.u16 r0, q1[1]649; CHECK-NEXT: vmovx.f16 s0, s7650; CHECK-NEXT: vmov.f32 s2, s6651; CHECK-NEXT: vins.f16 s2, s0652; CHECK-NEXT: vmov.16 q3[5], r0653; CHECK-NEXT: vmov.f32 s15, s2654; CHECK-NEXT: vadd.i16 q0, q2, q3655; CHECK-NEXT: vstrb.16 q0, [r1]656; CHECK-NEXT: vpop {d8, d9}657; CHECK-NEXT: bx lr658entry:659 %l1 = load <24 x i8>, ptr %src, align 4660 %s1 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>661 %s2 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>662 %s3 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>663 %a1 = add <8 x i8> %s1, %s2664 %a = add <8 x i8> %a1, %s3665 store <8 x i8> %a, ptr %dst666 ret void667}668 669define void @vld3_v16i8(ptr %src, ptr %dst) {670; CHECK-LABEL: vld3_v16i8:671; CHECK: @ %bb.0: @ %entry672; CHECK-NEXT: .vsave {d8, d9, d10, d11}673; CHECK-NEXT: vpush {d8, d9, d10, d11}674; CHECK-NEXT: vldrw.u32 q1, [r0]675; CHECK-NEXT: vldrw.u32 q0, [r0, #16]676; CHECK-NEXT: vldrw.u32 q2, [r0, #32]677; CHECK-NEXT: vmov.u8 r2, q1[1]678; CHECK-NEXT: vmov.8 q3[0], r2679; CHECK-NEXT: vmov.u8 r2, q1[4]680; CHECK-NEXT: vmov.8 q3[1], r2681; CHECK-NEXT: vmov.u8 r2, q1[7]682; CHECK-NEXT: vmov.8 q3[2], r2683; CHECK-NEXT: vmov.u8 r2, q1[10]684; CHECK-NEXT: vmov.8 q3[3], r2685; CHECK-NEXT: vmov.u8 r2, q1[13]686; CHECK-NEXT: vmov.8 q3[4], r2687; CHECK-NEXT: vmov.u8 r2, q0[0]688; CHECK-NEXT: vmov.8 q3[5], r2689; CHECK-NEXT: vmov.u8 r2, q0[3]690; CHECK-NEXT: vmov.8 q3[6], r2691; CHECK-NEXT: vmov.u8 r2, q0[9]692; CHECK-NEXT: vmov.8 q4[8], r2693; CHECK-NEXT: vmov.u8 r2, q0[12]694; CHECK-NEXT: vmov.8 q4[9], r2695; CHECK-NEXT: vmov.u8 r2, q0[15]696; CHECK-NEXT: vmov.8 q4[10], r2697; CHECK-NEXT: vmov.u8 r0, q2[2]698; CHECK-NEXT: vmov.8 q4[11], r0699; CHECK-NEXT: vmov.u8 r0, q2[5]700; CHECK-NEXT: vmov.8 q4[12], r0701; CHECK-NEXT: vmov.u8 r0, q2[8]702; CHECK-NEXT: vmov.8 q4[13], r0703; CHECK-NEXT: vmov.u8 r0, q2[11]704; CHECK-NEXT: vmov.8 q4[14], r0705; CHECK-NEXT: vmov.u8 r0, q2[14]706; CHECK-NEXT: vmov.8 q4[15], r0707; CHECK-NEXT: vmov.u8 r0, q0[6]708; CHECK-NEXT: vmov.8 q3[7], r0709; CHECK-NEXT: vmov.u8 r0, q1[0]710; CHECK-NEXT: vmov.f32 s14, s18711; CHECK-NEXT: vmov.f32 s15, s19712; CHECK-NEXT: vmov.8 q4[0], r0713; CHECK-NEXT: vmov.u8 r0, q1[3]714; CHECK-NEXT: vmov.8 q4[1], r0715; CHECK-NEXT: vmov.u8 r0, q1[6]716; CHECK-NEXT: vmov.8 q4[2], r0717; CHECK-NEXT: vmov.u8 r0, q1[9]718; CHECK-NEXT: vmov.8 q4[3], r0719; CHECK-NEXT: vmov.u8 r0, q1[12]720; CHECK-NEXT: vmov.8 q4[4], r0721; CHECK-NEXT: vmov.u8 r0, q1[15]722; CHECK-NEXT: vmov.8 q4[5], r0723; CHECK-NEXT: vmov.u8 r0, q0[2]724; CHECK-NEXT: vmov.8 q4[6], r0725; CHECK-NEXT: vmov.u8 r0, q0[8]726; CHECK-NEXT: vmov.8 q5[8], r0727; CHECK-NEXT: vmov.u8 r0, q0[11]728; CHECK-NEXT: vmov.8 q5[9], r0729; CHECK-NEXT: vmov.u8 r0, q0[14]730; CHECK-NEXT: vmov.8 q5[10], r0731; CHECK-NEXT: vmov.u8 r0, q2[1]732; CHECK-NEXT: vmov.8 q5[11], r0733; CHECK-NEXT: vmov.u8 r0, q2[4]734; CHECK-NEXT: vmov.8 q5[12], r0735; CHECK-NEXT: vmov.u8 r0, q2[7]736; CHECK-NEXT: vmov.8 q5[13], r0737; CHECK-NEXT: vmov.u8 r0, q2[10]738; CHECK-NEXT: vmov.8 q5[14], r0739; CHECK-NEXT: vmov.u8 r0, q2[13]740; CHECK-NEXT: vmov.8 q5[15], r0741; CHECK-NEXT: vmov.u8 r0, q0[5]742; CHECK-NEXT: vmov.8 q4[7], r0743; CHECK-NEXT: vmov.u8 r0, q1[2]744; CHECK-NEXT: vmov.f32 s18, s22745; CHECK-NEXT: vmov.f32 s19, s23746; CHECK-NEXT: vadd.i8 q3, q4, q3747; CHECK-NEXT: vmov.8 q4[0], r0748; CHECK-NEXT: vmov.u8 r0, q1[5]749; CHECK-NEXT: vmov.8 q4[1], r0750; CHECK-NEXT: vmov.u8 r0, q1[8]751; CHECK-NEXT: vmov.8 q4[2], r0752; CHECK-NEXT: vmov.u8 r0, q1[11]753; CHECK-NEXT: vmov.8 q4[3], r0754; CHECK-NEXT: vmov.u8 r0, q1[14]755; CHECK-NEXT: vmov.8 q4[4], r0756; CHECK-NEXT: vmov.u8 r0, q0[1]757; CHECK-NEXT: vmov.8 q4[5], r0758; CHECK-NEXT: vmov.u8 r0, q0[4]759; CHECK-NEXT: vmov.8 q4[6], r0760; CHECK-NEXT: vmov.u8 r0, q0[10]761; CHECK-NEXT: vmov.8 q1[8], r0762; CHECK-NEXT: vmov.u8 r0, q0[13]763; CHECK-NEXT: vmov.8 q1[9], r0764; CHECK-NEXT: vmov.u8 r0, q2[0]765; CHECK-NEXT: vmov.8 q1[10], r0766; CHECK-NEXT: vmov.u8 r0, q2[3]767; CHECK-NEXT: vmov.8 q1[11], r0768; CHECK-NEXT: vmov.u8 r0, q2[6]769; CHECK-NEXT: vmov.8 q1[12], r0770; CHECK-NEXT: vmov.u8 r0, q2[9]771; CHECK-NEXT: vmov.8 q1[13], r0772; CHECK-NEXT: vmov.u8 r0, q2[12]773; CHECK-NEXT: vmov.8 q1[14], r0774; CHECK-NEXT: vmov.u8 r0, q2[15]775; CHECK-NEXT: vmov.8 q1[15], r0776; CHECK-NEXT: vmov.u8 r0, q0[7]777; CHECK-NEXT: vmov.8 q4[7], r0778; CHECK-NEXT: vmov.f32 s18, s6779; CHECK-NEXT: vmov.f32 s19, s7780; CHECK-NEXT: vadd.i8 q0, q3, q4781; CHECK-NEXT: vstrw.32 q0, [r1]782; CHECK-NEXT: vpop {d8, d9, d10, d11}783; CHECK-NEXT: bx lr784entry:785 %l1 = load <48 x i8>, ptr %src, align 4786 %s1 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>787 %s2 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>788 %s3 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>789 %a1 = add <16 x i8> %s1, %s2790 %a = add <16 x i8> %a1, %s3791 store <16 x i8> %a, ptr %dst792 ret void793}794 795; i64796 797define void @vld3_v2i64(ptr %src, ptr %dst) {798; CHECK-LV-LABEL: vld3_v2i64:799; CHECK-LV: @ %bb.0: @ %entry800; CHECK-LV-NEXT: .save {r4, r5, r6, r7, r8, lr}801; CHECK-LV-NEXT: push.w {r4, r5, r6, r7, r8, lr}802; CHECK-LV-NEXT: vldrw.u32 q0, [r0]803; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #32]804; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #16]805; CHECK-LV-NEXT: vmov.f32 s12, s2806; CHECK-LV-NEXT: vmov.f32 s13, s3807; CHECK-LV-NEXT: vmov.f32 s2, s4808; CHECK-LV-NEXT: vmov.f32 s3, s5809; CHECK-LV-NEXT: vmov r0, r3, d5810; CHECK-LV-NEXT: vmov r2, r4, d3811; CHECK-LV-NEXT: vmov r6, r7, d0812; CHECK-LV-NEXT: vmov r5, r8, d6813; CHECK-LV-NEXT: vmov lr, r12, d1814; CHECK-LV-NEXT: adds.w r0, r0, lr815; CHECK-LV-NEXT: adc.w r3, r3, r12816; CHECK-LV-NEXT: adds r0, r0, r2817; CHECK-LV-NEXT: adc.w r2, r3, r4818; CHECK-LV-NEXT: vmov r3, r4, d4819; CHECK-LV-NEXT: adds r6, r6, r5820; CHECK-LV-NEXT: adc.w r7, r7, r8821; CHECK-LV-NEXT: adds r3, r3, r6822; CHECK-LV-NEXT: adcs r7, r4823; CHECK-LV-NEXT: vmov q0[2], q0[0], r3, r0824; CHECK-LV-NEXT: vmov q0[3], q0[1], r7, r2825; CHECK-LV-NEXT: vstrw.32 q0, [r1]826; CHECK-LV-NEXT: pop.w {r4, r5, r6, r7, r8, pc}827;828; CHECK-LIS-LABEL: vld3_v2i64:829; CHECK-LIS: @ %bb.0: @ %entry830; CHECK-LIS-NEXT: .save {r4, r5, r6, r7, r8, lr}831; CHECK-LIS-NEXT: push.w {r4, r5, r6, r7, r8, lr}832; CHECK-LIS-NEXT: vldrw.u32 q0, [r0]833; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #32]834; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #16]835; CHECK-LIS-NEXT: vmov.f32 s8, s2836; CHECK-LIS-NEXT: vmov.f32 s9, s3837; CHECK-LIS-NEXT: vmov.f32 s2, s4838; CHECK-LIS-NEXT: vmov.f32 s3, s5839; CHECK-LIS-NEXT: vmov r0, r3, d7840; CHECK-LIS-NEXT: vmov r2, r4, d3841; CHECK-LIS-NEXT: vmov r6, r7, d0842; CHECK-LIS-NEXT: vmov r5, r8, d4843; CHECK-LIS-NEXT: vmov lr, r12, d1844; CHECK-LIS-NEXT: adds.w r0, r0, lr845; CHECK-LIS-NEXT: adc.w r3, r3, r12846; CHECK-LIS-NEXT: adds r0, r0, r2847; CHECK-LIS-NEXT: adc.w r2, r3, r4848; CHECK-LIS-NEXT: vmov r3, r4, d6849; CHECK-LIS-NEXT: adds r6, r6, r5850; CHECK-LIS-NEXT: adc.w r7, r7, r8851; CHECK-LIS-NEXT: adds r3, r3, r6852; CHECK-LIS-NEXT: adcs r7, r4853; CHECK-LIS-NEXT: vmov q0[2], q0[0], r3, r0854; CHECK-LIS-NEXT: vmov q0[3], q0[1], r7, r2855; CHECK-LIS-NEXT: vstrw.32 q0, [r1]856; CHECK-LIS-NEXT: pop.w {r4, r5, r6, r7, r8, pc}857 858entry:859 %l1 = load <6 x i64>, ptr %src, align 4860 %s1 = shufflevector <6 x i64> %l1, <6 x i64> undef, <2 x i32> <i32 0, i32 3>861 %s2 = shufflevector <6 x i64> %l1, <6 x i64> undef, <2 x i32> <i32 1, i32 4>862 %s3 = shufflevector <6 x i64> %l1, <6 x i64> undef, <2 x i32> <i32 2, i32 5>863 %a1 = add <2 x i64> %s1, %s2864 %a = add <2 x i64> %a1, %s3865 store <2 x i64> %a, ptr %dst866 ret void867}868 869define void @vld3_v4i64(ptr %src, ptr %dst) {870; CHECK-LV-LABEL: vld3_v4i64:871; CHECK-LV: @ %bb.0: @ %entry872; CHECK-LV-NEXT: .save {r4, r5, r6, r7, r8, lr}873; CHECK-LV-NEXT: push.w {r4, r5, r6, r7, r8, lr}874; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11, d12}875; CHECK-LV-NEXT: vpush {d8, d9, d10, d11, d12}876; CHECK-LV-NEXT: vldrw.u32 q0, [r0]877; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #32]878; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #16]879; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #48]880; CHECK-LV-NEXT: vmov.f32 s4, s2881; CHECK-LV-NEXT: vldrw.u32 q5, [r0, #64]882; CHECK-LV-NEXT: vmov.f32 s5, s3883; CHECK-LV-NEXT: vmov.f32 s2, s12884; CHECK-LV-NEXT: vmov.f32 s3, s13885; CHECK-LV-NEXT: vmov r2, r3, d5886; CHECK-LV-NEXT: vmov r4, r8, d7887; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #80]888; CHECK-LV-NEXT: vmov.f32 s24, s18889; CHECK-LV-NEXT: vmov.f32 s25, s19890; CHECK-LV-NEXT: vmov.f32 s6, s22891; CHECK-LV-NEXT: vmov.f32 s7, s23892; CHECK-LV-NEXT: vmov lr, r12, d1893; CHECK-LV-NEXT: vmov.f32 s2, s12894; CHECK-LV-NEXT: vmov.f32 s3, s13895; CHECK-LV-NEXT: vmov r6, r7, d12896; CHECK-LV-NEXT: adds.w r0, r2, lr897; CHECK-LV-NEXT: adc.w r2, r3, r12898; CHECK-LV-NEXT: adds.w lr, r0, r4899; CHECK-LV-NEXT: vmov r3, r5, d8900; CHECK-LV-NEXT: adc.w r12, r2, r8901; CHECK-LV-NEXT: vmov r2, r0, d10902; CHECK-LV-NEXT: adds r3, r3, r6903; CHECK-LV-NEXT: adcs r7, r5904; CHECK-LV-NEXT: adds r2, r2, r3905; CHECK-LV-NEXT: adc.w r8, r7, r0906; CHECK-LV-NEXT: vmov r6, r5, d1907; CHECK-LV-NEXT: vmov r3, r7, d3908; CHECK-LV-NEXT: vmov r4, r0, d0909; CHECK-LV-NEXT: adds r3, r3, r6910; CHECK-LV-NEXT: adcs r7, r5911; CHECK-LV-NEXT: vmov r6, r5, d7912; CHECK-LV-NEXT: adds r3, r3, r6913; CHECK-LV-NEXT: adcs r7, r5914; CHECK-LV-NEXT: vmov r6, r5, d2915; CHECK-LV-NEXT: vmov q1[2], q1[0], r2, r3916; CHECK-LV-NEXT: vmov q1[3], q1[1], r8, r7917; CHECK-LV-NEXT: vstrw.32 q1, [r1, #16]918; CHECK-LV-NEXT: adds r4, r4, r6919; CHECK-LV-NEXT: adcs r0, r5920; CHECK-LV-NEXT: vmov r5, r6, d4921; CHECK-LV-NEXT: adds r4, r4, r5922; CHECK-LV-NEXT: vmov q0[2], q0[0], r4, lr923; CHECK-LV-NEXT: adcs r0, r6924; CHECK-LV-NEXT: vmov q0[3], q0[1], r0, r12925; CHECK-LV-NEXT: vstrw.32 q0, [r1]926; CHECK-LV-NEXT: vpop {d8, d9, d10, d11, d12}927; CHECK-LV-NEXT: pop.w {r4, r5, r6, r7, r8, pc}928;929; CHECK-LIS-LABEL: vld3_v4i64:930; CHECK-LIS: @ %bb.0: @ %entry931; CHECK-LIS-NEXT: .save {r4, r5, r6, r7, r8, lr}932; CHECK-LIS-NEXT: push.w {r4, r5, r6, r7, r8, lr}933; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11, d12}934; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11, d12}935; CHECK-LIS-NEXT: vldrw.u32 q0, [r0]936; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #32]937; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #16]938; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #48]939; CHECK-LIS-NEXT: vmov.f32 s4, s2940; CHECK-LIS-NEXT: vldrw.u32 q5, [r0, #64]941; CHECK-LIS-NEXT: vmov.f32 s5, s3942; CHECK-LIS-NEXT: vmov.f32 s2, s12943; CHECK-LIS-NEXT: vmov.f32 s3, s13944; CHECK-LIS-NEXT: vmov r5, r4, d5945; CHECK-LIS-NEXT: vmov r3, r8, d7946; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #80]947; CHECK-LIS-NEXT: vmov.f32 s24, s18948; CHECK-LIS-NEXT: vmov.f32 s25, s19949; CHECK-LIS-NEXT: vmov.f32 s6, s22950; CHECK-LIS-NEXT: vmov.f32 s7, s23951; CHECK-LIS-NEXT: vmov lr, r12, d1952; CHECK-LIS-NEXT: vmov.f32 s2, s12953; CHECK-LIS-NEXT: vmov.f32 s3, s13954; CHECK-LIS-NEXT: vmov r7, r6, d12955; CHECK-LIS-NEXT: adds.w r0, r5, lr956; CHECK-LIS-NEXT: adc.w r5, r4, r12957; CHECK-LIS-NEXT: adds.w lr, r0, r3958; CHECK-LIS-NEXT: vmov r4, r2, d8959; CHECK-LIS-NEXT: adc.w r12, r5, r8960; CHECK-LIS-NEXT: vmov r5, r0, d10961; CHECK-LIS-NEXT: adds r7, r7, r4962; CHECK-LIS-NEXT: adcs r2, r6963; CHECK-LIS-NEXT: adds r7, r7, r5964; CHECK-LIS-NEXT: adc.w r8, r2, r0965; CHECK-LIS-NEXT: vmov r6, r4, d1966; CHECK-LIS-NEXT: vmov r2, r5, d3967; CHECK-LIS-NEXT: vmov r3, r0, d0968; CHECK-LIS-NEXT: adds r2, r2, r6969; CHECK-LIS-NEXT: adc.w r6, r5, r4970; CHECK-LIS-NEXT: vmov r5, r4, d7971; CHECK-LIS-NEXT: adds r2, r2, r5972; CHECK-LIS-NEXT: adcs r6, r4973; CHECK-LIS-NEXT: vmov r5, r4, d2974; CHECK-LIS-NEXT: vmov q1[2], q1[0], r7, r2975; CHECK-LIS-NEXT: vmov q1[3], q1[1], r8, r6976; CHECK-LIS-NEXT: vstrw.32 q1, [r1, #16]977; CHECK-LIS-NEXT: adds r3, r3, r5978; CHECK-LIS-NEXT: adcs r0, r4979; CHECK-LIS-NEXT: vmov r4, r5, d4980; CHECK-LIS-NEXT: adds r3, r3, r4981; CHECK-LIS-NEXT: vmov q0[2], q0[0], r3, lr982; CHECK-LIS-NEXT: adcs r0, r5983; CHECK-LIS-NEXT: vmov q0[3], q0[1], r0, r12984; CHECK-LIS-NEXT: vstrw.32 q0, [r1]985; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11, d12}986; CHECK-LIS-NEXT: pop.w {r4, r5, r6, r7, r8, pc}987entry:988 %l1 = load <12 x i64>, ptr %src, align 4989 %s1 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>990 %s2 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>991 %s3 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>992 %a1 = add <4 x i64> %s1, %s2993 %a = add <4 x i64> %a1, %s3994 store <4 x i64> %a, ptr %dst995 ret void996}997 998; f32999 1000define void @vld3_v2f32(ptr %src, ptr %dst) {1001; CHECK-LV-LABEL: vld3_v2f32:1002; CHECK-LV: @ %bb.0: @ %entry1003; CHECK-LV-NEXT: vldrw.u32 q2, [r0]1004; CHECK-LV-NEXT: vldr s1, [r0, #16]1005; CHECK-LV-NEXT: vldr s5, [r0, #20]1006; CHECK-LV-NEXT: vmov.f32 s12, s81007; CHECK-LV-NEXT: vmov.f32 s13, s111008; CHECK-LV-NEXT: vmov.f32 s0, s91009; CHECK-LV-NEXT: vadd.f32 q0, q3, q01010; CHECK-LV-NEXT: vmov.f32 s4, s101011; CHECK-LV-NEXT: vadd.f32 q0, q0, q11012; CHECK-LV-NEXT: vstmia r1, {s0, s1}1013; CHECK-LV-NEXT: bx lr1014;1015; CHECK-LIS-LABEL: vld3_v2f32:1016; CHECK-LIS: @ %bb.0: @ %entry1017; CHECK-LIS-NEXT: vldrw.u32 q2, [r0]1018; CHECK-LIS-NEXT: vldr s5, [r0, #16]1019; CHECK-LIS-NEXT: vldr s1, [r0, #20]1020; CHECK-LIS-NEXT: vmov.f32 s12, s81021; CHECK-LIS-NEXT: vmov.f32 s13, s111022; CHECK-LIS-NEXT: vmov.f32 s4, s91023; CHECK-LIS-NEXT: vadd.f32 q1, q3, q11024; CHECK-LIS-NEXT: vmov.f32 s0, s101025; CHECK-LIS-NEXT: vadd.f32 q0, q1, q01026; CHECK-LIS-NEXT: vstmia r1, {s0, s1}1027; CHECK-LIS-NEXT: bx lr1028 1029entry:1030 %l1 = load <6 x float>, ptr %src, align 41031 %s1 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 0, i32 3>1032 %s2 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 1, i32 4>1033 %s3 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 2, i32 5>1034 %a1 = fadd <2 x float> %s1, %s21035 %a = fadd <2 x float> %a1, %s31036 store <2 x float> %a, ptr %dst1037 ret void1038}1039 1040define void @vld3_v4f32(ptr %src, ptr %dst) {1041; CHECK-LABEL: vld3_v4f32:1042; CHECK: @ %bb.0: @ %entry1043; CHECK-NEXT: .vsave {d8, d9}1044; CHECK-NEXT: vpush {d8, d9}1045; CHECK-NEXT: vldrw.u32 q0, [r0, #16]1046; CHECK-NEXT: vldrw.u32 q1, [r0]1047; CHECK-NEXT: vldrw.u32 q4, [r0, #32]1048; CHECK-NEXT: vmov.f32 s10, s21049; CHECK-NEXT: vmov.f32 s13, s01050; CHECK-NEXT: vmov.f32 s14, s31051; CHECK-NEXT: vmov.f32 s8, s41052; CHECK-NEXT: vmov.f32 s9, s71053; CHECK-NEXT: vmov.f32 s12, s51054; CHECK-NEXT: vmov.f32 s15, s181055; CHECK-NEXT: vmov.f32 s11, s171056; CHECK-NEXT: vadd.f32 q2, q2, q31057; CHECK-NEXT: vmov.f32 s0, s61058; CHECK-NEXT: vmov.f32 s2, s161059; CHECK-NEXT: vmov.f32 s3, s191060; CHECK-NEXT: vadd.f32 q0, q2, q01061; CHECK-NEXT: vstrw.32 q0, [r1]1062; CHECK-NEXT: vpop {d8, d9}1063; CHECK-NEXT: bx lr1064 1065entry:1066 %l1 = load <12 x float>, ptr %src, align 41067 %s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1068 %s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>1069 %s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>1070 %a1 = fadd <4 x float> %s1, %s21071 %a = fadd <4 x float> %a1, %s31072 store <4 x float> %a, ptr %dst1073 ret void1074}1075 1076define void @vld3_v8f32(ptr %src, ptr %dst) {1077; CHECK-LABEL: vld3_v8f32:1078; CHECK: @ %bb.0: @ %entry1079; CHECK-NEXT: .vsave {d8, d9, d10, d11}1080; CHECK-NEXT: vpush {d8, d9, d10, d11}1081; CHECK-NEXT: vldrw.u32 q0, [r0, #64]1082; CHECK-NEXT: vldrw.u32 q1, [r0, #48]1083; CHECK-NEXT: vldrw.u32 q4, [r0, #80]1084; CHECK-NEXT: vmov.f32 s10, s21085; CHECK-NEXT: vmov.f32 s13, s01086; CHECK-NEXT: vmov.f32 s14, s31087; CHECK-NEXT: vmov.f32 s8, s41088; CHECK-NEXT: vmov.f32 s9, s71089; CHECK-NEXT: vmov.f32 s12, s51090; CHECK-NEXT: vmov.f32 s15, s181091; CHECK-NEXT: vmov.f32 s11, s171092; CHECK-NEXT: vadd.f32 q2, q2, q31093; CHECK-NEXT: vmov.f32 s0, s61094; CHECK-NEXT: vmov.f32 s2, s161095; CHECK-NEXT: vldrw.u32 q1, [r0, #16]1096; CHECK-NEXT: vmov.f32 s3, s191097; CHECK-NEXT: vldrw.u32 q3, [r0, #32]1098; CHECK-NEXT: vadd.f32 q0, q2, q01099; CHECK-NEXT: vldrw.u32 q2, [r0]1100; CHECK-NEXT: vmov.f32 s17, s41101; CHECK-NEXT: vstrw.32 q0, [r1, #16]1102; CHECK-NEXT: vmov.f32 s18, s71103; CHECK-NEXT: vmov.f32 s22, s61104; CHECK-NEXT: vmov.f32 s16, s91105; CHECK-NEXT: vmov.f32 s19, s141106; CHECK-NEXT: vmov.f32 s20, s81107; CHECK-NEXT: vmov.f32 s21, s111108; CHECK-NEXT: vmov.f32 s23, s131109; CHECK-NEXT: vadd.f32 q4, q5, q41110; CHECK-NEXT: vmov.f32 s4, s101111; CHECK-NEXT: vmov.f32 s6, s121112; CHECK-NEXT: vmov.f32 s7, s151113; CHECK-NEXT: vadd.f32 q1, q4, q11114; CHECK-NEXT: vstrw.32 q1, [r1]1115; CHECK-NEXT: vpop {d8, d9, d10, d11}1116; CHECK-NEXT: bx lr1117 1118entry:1119 %l1 = load <24 x float>, ptr %src, align 41120 %s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>1121 %s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>1122 %s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>1123 %a1 = fadd <8 x float> %s1, %s21124 %a = fadd <8 x float> %a1, %s31125 store <8 x float> %a, ptr %dst1126 ret void1127}1128 1129define void @vld3_v16f32(ptr %src, ptr %dst) {1130; CHECK-LABEL: vld3_v16f32:1131; CHECK: @ %bb.0: @ %entry1132; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1133; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1134; CHECK-NEXT: vldrw.u32 q0, [r0, #64]1135; CHECK-NEXT: vldrw.u32 q1, [r0, #48]1136; CHECK-NEXT: vldrw.u32 q4, [r0, #80]1137; CHECK-NEXT: vldrw.u32 q6, [r0, #176]1138; CHECK-NEXT: vmov.f32 s10, s21139; CHECK-NEXT: vmov.f32 s13, s01140; CHECK-NEXT: vmov.f32 s14, s31141; CHECK-NEXT: vmov.f32 s8, s41142; CHECK-NEXT: vmov.f32 s9, s71143; CHECK-NEXT: vmov.f32 s12, s51144; CHECK-NEXT: vmov.f32 s15, s181145; CHECK-NEXT: vmov.f32 s11, s171146; CHECK-NEXT: vadd.f32 q2, q2, q31147; CHECK-NEXT: vmov.f32 s0, s61148; CHECK-NEXT: vmov.f32 s2, s161149; CHECK-NEXT: vldrw.u32 q1, [r0, #16]1150; CHECK-NEXT: vmov.f32 s3, s191151; CHECK-NEXT: vldrw.u32 q3, [r0, #32]1152; CHECK-NEXT: vadd.f32 q0, q2, q01153; CHECK-NEXT: vldrw.u32 q2, [r0]1154; CHECK-NEXT: vmov.f32 s17, s41155; CHECK-NEXT: vmov.f32 s18, s71156; CHECK-NEXT: vmov.f32 s22, s61157; CHECK-NEXT: vmov.f32 s16, s91158; CHECK-NEXT: vmov.f32 s19, s141159; CHECK-NEXT: vmov.f32 s20, s81160; CHECK-NEXT: vmov.f32 s21, s111161; CHECK-NEXT: vmov.f32 s23, s131162; CHECK-NEXT: vmov.f32 s4, s101163; CHECK-NEXT: vldrw.u32 q2, [r0, #160]1164; CHECK-NEXT: vmov.f32 s6, s121165; CHECK-NEXT: vadd.f32 q4, q5, q41166; CHECK-NEXT: vmov.f32 s7, s151167; CHECK-NEXT: vldrw.u32 q3, [r0, #144]1168; CHECK-NEXT: vadd.f32 q1, q4, q11169; CHECK-NEXT: vmov.f32 s18, s101170; CHECK-NEXT: vmov.f32 s21, s81171; CHECK-NEXT: vmov.f32 s22, s111172; CHECK-NEXT: vmov.f32 s16, s121173; CHECK-NEXT: vmov.f32 s17, s151174; CHECK-NEXT: vmov.f32 s20, s131175; CHECK-NEXT: vmov.f32 s23, s261176; CHECK-NEXT: vmov.f32 s19, s251177; CHECK-NEXT: vadd.f32 q4, q4, q51178; CHECK-NEXT: vmov.f32 s8, s141179; CHECK-NEXT: vmov.f32 s10, s241180; CHECK-NEXT: vldrw.u32 q3, [r0, #112]1181; CHECK-NEXT: vmov.f32 s11, s271182; CHECK-NEXT: vldrw.u32 q5, [r0, #128]1183; CHECK-NEXT: vadd.f32 q2, q4, q21184; CHECK-NEXT: vldrw.u32 q4, [r0, #96]1185; CHECK-NEXT: vmov.f32 s25, s121186; CHECK-NEXT: vstrw.32 q2, [r1, #48]1187; CHECK-NEXT: vmov.f32 s26, s151188; CHECK-NEXT: vstrw.32 q0, [r1, #16]1189; CHECK-NEXT: vmov.f32 s30, s141190; CHECK-NEXT: vstrw.32 q1, [r1]1191; CHECK-NEXT: vmov.f32 s24, s171192; CHECK-NEXT: vmov.f32 s27, s221193; CHECK-NEXT: vmov.f32 s28, s161194; CHECK-NEXT: vmov.f32 s29, s191195; CHECK-NEXT: vmov.f32 s31, s211196; CHECK-NEXT: vadd.f32 q6, q7, q61197; CHECK-NEXT: vmov.f32 s12, s181198; CHECK-NEXT: vmov.f32 s14, s201199; CHECK-NEXT: vmov.f32 s15, s231200; CHECK-NEXT: vadd.f32 q3, q6, q31201; CHECK-NEXT: vstrw.32 q3, [r1, #32]1202; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1203; CHECK-NEXT: bx lr1204 1205entry:1206 %l1 = load <48 x float>, ptr %src, align 41207 %s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>1208 %s2 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>1209 %s3 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>1210 %a1 = fadd <16 x float> %s1, %s21211 %a = fadd <16 x float> %a1, %s31212 store <16 x float> %a, ptr %dst1213 ret void1214}1215 1216; f161217 1218define void @vld3_v2f16(ptr %src, ptr %dst) {1219; CHECK-LABEL: vld3_v2f16:1220; CHECK: @ %bb.0: @ %entry1221; CHECK-NEXT: ldrd r2, r3, [r0]1222; CHECK-NEXT: ldr r0, [r0, #8]1223; CHECK-NEXT: vmov.32 q0[1], r31224; CHECK-NEXT: vmov q0[2], q0[0], r2, r01225; CHECK-NEXT: vmovx.f16 s8, s01226; CHECK-NEXT: vmovx.f16 s4, s21227; CHECK-NEXT: vins.f16 s8, s21228; CHECK-NEXT: vmovx.f16 s2, s11229; CHECK-NEXT: vins.f16 s1, s41230; CHECK-NEXT: vins.f16 s0, s21231; CHECK-NEXT: vadd.f16 q1, q0, q21232; CHECK-NEXT: vmov.f32 s0, s11233; CHECK-NEXT: vadd.f16 q0, q1, q01234; CHECK-NEXT: vmov r0, s01235; CHECK-NEXT: str r0, [r1]1236; CHECK-NEXT: bx lr1237entry:1238 %l1 = load <6 x half>, ptr %src, align 41239 %s1 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 0, i32 3>1240 %s2 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 1, i32 4>1241 %s3 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 2, i32 5>1242 %a1 = fadd <2 x half> %s1, %s21243 %a = fadd <2 x half> %a1, %s31244 store <2 x half> %a, ptr %dst1245 ret void1246}1247 1248define void @vld3_v4f16(ptr %src, ptr %dst) {1249; CHECK-LABEL: vld3_v4f16:1250; CHECK: @ %bb.0: @ %entry1251; CHECK-NEXT: ldrd r2, r3, [r0, #16]1252; CHECK-NEXT: vldrw.u32 q1, [r0]1253; CHECK-NEXT: vmov.32 q0[0], r21254; CHECK-NEXT: vmovx.f16 s8, s41255; CHECK-NEXT: vmov q3, q01256; CHECK-NEXT: vmov.f32 s1, s01257; CHECK-NEXT: vmov.32 q3[1], r31258; CHECK-NEXT: vmovx.f16 s0, s01259; CHECK-NEXT: vmovx.f16 s2, s131260; CHECK-NEXT: vmovx.f16 s9, s71261; CHECK-NEXT: vins.f16 s1, s21262; CHECK-NEXT: vmovx.f16 s2, s51263; CHECK-NEXT: vins.f16 s4, s21264; CHECK-NEXT: vmovx.f16 s2, s61265; CHECK-NEXT: vins.f16 s5, s21266; CHECK-NEXT: vins.f16 s7, s01267; CHECK-NEXT: vmov.f32 s0, s51268; CHECK-NEXT: vins.f16 s8, s61269; CHECK-NEXT: vins.f16 s9, s131270; CHECK-NEXT: vmov.f32 s5, s71271; CHECK-NEXT: vadd.f16 q1, q1, q21272; CHECK-NEXT: vadd.f16 q0, q1, q01273; CHECK-NEXT: vmov r0, r2, d01274; CHECK-NEXT: strd r0, r2, [r1]1275; CHECK-NEXT: bx lr1276entry:1277 %l1 = load <12 x half>, ptr %src, align 41278 %s1 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1279 %s2 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>1280 %s3 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>1281 %a1 = fadd <4 x half> %s1, %s21282 %a = fadd <4 x half> %a1, %s31283 store <4 x half> %a, ptr %dst1284 ret void1285}1286 1287define void @vld3_v8f16(ptr %src, ptr %dst) {1288; CHECK-LABEL: vld3_v8f16:1289; CHECK: @ %bb.0: @ %entry1290; CHECK-NEXT: .vsave {d8, d9}1291; CHECK-NEXT: vpush {d8, d9}1292; CHECK-NEXT: vldrw.u32 q2, [r0, #16]1293; CHECK-NEXT: vldrw.u32 q0, [r0]1294; CHECK-NEXT: vldrw.u32 q3, [r0, #32]1295; CHECK-NEXT: vmov.f32 s5, s81296; CHECK-NEXT: vmovx.f16 s8, s81297; CHECK-NEXT: vmovx.f16 s17, s31298; CHECK-NEXT: vins.f16 s3, s81299; CHECK-NEXT: vmovx.f16 s8, s111300; CHECK-NEXT: vmovx.f16 s18, s101301; CHECK-NEXT: vmovx.f16 s16, s01302; CHECK-NEXT: vins.f16 s10, s81303; CHECK-NEXT: vmovx.f16 s6, s21304; CHECK-NEXT: vmov.f32 s4, s11305; CHECK-NEXT: vmovx.f16 s8, s141306; CHECK-NEXT: vmovx.f16 s19, s131307; CHECK-NEXT: vins.f16 s4, s61308; CHECK-NEXT: vmovx.f16 s6, s91309; CHECK-NEXT: vins.f16 s16, s21310; CHECK-NEXT: vmovx.f16 s2, s151311; CHECK-NEXT: vmovx.f16 s7, s121312; CHECK-NEXT: vins.f16 s18, s121313; CHECK-NEXT: vmovx.f16 s12, s11314; CHECK-NEXT: vins.f16 s13, s81315; CHECK-NEXT: vins.f16 s5, s61316; CHECK-NEXT: vmov.f32 s6, s111317; CHECK-NEXT: vins.f16 s14, s21318; CHECK-NEXT: vmov.f32 s1, s31319; CHECK-NEXT: vins.f16 s19, s151320; CHECK-NEXT: vins.f16 s17, s91321; CHECK-NEXT: vins.f16 s0, s121322; CHECK-NEXT: vmov.f32 s2, s101323; CHECK-NEXT: vmov.f32 s3, s131324; CHECK-NEXT: vins.f16 s6, s71325; CHECK-NEXT: vmov.f32 s7, s141326; CHECK-NEXT: vadd.f16 q0, q0, q41327; CHECK-NEXT: vadd.f16 q0, q0, q11328; CHECK-NEXT: vstrw.32 q0, [r1]1329; CHECK-NEXT: vpop {d8, d9}1330; CHECK-NEXT: bx lr1331entry:1332 %l1 = load <24 x half>, ptr %src, align 41333 %s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>1334 %s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>1335 %s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>1336 %a1 = fadd <8 x half> %s1, %s21337 %a = fadd <8 x half> %a1, %s31338 store <8 x half> %a, ptr %dst1339 ret void1340}1341 1342define void @vld3_v16f16(ptr %src, ptr %dst) {1343; CHECK-LV-LABEL: vld3_v16f16:1344; CHECK-LV: @ %bb.0: @ %entry1345; CHECK-LV-NEXT: .vsave {d8, d9}1346; CHECK-LV-NEXT: vpush {d8, d9}1347; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #48]1348; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #64]1349; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #80]1350; CHECK-LV-NEXT: vmovx.f16 s6, s21351; CHECK-LV-NEXT: vmov.f32 s4, s11352; CHECK-LV-NEXT: vins.f16 s4, s61353; CHECK-LV-NEXT: vmovx.f16 s6, s91354; CHECK-LV-NEXT: vmov.f32 s5, s81355; CHECK-LV-NEXT: vmovx.f16 s7, s121356; CHECK-LV-NEXT: vins.f16 s5, s61357; CHECK-LV-NEXT: vmov.f32 s6, s111358; CHECK-LV-NEXT: vins.f16 s6, s71359; CHECK-LV-NEXT: vmovx.f16 s16, s151360; CHECK-LV-NEXT: vmov.f32 s7, s141361; CHECK-LV-NEXT: vmovx.f16 s17, s31362; CHECK-LV-NEXT: vins.f16 s7, s161363; CHECK-LV-NEXT: vmovx.f16 s16, s01364; CHECK-LV-NEXT: vins.f16 s16, s21365; CHECK-LV-NEXT: vmovx.f16 s2, s11366; CHECK-LV-NEXT: vins.f16 s0, s21367; CHECK-LV-NEXT: vmovx.f16 s2, s81368; CHECK-LV-NEXT: vins.f16 s3, s21369; CHECK-LV-NEXT: vmovx.f16 s2, s111370; CHECK-LV-NEXT: vmovx.f16 s18, s101371; CHECK-LV-NEXT: vins.f16 s10, s21372; CHECK-LV-NEXT: vmovx.f16 s2, s141373; CHECK-LV-NEXT: vmovx.f16 s19, s131374; CHECK-LV-NEXT: vins.f16 s13, s21375; CHECK-LV-NEXT: vmov.f32 s1, s31376; CHECK-LV-NEXT: vins.f16 s18, s121377; CHECK-LV-NEXT: vins.f16 s19, s151378; CHECK-LV-NEXT: vins.f16 s17, s91379; CHECK-LV-NEXT: vmov.f32 s2, s101380; CHECK-LV-NEXT: vmov.f32 s3, s131381; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #16]1382; CHECK-LV-NEXT: vadd.f16 q0, q0, q41383; CHECK-LV-NEXT: vadd.f16 q3, q0, q11384; CHECK-LV-NEXT: vldrw.u32 q1, [r0]1385; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #32]1386; CHECK-LV-NEXT: vstrw.32 q3, [r1, #16]1387; CHECK-LV-NEXT: vmovx.f16 s14, s61388; CHECK-LV-NEXT: vmov.f32 s12, s51389; CHECK-LV-NEXT: vins.f16 s12, s141390; CHECK-LV-NEXT: vmovx.f16 s14, s91391; CHECK-LV-NEXT: vmov.f32 s13, s81392; CHECK-LV-NEXT: vmovx.f16 s18, s101393; CHECK-LV-NEXT: vins.f16 s13, s141394; CHECK-LV-NEXT: vmovx.f16 s15, s01395; CHECK-LV-NEXT: vmov.f32 s14, s111396; CHECK-LV-NEXT: vins.f16 s18, s01397; CHECK-LV-NEXT: vins.f16 s14, s151398; CHECK-LV-NEXT: vmovx.f16 s16, s31399; CHECK-LV-NEXT: vmov.f32 s15, s21400; CHECK-LV-NEXT: vmovx.f16 s0, s51401; CHECK-LV-NEXT: vins.f16 s15, s161402; CHECK-LV-NEXT: vmovx.f16 s16, s41403; CHECK-LV-NEXT: vins.f16 s4, s01404; CHECK-LV-NEXT: vmovx.f16 s0, s81405; CHECK-LV-NEXT: vmovx.f16 s17, s71406; CHECK-LV-NEXT: vins.f16 s7, s01407; CHECK-LV-NEXT: vmovx.f16 s0, s111408; CHECK-LV-NEXT: vmovx.f16 s19, s11409; CHECK-LV-NEXT: vins.f16 s10, s01410; CHECK-LV-NEXT: vmovx.f16 s0, s21411; CHECK-LV-NEXT: vins.f16 s1, s01412; CHECK-LV-NEXT: vins.f16 s16, s61413; CHECK-LV-NEXT: vmov.f32 s5, s71414; CHECK-LV-NEXT: vins.f16 s19, s31415; CHECK-LV-NEXT: vins.f16 s17, s91416; CHECK-LV-NEXT: vmov.f32 s6, s101417; CHECK-LV-NEXT: vmov.f32 s7, s11418; CHECK-LV-NEXT: vadd.f16 q0, q1, q41419; CHECK-LV-NEXT: vadd.f16 q0, q0, q31420; CHECK-LV-NEXT: vstrw.32 q0, [r1]1421; CHECK-LV-NEXT: vpop {d8, d9}1422; CHECK-LV-NEXT: bx lr1423;1424; CHECK-LIS-LABEL: vld3_v16f16:1425; CHECK-LIS: @ %bb.0: @ %entry1426; CHECK-LIS-NEXT: .vsave {d8, d9}1427; CHECK-LIS-NEXT: vpush {d8, d9}1428; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #48]1429; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #64]1430; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #80]1431; CHECK-LIS-NEXT: vmovx.f16 s6, s21432; CHECK-LIS-NEXT: vmov.f32 s4, s11433; CHECK-LIS-NEXT: vins.f16 s4, s61434; CHECK-LIS-NEXT: vmovx.f16 s6, s91435; CHECK-LIS-NEXT: vmov.f32 s5, s81436; CHECK-LIS-NEXT: vmovx.f16 s7, s121437; CHECK-LIS-NEXT: vins.f16 s5, s61438; CHECK-LIS-NEXT: vmov.f32 s6, s111439; CHECK-LIS-NEXT: vins.f16 s6, s71440; CHECK-LIS-NEXT: vmovx.f16 s16, s151441; CHECK-LIS-NEXT: vmov.f32 s7, s141442; CHECK-LIS-NEXT: vmovx.f16 s17, s31443; CHECK-LIS-NEXT: vins.f16 s7, s161444; CHECK-LIS-NEXT: vmovx.f16 s16, s01445; CHECK-LIS-NEXT: vins.f16 s16, s21446; CHECK-LIS-NEXT: vmovx.f16 s2, s11447; CHECK-LIS-NEXT: vins.f16 s0, s21448; CHECK-LIS-NEXT: vmovx.f16 s2, s81449; CHECK-LIS-NEXT: vins.f16 s3, s21450; CHECK-LIS-NEXT: vmovx.f16 s2, s111451; CHECK-LIS-NEXT: vmovx.f16 s18, s101452; CHECK-LIS-NEXT: vins.f16 s10, s21453; CHECK-LIS-NEXT: vmovx.f16 s2, s141454; CHECK-LIS-NEXT: vmovx.f16 s19, s131455; CHECK-LIS-NEXT: vins.f16 s13, s21456; CHECK-LIS-NEXT: vmov.f32 s1, s31457; CHECK-LIS-NEXT: vins.f16 s18, s121458; CHECK-LIS-NEXT: vins.f16 s19, s151459; CHECK-LIS-NEXT: vins.f16 s17, s91460; CHECK-LIS-NEXT: vmov.f32 s2, s101461; CHECK-LIS-NEXT: vmov.f32 s3, s131462; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #16]1463; CHECK-LIS-NEXT: vadd.f16 q0, q0, q41464; CHECK-LIS-NEXT: vadd.f16 q3, q0, q11465; CHECK-LIS-NEXT: vldrw.u32 q0, [r0]1466; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #32]1467; CHECK-LIS-NEXT: vstrw.32 q3, [r1, #16]1468; CHECK-LIS-NEXT: vmovx.f16 s14, s21469; CHECK-LIS-NEXT: vmov.f32 s12, s11470; CHECK-LIS-NEXT: vins.f16 s12, s141471; CHECK-LIS-NEXT: vmovx.f16 s14, s91472; CHECK-LIS-NEXT: vmov.f32 s13, s81473; CHECK-LIS-NEXT: vmovx.f16 s15, s41474; CHECK-LIS-NEXT: vins.f16 s13, s141475; CHECK-LIS-NEXT: vmov.f32 s14, s111476; CHECK-LIS-NEXT: vins.f16 s14, s151477; CHECK-LIS-NEXT: vmovx.f16 s16, s71478; CHECK-LIS-NEXT: vmov.f32 s15, s61479; CHECK-LIS-NEXT: vmovx.f16 s17, s31480; CHECK-LIS-NEXT: vins.f16 s15, s161481; CHECK-LIS-NEXT: vmovx.f16 s16, s01482; CHECK-LIS-NEXT: vins.f16 s16, s21483; CHECK-LIS-NEXT: vmovx.f16 s2, s11484; CHECK-LIS-NEXT: vins.f16 s0, s21485; CHECK-LIS-NEXT: vmovx.f16 s2, s81486; CHECK-LIS-NEXT: vins.f16 s3, s21487; CHECK-LIS-NEXT: vmovx.f16 s2, s111488; CHECK-LIS-NEXT: vmovx.f16 s18, s101489; CHECK-LIS-NEXT: vins.f16 s10, s21490; CHECK-LIS-NEXT: vmovx.f16 s2, s61491; CHECK-LIS-NEXT: vmovx.f16 s19, s51492; CHECK-LIS-NEXT: vins.f16 s5, s21493; CHECK-LIS-NEXT: vmov.f32 s1, s31494; CHECK-LIS-NEXT: vins.f16 s18, s41495; CHECK-LIS-NEXT: vins.f16 s19, s71496; CHECK-LIS-NEXT: vins.f16 s17, s91497; CHECK-LIS-NEXT: vmov.f32 s2, s101498; CHECK-LIS-NEXT: vmov.f32 s3, s51499; CHECK-LIS-NEXT: vadd.f16 q0, q0, q41500; CHECK-LIS-NEXT: vadd.f16 q0, q0, q31501; CHECK-LIS-NEXT: vstrw.32 q0, [r1]1502; CHECK-LIS-NEXT: vpop {d8, d9}1503; CHECK-LIS-NEXT: bx lr1504 1505entry:1506 %l1 = load <48 x half>, ptr %src, align 41507 %s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>1508 %s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>1509 %s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>1510 %a1 = fadd <16 x half> %s1, %s21511 %a = fadd <16 x half> %a1, %s31512 store <16 x half> %a, ptr %dst1513 ret void1514}1515 1516; f641517 1518define void @vld3_v2f64(ptr %src, ptr %dst) {1519; CHECK-LABEL: vld3_v2f64:1520; CHECK: @ %bb.0: @ %entry1521; CHECK-NEXT: vldrw.u32 q0, [r0, #32]1522; CHECK-NEXT: vldrw.u32 q1, [r0, #16]1523; CHECK-NEXT: vldrw.u32 q2, [r0]1524; CHECK-NEXT: vadd.f64 d0, d3, d01525; CHECK-NEXT: vadd.f64 d3, d4, d51526; CHECK-NEXT: vadd.f64 d1, d0, d11527; CHECK-NEXT: vadd.f64 d0, d3, d21528; CHECK-NEXT: vstrw.32 q0, [r1]1529; CHECK-NEXT: bx lr1530entry:1531 %l1 = load <6 x double>, ptr %src, align 41532 %s1 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 0, i32 3>1533 %s2 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 1, i32 4>1534 %s3 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 2, i32 5>1535 %a1 = fadd <2 x double> %s1, %s21536 %a = fadd <2 x double> %a1, %s31537 store <2 x double> %a, ptr %dst1538 ret void1539}1540 1541define void @vld3_v4f64(ptr %src, ptr %dst) {1542; CHECK-LABEL: vld3_v4f64:1543; CHECK: @ %bb.0: @ %entry1544; CHECK-NEXT: .vsave {d8, d9}1545; CHECK-NEXT: vpush {d8, d9}1546; CHECK-NEXT: vldrw.u32 q1, [r0, #80]1547; CHECK-NEXT: vldrw.u32 q0, [r0, #64]1548; CHECK-NEXT: vldrw.u32 q2, [r0, #48]1549; CHECK-NEXT: vldrw.u32 q3, [r0, #16]1550; CHECK-NEXT: vadd.f64 d1, d1, d21551; CHECK-NEXT: vldrw.u32 q4, [r0]1552; CHECK-NEXT: vadd.f64 d2, d4, d51553; CHECK-NEXT: vldrw.u32 q2, [r0, #32]1554; CHECK-NEXT: vadd.f64 d4, d7, d41555; CHECK-NEXT: vadd.f64 d7, d8, d91556; CHECK-NEXT: vadd.f64 d1, d1, d31557; CHECK-NEXT: vadd.f64 d0, d2, d01558; CHECK-NEXT: vadd.f64 d3, d4, d51559; CHECK-NEXT: vstrw.32 q0, [r1, #16]1560; CHECK-NEXT: vadd.f64 d2, d7, d61561; CHECK-NEXT: vstrw.32 q1, [r1]1562; CHECK-NEXT: vpop {d8, d9}1563; CHECK-NEXT: bx lr1564entry:1565 %l1 = load <12 x double>, ptr %src, align 41566 %s1 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>1567 %s2 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>1568 %s3 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>1569 %a1 = fadd <4 x double> %s1, %s21570 %a = fadd <4 x double> %a1, %s31571 store <4 x double> %a, ptr %dst1572 ret void1573}1574