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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s3 4; i325 6define void @vld4_v2i32(ptr %src, ptr %dst) {7; CHECK-LABEL: vld4_v2i32:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vldrw.u32 q1, [r0, #16]10; CHECK-NEXT: vldrw.u32 q0, [r0]11; CHECK-NEXT: vmov.f32 s10, s712; CHECK-NEXT: vmov r2, s613; CHECK-NEXT: vmov.f32 s6, s514; CHECK-NEXT: vmov r3, s415; CHECK-NEXT: vmov.f32 s8, s316; CHECK-NEXT: vmov.f32 s12, s117; CHECK-NEXT: vmov r0, s1018; CHECK-NEXT: add r0, r219; CHECK-NEXT: vmov r2, s620; CHECK-NEXT: add r2, r321; CHECK-NEXT: vmov r3, s222; CHECK-NEXT: add.w r12, r2, r023; CHECK-NEXT: vmov r2, s824; CHECK-NEXT: vmov r0, s025; CHECK-NEXT: add r2, r326; CHECK-NEXT: vmov r3, s1227; CHECK-NEXT: add r0, r328; CHECK-NEXT: add r0, r229; CHECK-NEXT: strd r0, r12, [r1]30; CHECK-NEXT: bx lr31entry:32 %l1 = load <8 x i32>, ptr %src, align 433 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 0, i32 4>34 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 1, i32 5>35 %s3 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 2, i32 6>36 %s4 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 3, i32 7>37 %a1 = add <2 x i32> %s1, %s238 %a2 = add <2 x i32> %s3, %s439 %a3 = add <2 x i32> %a1, %a240 store <2 x i32> %a3, ptr %dst41 ret void42}43 44define void @vld4_v4i32(ptr %src, ptr %dst) {45; CHECK-LABEL: vld4_v4i32:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]48; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]49; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]50; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]51; CHECK-NEXT: vadd.i32 q2, q2, q352; CHECK-NEXT: vadd.i32 q0, q0, q153; CHECK-NEXT: vadd.i32 q0, q0, q254; CHECK-NEXT: vstrw.32 q0, [r1]55; CHECK-NEXT: bx lr56entry:57 %l1 = load <16 x i32>, ptr %src, align 458 %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>59 %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>60 %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>61 %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>62 %a1 = add <4 x i32> %s1, %s263 %a2 = add <4 x i32> %s3, %s464 %a3 = add <4 x i32> %a1, %a265 store <4 x i32> %a3, ptr %dst66 ret void67}68 69define void @vld4_v8i32(ptr %src, ptr %dst) {70; CHECK-LABEL: vld4_v8i32:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: .vsave {d8, d9, d10, d11}73; CHECK-NEXT: vpush {d8, d9, d10, d11}74; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]75; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]76; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]77; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!78; CHECK-NEXT: vadd.i32 q4, q2, q379; CHECK-NEXT: vadd.i32 q5, q0, q180; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]81; CHECK-NEXT: vadd.i32 q4, q5, q482; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]83; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]84; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]85; CHECK-NEXT: vstrw.32 q4, [r1]86; CHECK-NEXT: vadd.i32 q2, q2, q387; CHECK-NEXT: vadd.i32 q0, q0, q188; CHECK-NEXT: vadd.i32 q0, q0, q289; CHECK-NEXT: vstrw.32 q0, [r1, #16]90; CHECK-NEXT: vpop {d8, d9, d10, d11}91; CHECK-NEXT: bx lr92entry:93 %l1 = load <32 x i32>, ptr %src, align 494 %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>95 %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>96 %s3 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>97 %s4 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>98 %a1 = add <8 x i32> %s1, %s299 %a2 = add <8 x i32> %s3, %s4100 %a3 = add <8 x i32> %a1, %a2101 store <8 x i32> %a3, ptr %dst102 ret void103}104 105define void @vld4_v16i32(ptr %src, ptr %dst) {106; CHECK-LABEL: vld4_v16i32:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}109; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}110; CHECK-NEXT: .pad #32111; CHECK-NEXT: sub sp, #32112; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]113; CHECK-NEXT: mov r2, r0114; CHECK-NEXT: add.w r3, r0, #192115; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]116; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]117; CHECK-NEXT: adds r0, #128118; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!119; CHECK-NEXT: vadd.i32 q2, q2, q3120; CHECK-NEXT: vld40.32 {q3, q4, q5, q6}, [r3]121; CHECK-NEXT: vadd.i32 q0, q0, q1122; CHECK-NEXT: vld41.32 {q3, q4, q5, q6}, [r3]123; CHECK-NEXT: vadd.i32 q0, q0, q2124; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill125; CHECK-NEXT: vld42.32 {q3, q4, q5, q6}, [r3]126; CHECK-NEXT: vld43.32 {q3, q4, q5, q6}, [r3]127; CHECK-NEXT: vadd.i32 q1, q5, q6128; CHECK-NEXT: vadd.i32 q2, q3, q4129; CHECK-NEXT: vadd.i32 q0, q2, q1130; CHECK-NEXT: vld40.32 {q4, q5, q6, q7}, [r2]131; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill132; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]133; CHECK-NEXT: vld41.32 {q4, q5, q6, q7}, [r2]134; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]135; CHECK-NEXT: vld42.32 {q4, q5, q6, q7}, [r2]136; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]137; CHECK-NEXT: vld43.32 {q4, q5, q6, q7}, [r2]138; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]139; CHECK-NEXT: vadd.i32 q0, q0, q1140; CHECK-NEXT: vadd.i32 q2, q2, q3141; CHECK-NEXT: vadd.i32 q0, q0, q2142; CHECK-NEXT: vadd.i32 q1, q6, q7143; CHECK-NEXT: vadd.i32 q2, q4, q5144; CHECK-NEXT: vstrw.32 q0, [r1, #32]145; CHECK-NEXT: vadd.i32 q1, q2, q1146; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload147; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload148; CHECK-NEXT: vstrw.32 q1, [r1, #16]149; CHECK-NEXT: vstrw.32 q2, [r1, #48]150; CHECK-NEXT: vstrw.32 q0, [r1]151; CHECK-NEXT: add sp, #32152; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}153; CHECK-NEXT: bx lr154entry:155 %l1 = load <64 x i32>, ptr %src, align 4156 %s1 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>157 %s2 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>158 %s3 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>159 %s4 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>160 %a1 = add <16 x i32> %s1, %s2161 %a2 = add <16 x i32> %s3, %s4162 %a3 = add <16 x i32> %a1, %a2163 store <16 x i32> %a3, ptr %dst164 ret void165}166 167define void @vld4_v4i32_align1(ptr %src, ptr %dst) {168; CHECK-LABEL: vld4_v4i32_align1:169; CHECK: @ %bb.0: @ %entry170; CHECK-NEXT: .vsave {d8, d9, d10, d11}171; CHECK-NEXT: vpush {d8, d9, d10, d11}172; CHECK-NEXT: vldrb.u8 q0, [r0, #48]173; CHECK-NEXT: vldrb.u8 q1, [r0, #32]174; CHECK-NEXT: vldrb.u8 q3, [r0, #16]175; CHECK-NEXT: vldrb.u8 q2, [r0]176; CHECK-NEXT: vmov.f32 s18, s7177; CHECK-NEXT: vmov.f32 s16, s11178; CHECK-NEXT: vmov.f32 s20, s10179; CHECK-NEXT: vmov.f32 s17, s15180; CHECK-NEXT: vmov.f32 s19, s3181; CHECK-NEXT: vmov.f32 s21, s14182; CHECK-NEXT: vmov.f32 s22, s6183; CHECK-NEXT: vmov.f32 s23, s2184; CHECK-NEXT: vadd.i32 q4, q5, q4185; CHECK-NEXT: vmov.f32 s20, s9186; CHECK-NEXT: vmov.f32 s21, s13187; CHECK-NEXT: vmov.f32 s22, s5188; CHECK-NEXT: vmov.f32 s23, s1189; CHECK-NEXT: vmov.f32 s9, s12190; CHECK-NEXT: vmov.f32 s10, s4191; CHECK-NEXT: vmov.f32 s11, s0192; CHECK-NEXT: vadd.i32 q0, q2, q5193; CHECK-NEXT: vadd.i32 q0, q0, q4194; CHECK-NEXT: vstrw.32 q0, [r1]195; CHECK-NEXT: vpop {d8, d9, d10, d11}196; CHECK-NEXT: bx lr197entry:198 %l1 = load <16 x i32>, ptr %src, align 1199 %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>200 %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>201 %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>202 %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>203 %a1 = add <4 x i32> %s1, %s2204 %a2 = add <4 x i32> %s3, %s4205 %a3 = add <4 x i32> %a1, %a2206 store <4 x i32> %a3, ptr %dst207 ret void208}209 210; i16211 212define void @vld4_v2i16(ptr %src, ptr %dst) {213; CHECK-LABEL: vld4_v2i16:214; CHECK: @ %bb.0: @ %entry215; CHECK-NEXT: vldrh.u16 q0, [r0]216; CHECK-NEXT: vmov.u16 r0, q0[7]217; CHECK-NEXT: vmov.u16 r2, q0[6]218; CHECK-NEXT: add r0, r2219; CHECK-NEXT: vmov.u16 r2, q0[5]220; CHECK-NEXT: vmov.u16 r3, q0[4]221; CHECK-NEXT: add r2, r3222; CHECK-NEXT: vmov.u16 r3, q0[0]223; CHECK-NEXT: add r0, r2224; CHECK-NEXT: strh r0, [r1, #2]225; CHECK-NEXT: vmov.u16 r0, q0[3]226; CHECK-NEXT: vmov.u16 r2, q0[2]227; CHECK-NEXT: add r0, r2228; CHECK-NEXT: vmov.u16 r2, q0[1]229; CHECK-NEXT: add r2, r3230; CHECK-NEXT: add r0, r2231; CHECK-NEXT: strh r0, [r1]232; CHECK-NEXT: bx lr233entry:234 %l1 = load <8 x i16>, ptr %src, align 2235 %s1 = shufflevector <8 x i16> %l1, <8 x i16> undef, <2 x i32> <i32 0, i32 4>236 %s2 = shufflevector <8 x i16> %l1, <8 x i16> undef, <2 x i32> <i32 1, i32 5>237 %s3 = shufflevector <8 x i16> %l1, <8 x i16> undef, <2 x i32> <i32 2, i32 6>238 %s4 = shufflevector <8 x i16> %l1, <8 x i16> undef, <2 x i32> <i32 3, i32 7>239 %a1 = add <2 x i16> %s1, %s2240 %a2 = add <2 x i16> %s3, %s4241 %a3 = add <2 x i16> %a1, %a2242 store <2 x i16> %a3, ptr %dst243 ret void244}245 246define void @vld4_v4i16(ptr %src, ptr %dst) {247; CHECK-LABEL: vld4_v4i16:248; CHECK: @ %bb.0: @ %entry249; CHECK-NEXT: .save {r4, lr}250; CHECK-NEXT: push {r4, lr}251; CHECK-NEXT: .pad #32252; CHECK-NEXT: sub sp, #32253; CHECK-NEXT: vldrh.u16 q0, [r0, #16]254; CHECK-NEXT: mov r4, sp255; CHECK-NEXT: vshr.u32 q1, q0, #16256; CHECK-NEXT: vmov.u16 r3, q0[3]257; CHECK-NEXT: vstrh.32 q1, [r4, #8]258; CHECK-NEXT: vldrh.u16 q1, [r0]259; CHECK-NEXT: add r0, sp, #16260; CHECK-NEXT: vshr.u32 q2, q1, #16261; CHECK-NEXT: vmov.u16 r2, q1[3]262; CHECK-NEXT: vstrh.32 q2, [r4]263; CHECK-NEXT: vmov q2[2], q2[0], r2, r3264; CHECK-NEXT: vmov.u16 r2, q0[7]265; CHECK-NEXT: vmov.u16 r3, q1[7]266; CHECK-NEXT: vmov q2[3], q2[1], r3, r2267; CHECK-NEXT: vmov.u16 r2, q0[2]268; CHECK-NEXT: vmov.u16 r3, q1[2]269; CHECK-NEXT: vstrh.32 q0, [r0, #8]270; CHECK-NEXT: vmov q3[2], q3[0], r3, r2271; CHECK-NEXT: vmov.u16 r2, q0[6]272; CHECK-NEXT: vmov.u16 r3, q1[6]273; CHECK-NEXT: vstrh.32 q1, [r0]274; CHECK-NEXT: vmov q3[3], q3[1], r3, r2275; CHECK-NEXT: vldrw.u32 q1, [r4]276; CHECK-NEXT: vadd.i32 q0, q3, q2277; CHECK-NEXT: vldrw.u32 q2, [r0]278; CHECK-NEXT: vadd.i32 q1, q2, q1279; CHECK-NEXT: vadd.i32 q0, q1, q0280; CHECK-NEXT: vstrh.32 q0, [r1]281; CHECK-NEXT: add sp, #32282; CHECK-NEXT: pop {r4, pc}283entry:284 %l1 = load <16 x i16>, ptr %src, align 2285 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>286 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>287 %s3 = shufflevector <16 x i16> %l1, <16 x i16> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>288 %s4 = shufflevector <16 x i16> %l1, <16 x i16> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>289 %a1 = add <4 x i16> %s1, %s2290 %a2 = add <4 x i16> %s3, %s4291 %a3 = add <4 x i16> %a1, %a2292 store <4 x i16> %a3, ptr %dst293 ret void294}295 296define void @vld4_v8i16(ptr %src, ptr %dst) {297; CHECK-LABEL: vld4_v8i16:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]300; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]301; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]302; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]303; CHECK-NEXT: vadd.i16 q2, q2, q3304; CHECK-NEXT: vadd.i16 q0, q0, q1305; CHECK-NEXT: vadd.i16 q0, q0, q2306; CHECK-NEXT: vstrw.32 q0, [r1]307; CHECK-NEXT: bx lr308entry:309 %l1 = load <32 x i16>, ptr %src, align 2310 %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>311 %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>312 %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>313 %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>314 %a1 = add <8 x i16> %s1, %s2315 %a2 = add <8 x i16> %s3, %s4316 %a3 = add <8 x i16> %a1, %a2317 store <8 x i16> %a3, ptr %dst318 ret void319}320 321define void @vld4_v16i16(ptr %src, ptr %dst) {322; CHECK-LABEL: vld4_v16i16:323; CHECK: @ %bb.0: @ %entry324; CHECK-NEXT: .vsave {d8, d9, d10, d11}325; CHECK-NEXT: vpush {d8, d9, d10, d11}326; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]327; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]328; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]329; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!330; CHECK-NEXT: vadd.i16 q4, q2, q3331; CHECK-NEXT: vadd.i16 q5, q0, q1332; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]333; CHECK-NEXT: vadd.i16 q4, q5, q4334; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]335; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]336; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]337; CHECK-NEXT: vstrw.32 q4, [r1]338; CHECK-NEXT: vadd.i16 q2, q2, q3339; CHECK-NEXT: vadd.i16 q0, q0, q1340; CHECK-NEXT: vadd.i16 q0, q0, q2341; CHECK-NEXT: vstrw.32 q0, [r1, #16]342; CHECK-NEXT: vpop {d8, d9, d10, d11}343; CHECK-NEXT: bx lr344entry:345 %l1 = load <64 x i16>, ptr %src, align 2346 %s1 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>347 %s2 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>348 %s3 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>349 %s4 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>350 %a1 = add <16 x i16> %s1, %s2351 %a2 = add <16 x i16> %s3, %s4352 %a3 = add <16 x i16> %a1, %a2353 store <16 x i16> %a3, ptr %dst354 ret void355}356 357define void @vld4_v8i16_align1(ptr %src, ptr %dst) {358; CHECK-LABEL: vld4_v8i16_align1:359; CHECK: @ %bb.0: @ %entry360; CHECK-NEXT: .vsave {d8, d9, d10, d11}361; CHECK-NEXT: vpush {d8, d9, d10, d11}362; CHECK-NEXT: vldrb.u8 q1, [r0, #32]363; CHECK-NEXT: vmovx.f16 s18, s5364; CHECK-NEXT: vmovx.f16 s0, s7365; CHECK-NEXT: vins.f16 s18, s0366; CHECK-NEXT: vldrb.u8 q0, [r0, #48]367; CHECK-NEXT: vins.f16 s5, s7368; CHECK-NEXT: vmovx.f16 s19, s1369; CHECK-NEXT: vmovx.f16 s8, s3370; CHECK-NEXT: vins.f16 s19, s8371; CHECK-NEXT: vldrb.u8 q2, [r0]372; CHECK-NEXT: vins.f16 s1, s3373; CHECK-NEXT: vmov.f32 s22, s5374; CHECK-NEXT: vmovx.f16 s16, s9375; CHECK-NEXT: vmovx.f16 s12, s11376; CHECK-NEXT: vins.f16 s16, s12377; CHECK-NEXT: vldrb.u8 q3, [r0, #16]378; CHECK-NEXT: vins.f16 s9, s11379; CHECK-NEXT: vmov.f32 s23, s1380; CHECK-NEXT: vmovx.f16 s17, s13381; CHECK-NEXT: vmovx.f16 s20, s15382; CHECK-NEXT: vins.f16 s13, s15383; CHECK-NEXT: vins.f16 s17, s20384; CHECK-NEXT: vmov.f32 s20, s9385; CHECK-NEXT: vmovx.f16 s1, s6386; CHECK-NEXT: vmov.f32 s21, s13387; CHECK-NEXT: vadd.i16 q4, q5, q4388; CHECK-NEXT: vmovx.f16 s22, s4389; CHECK-NEXT: vins.f16 s22, s1390; CHECK-NEXT: vmovx.f16 s23, s0391; CHECK-NEXT: vmovx.f16 s1, s2392; CHECK-NEXT: vmovx.f16 s20, s8393; CHECK-NEXT: vins.f16 s23, s1394; CHECK-NEXT: vmov.f32 s1, s10395; CHECK-NEXT: vmovx.f16 s10, s10396; CHECK-NEXT: vmovx.f16 s21, s12397; CHECK-NEXT: vins.f16 s20, s10398; CHECK-NEXT: vmovx.f16 s10, s14399; CHECK-NEXT: vins.f16 s0, s2400; CHECK-NEXT: vins.f16 s12, s14401; CHECK-NEXT: vins.f16 s4, s6402; CHECK-NEXT: vins.f16 s21, s10403; CHECK-NEXT: vmov.f32 s10, s4404; CHECK-NEXT: vins.f16 s8, s1405; CHECK-NEXT: vmov.f32 s9, s12406; CHECK-NEXT: vmov.f32 s11, s0407; CHECK-NEXT: vadd.i16 q0, q2, q5408; CHECK-NEXT: vadd.i16 q0, q0, q4409; CHECK-NEXT: vstrw.32 q0, [r1]410; CHECK-NEXT: vpop {d8, d9, d10, d11}411; CHECK-NEXT: bx lr412entry:413 %l1 = load <32 x i16>, ptr %src, align 1414 %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>415 %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>416 %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>417 %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>418 %a1 = add <8 x i16> %s1, %s2419 %a2 = add <8 x i16> %s3, %s4420 %a3 = add <8 x i16> %a1, %a2421 store <8 x i16> %a3, ptr %dst422 ret void423}424 425; i8426 427define void @vld4_v2i8(ptr %src, ptr %dst) {428; CHECK-LABEL: vld4_v2i8:429; CHECK: @ %bb.0: @ %entry430; CHECK-NEXT: vldrb.u16 q0, [r0]431; CHECK-NEXT: vmov.u16 r0, q0[7]432; CHECK-NEXT: vmov.u16 r2, q0[6]433; CHECK-NEXT: add r0, r2434; CHECK-NEXT: vmov.u16 r2, q0[5]435; CHECK-NEXT: vmov.u16 r3, q0[4]436; CHECK-NEXT: add r2, r3437; CHECK-NEXT: vmov.u16 r3, q0[0]438; CHECK-NEXT: add r0, r2439; CHECK-NEXT: strb r0, [r1, #1]440; CHECK-NEXT: vmov.u16 r0, q0[3]441; CHECK-NEXT: vmov.u16 r2, q0[2]442; CHECK-NEXT: add r0, r2443; CHECK-NEXT: vmov.u16 r2, q0[1]444; CHECK-NEXT: add r2, r3445; CHECK-NEXT: add r0, r2446; CHECK-NEXT: strb r0, [r1]447; CHECK-NEXT: bx lr448entry:449 %l1 = load <8 x i8>, ptr %src, align 1450 %s1 = shufflevector <8 x i8> %l1, <8 x i8> undef, <2 x i32> <i32 0, i32 4>451 %s2 = shufflevector <8 x i8> %l1, <8 x i8> undef, <2 x i32> <i32 1, i32 5>452 %s3 = shufflevector <8 x i8> %l1, <8 x i8> undef, <2 x i32> <i32 2, i32 6>453 %s4 = shufflevector <8 x i8> %l1, <8 x i8> undef, <2 x i32> <i32 3, i32 7>454 %a1 = add <2 x i8> %s1, %s2455 %a2 = add <2 x i8> %s3, %s4456 %a3 = add <2 x i8> %a1, %a2457 store <2 x i8> %a3, ptr %dst458 ret void459}460 461define void @vld4_v4i8(ptr %src, ptr %dst) {462; CHECK-LABEL: vld4_v4i8:463; CHECK: @ %bb.0: @ %entry464; CHECK-NEXT: vldrb.u8 q0, [r0]465; CHECK-NEXT: vmov.u8 r0, q0[10]466; CHECK-NEXT: vmov.u8 r2, q0[2]467; CHECK-NEXT: vmov q1[2], q1[0], r2, r0468; CHECK-NEXT: vmov.u8 r0, q0[14]469; CHECK-NEXT: vmov.u8 r2, q0[6]470; CHECK-NEXT: vrev32.8 q2, q0471; CHECK-NEXT: vmov q1[3], q1[1], r2, r0472; CHECK-NEXT: vadd.i32 q1, q1, q2473; CHECK-NEXT: vrev16.8 q2, q0474; CHECK-NEXT: vadd.i32 q0, q0, q2475; CHECK-NEXT: vadd.i32 q0, q0, q1476; CHECK-NEXT: vstrb.32 q0, [r1]477; CHECK-NEXT: bx lr478entry:479 %l1 = load <16 x i8>, ptr %src, align 1480 %s1 = shufflevector <16 x i8> %l1, <16 x i8> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>481 %s2 = shufflevector <16 x i8> %l1, <16 x i8> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>482 %s3 = shufflevector <16 x i8> %l1, <16 x i8> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>483 %s4 = shufflevector <16 x i8> %l1, <16 x i8> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>484 %a1 = add <4 x i8> %s1, %s2485 %a2 = add <4 x i8> %s3, %s4486 %a3 = add <4 x i8> %a1, %a2487 store <4 x i8> %a3, ptr %dst488 ret void489}490 491define void @vld4_v8i8(ptr %src, ptr %dst) {492; CHECK-LABEL: vld4_v8i8:493; CHECK: @ %bb.0: @ %entry494; CHECK-NEXT: .pad #32495; CHECK-NEXT: sub sp, #32496; CHECK-NEXT: vldrb.u8 q0, [r0, #16]497; CHECK-NEXT: mov r2, sp498; CHECK-NEXT: vshr.u16 q1, q0, #8499; CHECK-NEXT: vstrb.16 q1, [r2, #8]500; CHECK-NEXT: vldrb.u8 q2, [r0]501; CHECK-NEXT: add r0, sp, #16502; CHECK-NEXT: vshr.u16 q1, q2, #8503; CHECK-NEXT: vmov.u8 r3, q2[3]504; CHECK-NEXT: vstrb.16 q1, [r2]505; CHECK-NEXT: vmov.16 q1[0], r3506; CHECK-NEXT: vmov.u8 r3, q2[7]507; CHECK-NEXT: vstrb.16 q0, [r0, #8]508; CHECK-NEXT: vmov.16 q1[1], r3509; CHECK-NEXT: vmov.u8 r3, q2[11]510; CHECK-NEXT: vmov.16 q1[2], r3511; CHECK-NEXT: vmov.u8 r3, q2[15]512; CHECK-NEXT: vmov.16 q1[3], r3513; CHECK-NEXT: vmov.u8 r3, q0[3]514; CHECK-NEXT: vmov.16 q1[4], r3515; CHECK-NEXT: vmov.u8 r3, q0[7]516; CHECK-NEXT: vmov.16 q1[5], r3517; CHECK-NEXT: vmov.u8 r3, q0[11]518; CHECK-NEXT: vmov.16 q1[6], r3519; CHECK-NEXT: vmov.u8 r3, q0[15]520; CHECK-NEXT: vmov.16 q1[7], r3521; CHECK-NEXT: vmov.u8 r3, q2[2]522; CHECK-NEXT: vmov.16 q3[0], r3523; CHECK-NEXT: vmov.u8 r3, q2[6]524; CHECK-NEXT: vmov.16 q3[1], r3525; CHECK-NEXT: vmov.u8 r3, q2[10]526; CHECK-NEXT: vmov.16 q3[2], r3527; CHECK-NEXT: vmov.u8 r3, q2[14]528; CHECK-NEXT: vmov.16 q3[3], r3529; CHECK-NEXT: vmov.u8 r3, q0[2]530; CHECK-NEXT: vmov.16 q3[4], r3531; CHECK-NEXT: vmov.u8 r3, q0[6]532; CHECK-NEXT: vmov.16 q3[5], r3533; CHECK-NEXT: vmov.u8 r3, q0[10]534; CHECK-NEXT: vmov.16 q3[6], r3535; CHECK-NEXT: vmov.u8 r3, q0[14]536; CHECK-NEXT: vstrb.16 q2, [r0]537; CHECK-NEXT: vmov.16 q3[7], r3538; CHECK-NEXT: vadd.i16 q0, q3, q1539; CHECK-NEXT: vldrw.u32 q1, [r2]540; CHECK-NEXT: vldrw.u32 q2, [r0]541; CHECK-NEXT: vadd.i16 q1, q2, q1542; CHECK-NEXT: vadd.i16 q0, q1, q0543; CHECK-NEXT: vstrb.16 q0, [r1]544; CHECK-NEXT: add sp, #32545; CHECK-NEXT: bx lr546entry:547 %l1 = load <32 x i8>, ptr %src, align 1548 %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>549 %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>550 %s3 = shufflevector <32 x i8> %l1, <32 x i8> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>551 %s4 = shufflevector <32 x i8> %l1, <32 x i8> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>552 %a1 = add <8 x i8> %s1, %s2553 %a2 = add <8 x i8> %s3, %s4554 %a3 = add <8 x i8> %a1, %a2555 store <8 x i8> %a3, ptr %dst556 ret void557}558 559define void @vld4_v16i8(ptr %src, ptr %dst) {560; CHECK-LABEL: vld4_v16i8:561; CHECK: @ %bb.0: @ %entry562; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0]563; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0]564; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0]565; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]566; CHECK-NEXT: vadd.i8 q2, q2, q3567; CHECK-NEXT: vadd.i8 q0, q0, q1568; CHECK-NEXT: vadd.i8 q0, q0, q2569; CHECK-NEXT: vstrw.32 q0, [r1]570; CHECK-NEXT: bx lr571entry:572 %l1 = load <64 x i8>, ptr %src, align 1573 %s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>574 %s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>575 %s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>576 %s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>577 %a1 = add <16 x i8> %s1, %s2578 %a2 = add <16 x i8> %s3, %s4579 %a3 = add <16 x i8> %a1, %a2580 store <16 x i8> %a3, ptr %dst581 ret void582}583 584; i64585 586define void @vld4_v2i64(ptr %src, ptr %dst) {587; CHECK-LABEL: vld4_v2i64:588; CHECK: @ %bb.0: @ %entry589; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}590; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}591; CHECK-NEXT: .vsave {d8, d9}592; CHECK-NEXT: vpush {d8, d9}593; CHECK-NEXT: vldrw.u32 q0, [r0, #16]594; CHECK-NEXT: vldrw.u32 q2, [r0, #48]595; CHECK-NEXT: vldrw.u32 q4, [r0, #32]596; CHECK-NEXT: vmov.f32 s4, s2597; CHECK-NEXT: vmov.f32 s5, s3598; CHECK-NEXT: vmov.f32 s2, s8599; CHECK-NEXT: vmov.f32 s3, s9600; CHECK-NEXT: vmov lr, r12, d5601; CHECK-NEXT: vldrw.u32 q2, [r0]602; CHECK-NEXT: vmov r0, r8, d9603; CHECK-NEXT: vmov.f32 s12, s10604; CHECK-NEXT: vmov.f32 s13, s11605; CHECK-NEXT: vmov r2, r3, d1606; CHECK-NEXT: vmov.f32 s2, s16607; CHECK-NEXT: vmov.f32 s3, s17608; CHECK-NEXT: vmov r5, r6, d1609; CHECK-NEXT: adds.w r2, r2, lr610; CHECK-NEXT: adc.w r3, r3, r12611; CHECK-NEXT: vmov r4, r12, d2612; CHECK-NEXT: adds r0, r0, r5613; CHECK-NEXT: vmov r5, r7, d0614; CHECK-NEXT: adc.w r6, r6, r8615; CHECK-NEXT: adds r0, r0, r2616; CHECK-NEXT: adc.w lr, r6, r3617; CHECK-NEXT: vmov r3, r6, d6618; CHECK-NEXT: adds r5, r5, r4619; CHECK-NEXT: vmov r4, r2, d4620; CHECK-NEXT: adc.w r7, r7, r12621; CHECK-NEXT: adds r3, r3, r4622; CHECK-NEXT: adcs r2, r6623; CHECK-NEXT: adds r3, r3, r5624; CHECK-NEXT: adcs r2, r7625; CHECK-NEXT: vmov q0[2], q0[0], r3, r0626; CHECK-NEXT: vmov q0[3], q0[1], r2, lr627; CHECK-NEXT: vstrw.32 q0, [r1]628; CHECK-NEXT: vpop {d8, d9}629; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}630entry:631 %l1 = load <8 x i64>, ptr %src, align 8632 %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 0, i32 4>633 %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 1, i32 5>634 %s3 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 2, i32 6>635 %s4 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 3, i32 7>636 %a1 = add <2 x i64> %s1, %s2637 %a2 = add <2 x i64> %s3, %s4638 %a3 = add <2 x i64> %a1, %a2639 store <2 x i64> %a3, ptr %dst640 ret void641}642 643define void @vld4_v4i64(ptr %src, ptr %dst) {644; CHECK-LABEL: vld4_v4i64:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}647; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}648; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}649; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}650; CHECK-NEXT: .pad #16651; CHECK-NEXT: sub sp, #16652; CHECK-NEXT: vldrw.u32 q0, [r0]653; CHECK-NEXT: vldrw.u32 q5, [r0, #48]654; CHECK-NEXT: vldrw.u32 q4, [r0, #32]655; CHECK-NEXT: vldrw.u32 q6, [r0, #80]656; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill657; CHECK-NEXT: vmov.f32 s8, s2658; CHECK-NEXT: vmov.f32 s9, s3659; CHECK-NEXT: vldrw.u32 q1, [r0, #16]660; CHECK-NEXT: vmov.f32 s2, s20661; CHECK-NEXT: vldrw.u32 q7, [r0, #112]662; CHECK-NEXT: vmov.f32 s3, s21663; CHECK-NEXT: vmov r3, r2, d11664; CHECK-NEXT: vldrw.u32 q5, [r0, #96]665; CHECK-NEXT: vmov lr, r12, d9666; CHECK-NEXT: vmov.f32 s0, s26667; CHECK-NEXT: vmov.f32 s1, s27668; CHECK-NEXT: vmov.f32 s12, s6669; CHECK-NEXT: vmov.f32 s13, s7670; CHECK-NEXT: vmov r4, r5, d1671; CHECK-NEXT: vmov.f32 s2, s16672; CHECK-NEXT: vmov.f32 s3, s17673; CHECK-NEXT: vldrw.u32 q4, [r0, #64]674; CHECK-NEXT: vmov.f32 s6, s28675; CHECK-NEXT: vmov.f32 s7, s29676; CHECK-NEXT: vmov.f32 s10, s20677; CHECK-NEXT: vmov.f32 s11, s21678; CHECK-NEXT: vmov r6, r7, d1679; CHECK-NEXT: adds r3, r3, r4680; CHECK-NEXT: adc.w r4, r5, r2681; CHECK-NEXT: vmov r5, r8, d0682; CHECK-NEXT: vmov.f32 s0, s18683; CHECK-NEXT: vmov.f32 s1, s19684; CHECK-NEXT: adds.w r2, r6, lr685; CHECK-NEXT: vmov r6, r0, d12686; CHECK-NEXT: adc.w r7, r7, r12687; CHECK-NEXT: adds.w lr, r2, r3688; CHECK-NEXT: adc.w r12, r7, r4689; CHECK-NEXT: vmov r7, r4, d0690; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload691; CHECK-NEXT: adds r6, r6, r5692; CHECK-NEXT: vmov r5, r3, d8693; CHECK-NEXT: adc.w r0, r0, r8694; CHECK-NEXT: adds r7, r7, r5695; CHECK-NEXT: adcs r3, r4696; CHECK-NEXT: adds.w r9, r7, r6697; CHECK-NEXT: adc.w r8, r3, r0698; CHECK-NEXT: vmov r5, r4, d15699; CHECK-NEXT: vmov r3, r6, d3700; CHECK-NEXT: vmov r2, r0, d5701; CHECK-NEXT: adds r3, r3, r5702; CHECK-NEXT: adcs r6, r4703; CHECK-NEXT: vmov r5, r4, d11704; CHECK-NEXT: adds r2, r2, r5705; CHECK-NEXT: adcs r0, r4706; CHECK-NEXT: adds r2, r2, r3707; CHECK-NEXT: adc.w r10, r0, r6708; CHECK-NEXT: vmov r3, r4, d4709; CHECK-NEXT: vmov r5, r6, d0710; CHECK-NEXT: vmov r7, r0, d2711; CHECK-NEXT: vmov q1[2], q1[0], r9, r2712; CHECK-NEXT: vmov q1[3], q1[1], r8, r10713; CHECK-NEXT: vstrw.32 q1, [r1, #16]714; CHECK-NEXT: adds r3, r3, r5715; CHECK-NEXT: adcs r4, r6716; CHECK-NEXT: vmov r5, r6, d6717; CHECK-NEXT: adds r5, r5, r7718; CHECK-NEXT: adcs r0, r6719; CHECK-NEXT: adds r3, r3, r5720; CHECK-NEXT: vmov q0[2], q0[0], r3, lr721; CHECK-NEXT: adcs r0, r4722; CHECK-NEXT: vmov q0[3], q0[1], r0, r12723; CHECK-NEXT: vstrw.32 q0, [r1]724; CHECK-NEXT: add sp, #16725; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}726; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}727entry:728 %l1 = load <16 x i64>, ptr %src, align 8729 %s1 = shufflevector <16 x i64> %l1, <16 x i64> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>730 %s2 = shufflevector <16 x i64> %l1, <16 x i64> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>731 %s3 = shufflevector <16 x i64> %l1, <16 x i64> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>732 %s4 = shufflevector <16 x i64> %l1, <16 x i64> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>733 %a1 = add <4 x i64> %s1, %s2734 %a2 = add <4 x i64> %s3, %s4735 %a3 = add <4 x i64> %a1, %a2736 store <4 x i64> %a3, ptr %dst737 ret void738}739 740; f32741 742define void @vld4_v2f32(ptr %src, ptr %dst) {743; CHECK-LABEL: vld4_v2f32:744; CHECK: @ %bb.0: @ %entry745; CHECK-NEXT: vldrw.u32 q0, [r0, #16]746; CHECK-NEXT: vldrw.u32 q1, [r0]747; CHECK-NEXT: vmov.f32 s8, s7748; CHECK-NEXT: vmov.f32 s9, s3749; CHECK-NEXT: vmov.f32 s12, s6750; CHECK-NEXT: vmov.f32 s13, s2751; CHECK-NEXT: vadd.f32 q2, q3, q2752; CHECK-NEXT: vmov.f32 s12, s5753; CHECK-NEXT: vmov.f32 s13, s1754; CHECK-NEXT: vmov.f32 s5, s0755; CHECK-NEXT: vadd.f32 q0, q1, q3756; CHECK-NEXT: vadd.f32 q0, q0, q2757; CHECK-NEXT: vstmia r1, {s0, s1}758; CHECK-NEXT: bx lr759entry:760 %l1 = load <8 x float>, ptr %src, align 4761 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <2 x i32> <i32 0, i32 4>762 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <2 x i32> <i32 1, i32 5>763 %s3 = shufflevector <8 x float> %l1, <8 x float> undef, <2 x i32> <i32 2, i32 6>764 %s4 = shufflevector <8 x float> %l1, <8 x float> undef, <2 x i32> <i32 3, i32 7>765 %a1 = fadd <2 x float> %s1, %s2766 %a2 = fadd <2 x float> %s3, %s4767 %a3 = fadd <2 x float> %a1, %a2768 store <2 x float> %a3, ptr %dst769 ret void770}771 772define void @vld4_v4f32(ptr %src, ptr %dst) {773; CHECK-LABEL: vld4_v4f32:774; CHECK: @ %bb.0: @ %entry775; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]776; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]777; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]778; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]779; CHECK-NEXT: vadd.f32 q2, q2, q3780; CHECK-NEXT: vadd.f32 q0, q0, q1781; CHECK-NEXT: vadd.f32 q0, q0, q2782; CHECK-NEXT: vstrw.32 q0, [r1]783; CHECK-NEXT: bx lr784entry:785 %l1 = load <16 x float>, ptr %src, align 4786 %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>787 %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>788 %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>789 %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>790 %a1 = fadd <4 x float> %s1, %s2791 %a2 = fadd <4 x float> %s3, %s4792 %a3 = fadd <4 x float> %a1, %a2793 store <4 x float> %a3, ptr %dst794 ret void795}796 797define void @vld4_v8f32(ptr %src, ptr %dst) {798; CHECK-LABEL: vld4_v8f32:799; CHECK: @ %bb.0: @ %entry800; CHECK-NEXT: .vsave {d8, d9, d10, d11}801; CHECK-NEXT: vpush {d8, d9, d10, d11}802; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]803; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]804; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]805; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!806; CHECK-NEXT: vadd.f32 q4, q2, q3807; CHECK-NEXT: vadd.f32 q5, q0, q1808; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]809; CHECK-NEXT: vadd.f32 q4, q5, q4810; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]811; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]812; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]813; CHECK-NEXT: vstrw.32 q4, [r1]814; CHECK-NEXT: vadd.f32 q2, q2, q3815; CHECK-NEXT: vadd.f32 q0, q0, q1816; CHECK-NEXT: vadd.f32 q0, q0, q2817; CHECK-NEXT: vstrw.32 q0, [r1, #16]818; CHECK-NEXT: vpop {d8, d9, d10, d11}819; CHECK-NEXT: bx lr820entry:821 %l1 = load <32 x float>, ptr %src, align 4822 %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>823 %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>824 %s3 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>825 %s4 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>826 %a1 = fadd <8 x float> %s1, %s2827 %a2 = fadd <8 x float> %s3, %s4828 %a3 = fadd <8 x float> %a1, %a2829 store <8 x float> %a3, ptr %dst830 ret void831}832 833define void @vld4_v16f32(ptr %src, ptr %dst) {834; CHECK-LABEL: vld4_v16f32:835; CHECK: @ %bb.0: @ %entry836; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}837; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}838; CHECK-NEXT: .pad #32839; CHECK-NEXT: sub sp, #32840; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]841; CHECK-NEXT: mov r2, r0842; CHECK-NEXT: add.w r3, r0, #192843; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]844; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]845; CHECK-NEXT: adds r0, #128846; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!847; CHECK-NEXT: vadd.f32 q2, q2, q3848; CHECK-NEXT: vld40.32 {q3, q4, q5, q6}, [r3]849; CHECK-NEXT: vadd.f32 q0, q0, q1850; CHECK-NEXT: vld41.32 {q3, q4, q5, q6}, [r3]851; CHECK-NEXT: vadd.f32 q0, q0, q2852; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill853; CHECK-NEXT: vld42.32 {q3, q4, q5, q6}, [r3]854; CHECK-NEXT: vld43.32 {q3, q4, q5, q6}, [r3]855; CHECK-NEXT: vadd.f32 q1, q5, q6856; CHECK-NEXT: vadd.f32 q2, q3, q4857; CHECK-NEXT: vadd.f32 q0, q2, q1858; CHECK-NEXT: vld40.32 {q4, q5, q6, q7}, [r2]859; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill860; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]861; CHECK-NEXT: vld41.32 {q4, q5, q6, q7}, [r2]862; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]863; CHECK-NEXT: vld42.32 {q4, q5, q6, q7}, [r2]864; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]865; CHECK-NEXT: vld43.32 {q4, q5, q6, q7}, [r2]866; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]867; CHECK-NEXT: vadd.f32 q0, q0, q1868; CHECK-NEXT: vadd.f32 q2, q2, q3869; CHECK-NEXT: vadd.f32 q0, q0, q2870; CHECK-NEXT: vadd.f32 q1, q6, q7871; CHECK-NEXT: vadd.f32 q2, q4, q5872; CHECK-NEXT: vstrw.32 q0, [r1, #32]873; CHECK-NEXT: vadd.f32 q1, q2, q1874; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload875; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload876; CHECK-NEXT: vstrw.32 q1, [r1, #16]877; CHECK-NEXT: vstrw.32 q2, [r1, #48]878; CHECK-NEXT: vstrw.32 q0, [r1]879; CHECK-NEXT: add sp, #32880; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}881; CHECK-NEXT: bx lr882entry:883 %l1 = load <64 x float>, ptr %src, align 4884 %s1 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>885 %s2 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>886 %s3 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>887 %s4 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>888 %a1 = fadd <16 x float> %s1, %s2889 %a2 = fadd <16 x float> %s3, %s4890 %a3 = fadd <16 x float> %a1, %a2891 store <16 x float> %a3, ptr %dst892 ret void893}894 895define void @vld4_v4f32_align1(ptr %src, ptr %dst) {896; CHECK-LABEL: vld4_v4f32_align1:897; CHECK: @ %bb.0: @ %entry898; CHECK-NEXT: .vsave {d8, d9, d10, d11}899; CHECK-NEXT: vpush {d8, d9, d10, d11}900; CHECK-NEXT: vldrb.u8 q0, [r0, #48]901; CHECK-NEXT: vldrb.u8 q1, [r0, #32]902; CHECK-NEXT: vldrb.u8 q3, [r0, #16]903; CHECK-NEXT: vldrb.u8 q2, [r0]904; CHECK-NEXT: vmov.f32 s18, s7905; CHECK-NEXT: vmov.f32 s16, s11906; CHECK-NEXT: vmov.f32 s20, s10907; CHECK-NEXT: vmov.f32 s17, s15908; CHECK-NEXT: vmov.f32 s19, s3909; CHECK-NEXT: vmov.f32 s21, s14910; CHECK-NEXT: vmov.f32 s22, s6911; CHECK-NEXT: vmov.f32 s23, s2912; CHECK-NEXT: vadd.f32 q4, q5, q4913; CHECK-NEXT: vmov.f32 s20, s9914; CHECK-NEXT: vmov.f32 s21, s13915; CHECK-NEXT: vmov.f32 s22, s5916; CHECK-NEXT: vmov.f32 s23, s1917; CHECK-NEXT: vmov.f32 s9, s12918; CHECK-NEXT: vmov.f32 s10, s4919; CHECK-NEXT: vmov.f32 s11, s0920; CHECK-NEXT: vadd.f32 q0, q2, q5921; CHECK-NEXT: vadd.f32 q0, q0, q4922; CHECK-NEXT: vstrw.32 q0, [r1]923; CHECK-NEXT: vpop {d8, d9, d10, d11}924; CHECK-NEXT: bx lr925entry:926 %l1 = load <16 x float>, ptr %src, align 1927 %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>928 %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>929 %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>930 %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>931 %a1 = fadd <4 x float> %s1, %s2932 %a2 = fadd <4 x float> %s3, %s4933 %a3 = fadd <4 x float> %a1, %a2934 store <4 x float> %a3, ptr %dst935 ret void936}937 938; f16939 940define void @vld4_v2f16(ptr %src, ptr %dst) {941; CHECK-LABEL: vld4_v2f16:942; CHECK: @ %bb.0: @ %entry943; CHECK-NEXT: vldrh.u16 q0, [r0]944; CHECK-NEXT: vmovx.f16 s8, s1945; CHECK-NEXT: vmovx.f16 s4, s3946; CHECK-NEXT: vins.f16 s8, s4947; CHECK-NEXT: vmovx.f16 s12, s0948; CHECK-NEXT: vmovx.f16 s4, s2949; CHECK-NEXT: vins.f16 s1, s3950; CHECK-NEXT: vins.f16 s12, s4951; CHECK-NEXT: vmov.f32 s4, s1952; CHECK-NEXT: vins.f16 s0, s2953; CHECK-NEXT: vadd.f16 q1, q1, q2954; CHECK-NEXT: vadd.f16 q0, q0, q3955; CHECK-NEXT: vadd.f16 q0, q0, q1956; CHECK-NEXT: vmov r0, s0957; CHECK-NEXT: str r0, [r1]958; CHECK-NEXT: bx lr959entry:960 %l1 = load <8 x half>, ptr %src, align 2961 %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 0, i32 4>962 %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 1, i32 5>963 %s3 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 2, i32 6>964 %s4 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 3, i32 7>965 %a1 = fadd <2 x half> %s1, %s2966 %a2 = fadd <2 x half> %s3, %s4967 %a3 = fadd <2 x half> %a1, %a2968 store <2 x half> %a3, ptr %dst969 ret void970}971 972define void @vld4_v4f16(ptr %src, ptr %dst) {973; CHECK-LABEL: vld4_v4f16:974; CHECK: @ %bb.0: @ %entry975; CHECK-NEXT: .vsave {d8}976; CHECK-NEXT: vpush {d8}977; CHECK-NEXT: vldrh.u16 q0, [r0]978; CHECK-NEXT: vldrh.u16 q2, [r0, #16]979; CHECK-NEXT: vmovx.f16 s4, s0980; CHECK-NEXT: vmovx.f16 s6, s2981; CHECK-NEXT: vins.f16 s0, s2982; CHECK-NEXT: vmovx.f16 s12, s1983; CHECK-NEXT: vmovx.f16 s2, s3984; CHECK-NEXT: vins.f16 s4, s6985; CHECK-NEXT: vmovx.f16 s5, s8986; CHECK-NEXT: vmovx.f16 s6, s10987; CHECK-NEXT: vins.f16 s12, s2988; CHECK-NEXT: vmovx.f16 s13, s9989; CHECK-NEXT: vmovx.f16 s2, s11990; CHECK-NEXT: vins.f16 s1, s3991; CHECK-NEXT: vins.f16 s9, s11992; CHECK-NEXT: vins.f16 s8, s10993; CHECK-NEXT: vmov.f32 s16, s1994; CHECK-NEXT: vins.f16 s5, s6995; CHECK-NEXT: vins.f16 s13, s2996; CHECK-NEXT: vmov.f32 s1, s8997; CHECK-NEXT: vmov.f32 s17, s9998; CHECK-NEXT: vadd.f16 q0, q0, q1999; CHECK-NEXT: vadd.f16 q3, q4, q31000; CHECK-NEXT: vadd.f16 q0, q0, q31001; CHECK-NEXT: vmov r0, r2, d01002; CHECK-NEXT: strd r0, r2, [r1]1003; CHECK-NEXT: vpop {d8}1004; CHECK-NEXT: bx lr1005entry:1006 %l1 = load <16 x half>, ptr %src, align 21007 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>1008 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>1009 %s3 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>1010 %s4 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>1011 %a1 = fadd <4 x half> %s1, %s21012 %a2 = fadd <4 x half> %s3, %s41013 %a3 = fadd <4 x half> %a1, %a21014 store <4 x half> %a3, ptr %dst1015 ret void1016}1017 1018define void @vld4_v8f16(ptr %src, ptr %dst) {1019; CHECK-LABEL: vld4_v8f16:1020; CHECK: @ %bb.0: @ %entry1021; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]1022; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]1023; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]1024; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]1025; CHECK-NEXT: vadd.f16 q2, q2, q31026; CHECK-NEXT: vadd.f16 q0, q0, q11027; CHECK-NEXT: vadd.f16 q0, q0, q21028; CHECK-NEXT: vstrw.32 q0, [r1]1029; CHECK-NEXT: bx lr1030entry:1031 %l1 = load <32 x half>, ptr %src, align 21032 %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>1033 %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>1034 %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>1035 %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>1036 %a1 = fadd <8 x half> %s1, %s21037 %a2 = fadd <8 x half> %s3, %s41038 %a3 = fadd <8 x half> %a1, %a21039 store <8 x half> %a3, ptr %dst1040 ret void1041}1042 1043define void @vld4_v16f16(ptr %src, ptr %dst) {1044; CHECK-LABEL: vld4_v16f16:1045; CHECK: @ %bb.0: @ %entry1046; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1047; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}1048; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]1049; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]1050; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]1051; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!1052; CHECK-NEXT: vld40.16 {q4, q5, q6, q7}, [r0]1053; CHECK-NEXT: vadd.f16 q2, q2, q31054; CHECK-NEXT: vadd.f16 q0, q0, q11055; CHECK-NEXT: vld41.16 {q4, q5, q6, q7}, [r0]1056; CHECK-NEXT: vadd.f16 q0, q0, q21057; CHECK-NEXT: vld42.16 {q4, q5, q6, q7}, [r0]1058; CHECK-NEXT: vld43.16 {q4, q5, q6, q7}, [r0]1059; CHECK-NEXT: vstrw.32 q0, [r1]1060; CHECK-NEXT: vadd.f16 q6, q6, q71061; CHECK-NEXT: vadd.f16 q4, q4, q51062; CHECK-NEXT: vadd.f16 q4, q4, q61063; CHECK-NEXT: vstrw.32 q4, [r1, #16]1064; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}1065; CHECK-NEXT: bx lr1066entry:1067 %l1 = load <64 x half>, ptr %src, align 21068 %s1 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>1069 %s2 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>1070 %s3 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>1071 %s4 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>1072 %a1 = fadd <16 x half> %s1, %s21073 %a2 = fadd <16 x half> %s3, %s41074 %a3 = fadd <16 x half> %a1, %a21075 store <16 x half> %a3, ptr %dst1076 ret void1077}1078 1079define void @vld4_v8f16_align1(ptr %src, ptr %dst) {1080; CHECK-LABEL: vld4_v8f16_align1:1081; CHECK: @ %bb.0: @ %entry1082; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}1083; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}1084; CHECK-NEXT: vldrb.u8 q0, [r0, #32]1085; CHECK-NEXT: vldrb.u8 q4, [r0, #16]1086; CHECK-NEXT: vmovx.f16 s14, s11087; CHECK-NEXT: vmovx.f16 s4, s31088; CHECK-NEXT: vins.f16 s14, s41089; CHECK-NEXT: vldrb.u8 q1, [r0, #48]1090; CHECK-NEXT: vins.f16 s1, s31091; CHECK-NEXT: vmovx.f16 s22, s01092; CHECK-NEXT: vmovx.f16 s15, s51093; CHECK-NEXT: vmovx.f16 s8, s71094; CHECK-NEXT: vins.f16 s15, s81095; CHECK-NEXT: vldrb.u8 q2, [r0]1096; CHECK-NEXT: vmovx.f16 s3, s21097; CHECK-NEXT: vmovx.f16 s23, s41098; CHECK-NEXT: vmovx.f16 s12, s91099; CHECK-NEXT: vmovx.f16 s13, s111100; CHECK-NEXT: vins.f16 s12, s131101; CHECK-NEXT: vmovx.f16 s13, s171102; CHECK-NEXT: vmovx.f16 s20, s191103; CHECK-NEXT: vins.f16 s22, s31104; CHECK-NEXT: vmovx.f16 s3, s61105; CHECK-NEXT: vins.f16 s13, s201106; CHECK-NEXT: vins.f16 s23, s31107; CHECK-NEXT: vmovx.f16 s20, s81108; CHECK-NEXT: vmovx.f16 s3, s101109; CHECK-NEXT: vins.f16 s5, s71110; CHECK-NEXT: vins.f16 s9, s111111; CHECK-NEXT: vins.f16 s17, s191112; CHECK-NEXT: vins.f16 s20, s31113; CHECK-NEXT: vmovx.f16 s21, s161114; CHECK-NEXT: vmovx.f16 s3, s181115; CHECK-NEXT: vins.f16 s4, s61116; CHECK-NEXT: vins.f16 s0, s21117; CHECK-NEXT: vins.f16 s16, s181118; CHECK-NEXT: vins.f16 s8, s101119; CHECK-NEXT: vmov.f32 s24, s91120; CHECK-NEXT: vins.f16 s21, s31121; CHECK-NEXT: vmov.f32 s26, s11122; CHECK-NEXT: vmov.f32 s25, s171123; CHECK-NEXT: vmov.f32 s27, s51124; CHECK-NEXT: vmov.f32 s10, s01125; CHECK-NEXT: vadd.f16 q3, q6, q31126; CHECK-NEXT: vmov.f32 s9, s161127; CHECK-NEXT: vmov.f32 s11, s41128; CHECK-NEXT: vadd.f16 q0, q2, q51129; CHECK-NEXT: vadd.f16 q0, q0, q31130; CHECK-NEXT: vstrw.32 q0, [r1]1131; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}1132; CHECK-NEXT: bx lr1133entry:1134 %l1 = load <32 x half>, ptr %src, align 11135 %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>1136 %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>1137 %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>1138 %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>1139 %a1 = fadd <8 x half> %s1, %s21140 %a2 = fadd <8 x half> %s3, %s41141 %a3 = fadd <8 x half> %a1, %a21142 store <8 x half> %a3, ptr %dst1143 ret void1144}1145 1146; f641147 1148define void @vld4_v2f64(ptr %src, ptr %dst) {1149; CHECK-LABEL: vld4_v2f64:1150; CHECK: @ %bb.0: @ %entry1151; CHECK-NEXT: vldrw.u32 q0, [r0, #48]1152; CHECK-NEXT: vldrw.u32 q1, [r0, #32]1153; CHECK-NEXT: vldrw.u32 q2, [r0]1154; CHECK-NEXT: vadd.f64 d0, d0, d11155; CHECK-NEXT: vadd.f64 d1, d2, d31156; CHECK-NEXT: vldrw.u32 q1, [r0, #16]1157; CHECK-NEXT: vadd.f64 d2, d2, d31158; CHECK-NEXT: vadd.f64 d3, d4, d51159; CHECK-NEXT: vadd.f64 d1, d1, d01160; CHECK-NEXT: vadd.f64 d0, d3, d21161; CHECK-NEXT: vstrw.32 q0, [r1]1162; CHECK-NEXT: bx lr1163entry:1164 %l1 = load <8 x double>, ptr %src, align 81165 %s1 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 0, i32 4>1166 %s2 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 1, i32 5>1167 %s3 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 2, i32 6>1168 %s4 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 3, i32 7>1169 %a1 = fadd <2 x double> %s1, %s21170 %a2 = fadd <2 x double> %s3, %s41171 %a3 = fadd <2 x double> %a1, %a21172 store <2 x double> %a3, ptr %dst1173 ret void1174}1175 1176define void @vld4_v4f64(ptr %src, ptr %dst) {1177; CHECK-LABEL: vld4_v4f64:1178; CHECK: @ %bb.0: @ %entry1179; CHECK-NEXT: .vsave {d8, d9}1180; CHECK-NEXT: vpush {d8, d9}1181; CHECK-NEXT: vldrw.u32 q0, [r0, #112]1182; CHECK-NEXT: vldrw.u32 q1, [r0, #96]1183; CHECK-NEXT: vldrw.u32 q2, [r0, #64]1184; CHECK-NEXT: vldrw.u32 q3, [r0, #32]1185; CHECK-NEXT: vadd.f64 d0, d0, d11186; CHECK-NEXT: vldrw.u32 q4, [r0]1187; CHECK-NEXT: vadd.f64 d1, d2, d31188; CHECK-NEXT: vldrw.u32 q1, [r0, #80]1189; CHECK-NEXT: vadd.f64 d2, d2, d31190; CHECK-NEXT: vadd.f64 d3, d4, d51191; CHECK-NEXT: vldrw.u32 q2, [r0, #48]1192; CHECK-NEXT: vadd.f64 d4, d4, d51193; CHECK-NEXT: vadd.f64 d5, d6, d71194; CHECK-NEXT: vldrw.u32 q3, [r0, #16]1195; CHECK-NEXT: vadd.f64 d6, d6, d71196; CHECK-NEXT: vadd.f64 d7, d8, d91197; CHECK-NEXT: vadd.f64 d1, d1, d01198; CHECK-NEXT: vadd.f64 d0, d3, d21199; CHECK-NEXT: vadd.f64 d3, d5, d41200; CHECK-NEXT: vstrw.32 q0, [r1, #16]1201; CHECK-NEXT: vadd.f64 d2, d7, d61202; CHECK-NEXT: vstrw.32 q1, [r1]1203; CHECK-NEXT: vpop {d8, d9}1204; CHECK-NEXT: bx lr1205entry:1206 %l1 = load <16 x double>, ptr %src, align 81207 %s1 = shufflevector <16 x double> %l1, <16 x double> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>1208 %s2 = shufflevector <16 x double> %l1, <16 x double> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>1209 %s3 = shufflevector <16 x double> %l1, <16 x double> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>1210 %s4 = shufflevector <16 x double> %l1, <16 x double> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>1211 %a1 = fadd <4 x double> %s1, %s21212 %a2 = fadd <4 x double> %s3, %s41213 %a3 = fadd <4 x double> %a1, %a21214 store <4 x double> %a3, ptr %dst1215 ret void1216}1217