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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc zeroext i8 @uminv16i8(<16 x i8> %vec, i8 zeroext %min) {5; CHECK-LABEL: uminv16i8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vminv.u8 r0, q08; CHECK-NEXT: uxtb r0, r09; CHECK-NEXT: bx lr10 %x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)11 %cmp = icmp ult i8 %x, %min12 %1 = select i1 %cmp, i8 %x, i8 %min13 ret i8 %114}15 16define arm_aapcs_vfpcc zeroext i16 @uminv8i16(<8 x i16> %vec, i16 zeroext %min) {17; CHECK-LABEL: uminv8i16:18; CHECK: @ %bb.0:19; CHECK-NEXT: vminv.u16 r0, q020; CHECK-NEXT: uxth r0, r021; CHECK-NEXT: bx lr22 %x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)23 %cmp = icmp ult i16 %x, %min24 %1 = select i1 %cmp, i16 %x, i16 %min25 ret i16 %126}27 28define arm_aapcs_vfpcc i32 @uminv4i32(<4 x i32> %vec, i32 %min) {29; CHECK-LABEL: uminv4i32:30; CHECK: @ %bb.0:31; CHECK-NEXT: vminv.u32 r0, q032; CHECK-NEXT: bx lr33 %x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)34 %cmp = icmp ult i32 %x, %min35 %1 = select i1 %cmp, i32 %x, i32 %min36 ret i32 %137}38 39define arm_aapcs_vfpcc signext i8 @sminv16i8(<16 x i8> %vec, i8 signext %min) {40; CHECK-LABEL: sminv16i8:41; CHECK: @ %bb.0:42; CHECK-NEXT: vminv.s8 r0, q043; CHECK-NEXT: sxtb r0, r044; CHECK-NEXT: bx lr45 %x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)46 %cmp = icmp slt i8 %x, %min47 %1 = select i1 %cmp, i8 %x, i8 %min48 ret i8 %149}50 51define arm_aapcs_vfpcc signext i16 @sminv8i16(<8 x i16> %vec, i16 signext %min) {52; CHECK-LABEL: sminv8i16:53; CHECK: @ %bb.0:54; CHECK-NEXT: vminv.s16 r0, q055; CHECK-NEXT: sxth r0, r056; CHECK-NEXT: bx lr57 %x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)58 %cmp = icmp slt i16 %x, %min59 %1 = select i1 %cmp, i16 %x, i16 %min60 ret i16 %161}62 63define arm_aapcs_vfpcc i32 @sminv4i32(<4 x i32> %vec, i32 %min) {64; CHECK-LABEL: sminv4i32:65; CHECK: @ %bb.0:66; CHECK-NEXT: vminv.s32 r0, q067; CHECK-NEXT: bx lr68 %x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)69 %cmp = icmp slt i32 %x, %min70 %1 = select i1 %cmp, i32 %x, i32 %min71 ret i32 %172}73 74define arm_aapcs_vfpcc zeroext i8 @umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {75; CHECK-LABEL: umaxv16i8:76; CHECK: @ %bb.0:77; CHECK-NEXT: vmaxv.u8 r0, q078; CHECK-NEXT: uxtb r0, r079; CHECK-NEXT: bx lr80 %x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)81 %cmp = icmp ugt i8 %x, %max82 %1 = select i1 %cmp, i8 %x, i8 %max83 ret i8 %184}85 86define arm_aapcs_vfpcc zeroext i16 @umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {87; CHECK-LABEL: umaxv8i16:88; CHECK: @ %bb.0:89; CHECK-NEXT: vmaxv.u16 r0, q090; CHECK-NEXT: uxth r0, r091; CHECK-NEXT: bx lr92 %x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)93 %cmp = icmp ugt i16 %x, %max94 %1 = select i1 %cmp, i16 %x, i16 %max95 ret i16 %196}97 98define arm_aapcs_vfpcc i32 @umaxv4i32(<4 x i32> %vec, i32 %max) {99; CHECK-LABEL: umaxv4i32:100; CHECK: @ %bb.0:101; CHECK-NEXT: vmaxv.u32 r0, q0102; CHECK-NEXT: bx lr103 %x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)104 %cmp = icmp ugt i32 %x, %max105 %1 = select i1 %cmp, i32 %x, i32 %max106 ret i32 %1107}108 109define arm_aapcs_vfpcc signext i8 @smaxv16i8(<16 x i8> %vec, i8 signext %max) {110; CHECK-LABEL: smaxv16i8:111; CHECK: @ %bb.0:112; CHECK-NEXT: vmaxv.s8 r0, q0113; CHECK-NEXT: sxtb r0, r0114; CHECK-NEXT: bx lr115 %x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)116 %cmp = icmp sgt i8 %x, %max117 %1 = select i1 %cmp, i8 %x, i8 %max118 ret i8 %1119}120 121define arm_aapcs_vfpcc signext i16 @smaxv8i16(<8 x i16> %vec, i16 signext %max) {122; CHECK-LABEL: smaxv8i16:123; CHECK: @ %bb.0:124; CHECK-NEXT: vmaxv.s16 r0, q0125; CHECK-NEXT: sxth r0, r0126; CHECK-NEXT: bx lr127 %x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)128 %cmp = icmp sgt i16 %x, %max129 %1 = select i1 %cmp, i16 %x, i16 %max130 ret i16 %1131}132 133define arm_aapcs_vfpcc i32 @smaxv4i32(<4 x i32> %vec, i32 %max) {134; CHECK-LABEL: smaxv4i32:135; CHECK: @ %bb.0:136; CHECK-NEXT: vmaxv.s32 r0, q0137; CHECK-NEXT: bx lr138 %x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)139 %cmp = icmp sgt i32 %x, %max140 %1 = select i1 %cmp, i32 %x, i32 %max141 ret i32 %1142}143 144define arm_aapcs_vfpcc zeroext i8 @commute_uminv16i8(<16 x i8> %vec, i8 zeroext %min) {145; CHECK-LABEL: commute_uminv16i8:146; CHECK: @ %bb.0:147; CHECK-NEXT: vminv.u8 r0, q0148; CHECK-NEXT: uxtb r0, r0149; CHECK-NEXT: bx lr150 %x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)151 %cmp = icmp ult i8 %min, %x152 %1 = select i1 %cmp, i8 %min, i8 %x153 ret i8 %1154}155 156define arm_aapcs_vfpcc zeroext i16 @commute_uminv8i16(<8 x i16> %vec, i16 zeroext %min) {157; CHECK-LABEL: commute_uminv8i16:158; CHECK: @ %bb.0:159; CHECK-NEXT: vminv.u16 r0, q0160; CHECK-NEXT: uxth r0, r0161; CHECK-NEXT: bx lr162 %x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)163 %cmp = icmp ult i16 %min, %x164 %1 = select i1 %cmp, i16 %min, i16 %x165 ret i16 %1166}167 168define arm_aapcs_vfpcc i32 @commute_uminv4i32(<4 x i32> %vec, i32 %min) {169; CHECK-LABEL: commute_uminv4i32:170; CHECK: @ %bb.0:171; CHECK-NEXT: vminv.u32 r0, q0172; CHECK-NEXT: bx lr173 %x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)174 %cmp = icmp ult i32 %min, %x175 %1 = select i1 %cmp, i32 %min, i32 %x176 ret i32 %1177}178 179define arm_aapcs_vfpcc signext i8 @commute_sminv16i8(<16 x i8> %vec, i8 signext %min) {180; CHECK-LABEL: commute_sminv16i8:181; CHECK: @ %bb.0:182; CHECK-NEXT: vminv.s8 r0, q0183; CHECK-NEXT: sxtb r0, r0184; CHECK-NEXT: bx lr185 %x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)186 %cmp = icmp slt i8 %min, %x187 %1 = select i1 %cmp, i8 %min, i8 %x188 ret i8 %1189}190 191define arm_aapcs_vfpcc signext i16 @commute_sminv8i16(<8 x i16> %vec, i16 signext %min) {192; CHECK-LABEL: commute_sminv8i16:193; CHECK: @ %bb.0:194; CHECK-NEXT: vminv.s16 r0, q0195; CHECK-NEXT: sxth r0, r0196; CHECK-NEXT: bx lr197 %x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)198 %cmp = icmp slt i16 %min, %x199 %1 = select i1 %cmp, i16 %min, i16 %x200 ret i16 %1201}202 203define arm_aapcs_vfpcc i32 @commute_sminv4i32(<4 x i32> %vec, i32 %min) {204; CHECK-LABEL: commute_sminv4i32:205; CHECK: @ %bb.0:206; CHECK-NEXT: vminv.s32 r0, q0207; CHECK-NEXT: bx lr208 %x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)209 %cmp = icmp slt i32 %min, %x210 %1 = select i1 %cmp, i32 %min, i32 %x211 ret i32 %1212}213 214define arm_aapcs_vfpcc zeroext i8 @commute_umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {215; CHECK-LABEL: commute_umaxv16i8:216; CHECK: @ %bb.0:217; CHECK-NEXT: vmaxv.u8 r0, q0218; CHECK-NEXT: uxtb r0, r0219; CHECK-NEXT: bx lr220 %x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)221 %cmp = icmp ugt i8 %max, %x222 %1 = select i1 %cmp, i8 %max, i8 %x223 ret i8 %1224}225 226define arm_aapcs_vfpcc zeroext i16 @commute_umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {227; CHECK-LABEL: commute_umaxv8i16:228; CHECK: @ %bb.0:229; CHECK-NEXT: vmaxv.u16 r0, q0230; CHECK-NEXT: uxth r0, r0231; CHECK-NEXT: bx lr232 %x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)233 %cmp = icmp ugt i16 %max, %x234 %1 = select i1 %cmp, i16 %max, i16 %x235 ret i16 %1236}237 238define arm_aapcs_vfpcc i32 @commute_umaxv4i32(<4 x i32> %vec, i32 %max) {239; CHECK-LABEL: commute_umaxv4i32:240; CHECK: @ %bb.0:241; CHECK-NEXT: vmaxv.u32 r0, q0242; CHECK-NEXT: bx lr243 %x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)244 %cmp = icmp ugt i32 %max, %x245 %1 = select i1 %cmp, i32 %max, i32 %x246 ret i32 %1247}248 249define arm_aapcs_vfpcc signext i8 @commute_smaxv16i8(<16 x i8> %vec, i8 signext %max) {250; CHECK-LABEL: commute_smaxv16i8:251; CHECK: @ %bb.0:252; CHECK-NEXT: vmaxv.s8 r0, q0253; CHECK-NEXT: sxtb r0, r0254; CHECK-NEXT: bx lr255 %x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)256 %cmp = icmp sgt i8 %max, %x257 %1 = select i1 %cmp, i8 %max, i8 %x258 ret i8 %1259}260 261define arm_aapcs_vfpcc signext i16 @commute_smaxv8i16(<8 x i16> %vec, i16 signext %max) {262; CHECK-LABEL: commute_smaxv8i16:263; CHECK: @ %bb.0:264; CHECK-NEXT: vmaxv.s16 r0, q0265; CHECK-NEXT: sxth r0, r0266; CHECK-NEXT: bx lr267 %x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)268 %cmp = icmp sgt i16 %max, %x269 %1 = select i1 %cmp, i16 %max, i16 %x270 ret i16 %1271}272 273define arm_aapcs_vfpcc i32 @commute_smaxv4i32(<4 x i32> %vec, i32 %max) {274; CHECK-LABEL: commute_smaxv4i32:275; CHECK: @ %bb.0:276; CHECK-NEXT: vmaxv.s32 r0, q0277; CHECK-NEXT: bx lr278 %x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)279 %cmp = icmp sgt i32 %max, %x280 %1 = select i1 %cmp, i32 %max, i32 %x281 ret i32 %1282}283 284define arm_aapcs_vfpcc signext i8 @mismatch_smaxv16i8(<16 x i8> %vec, i8 signext %max) {285; CHECK-LABEL: mismatch_smaxv16i8:286; CHECK: @ %bb.0:287; CHECK-NEXT: mvn r1, #127288; CHECK-NEXT: vmaxv.s8 r1, q0289; CHECK-NEXT: sxtb r2, r1290; CHECK-NEXT: cmp r2, r0291; CHECK-NEXT: csel r0, r0, r1, gt292; CHECK-NEXT: sxtb r0, r0293; CHECK-NEXT: bx lr294 %x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)295 %cmp = icmp sgt i8 %x, %max296 %1 = select i1 %cmp, i8 %max, i8 %x297 ret i8 %1298}299 300define arm_aapcs_vfpcc signext i8 @mismatch2_smaxv16i8(<16 x i8> %vec, i8 signext %max) {301; CHECK-LABEL: mismatch2_smaxv16i8:302; CHECK: @ %bb.0:303; CHECK-NEXT: mvn r1, #127304; CHECK-NEXT: vmaxv.s8 r1, q0305; CHECK-NEXT: sxtb r2, r1306; CHECK-NEXT: cmp r0, r2307; CHECK-NEXT: csel r0, r1, r0, gt308; CHECK-NEXT: sxtb r0, r0309; CHECK-NEXT: bx lr310 %x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)311 %cmp = icmp sgt i8 %max, %x312 %1 = select i1 %cmp, i8 %x, i8 %max313 ret i8 %1314}315 316define arm_aapcs_vfpcc zeroext i8 @inverted_uminv16i8(<16 x i8> %vec, i8 zeroext %min) {317; CHECK-LABEL: inverted_uminv16i8:318; CHECK: @ %bb.0:319; CHECK-NEXT: vminv.u8 r0, q0320; CHECK-NEXT: uxtb r0, r0321; CHECK-NEXT: bx lr322 %x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)323 %cmp = icmp ugt i8 %x, %min324 %1 = select i1 %cmp, i8 %min, i8 %x325 ret i8 %1326}327 328define arm_aapcs_vfpcc zeroext i16 @inverted_uminv8i16(<8 x i16> %vec, i16 zeroext %min) {329; CHECK-LABEL: inverted_uminv8i16:330; CHECK: @ %bb.0:331; CHECK-NEXT: vminv.u16 r0, q0332; CHECK-NEXT: uxth r0, r0333; CHECK-NEXT: bx lr334 %x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)335 %cmp = icmp ugt i16 %x, %min336 %1 = select i1 %cmp, i16 %min, i16 %x337 ret i16 %1338}339 340define arm_aapcs_vfpcc i32 @inverted_uminv4i32(<4 x i32> %vec, i32 %min) {341; CHECK-LABEL: inverted_uminv4i32:342; CHECK: @ %bb.0:343; CHECK-NEXT: vminv.u32 r0, q0344; CHECK-NEXT: bx lr345 %x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)346 %cmp = icmp ugt i32 %x, %min347 %1 = select i1 %cmp, i32 %min, i32 %x348 ret i32 %1349}350 351define arm_aapcs_vfpcc signext i8 @inverted_sminv16i8(<16 x i8> %vec, i8 signext %min) {352; CHECK-LABEL: inverted_sminv16i8:353; CHECK: @ %bb.0:354; CHECK-NEXT: vminv.s8 r0, q0355; CHECK-NEXT: sxtb r0, r0356; CHECK-NEXT: bx lr357 %x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)358 %cmp = icmp sgt i8 %x, %min359 %1 = select i1 %cmp, i8 %min, i8 %x360 ret i8 %1361}362 363define arm_aapcs_vfpcc signext i16 @inverted_sminv8i16(<8 x i16> %vec, i16 signext %min) {364; CHECK-LABEL: inverted_sminv8i16:365; CHECK: @ %bb.0:366; CHECK-NEXT: vminv.s16 r0, q0367; CHECK-NEXT: sxth r0, r0368; CHECK-NEXT: bx lr369 %x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)370 %cmp = icmp sgt i16 %x, %min371 %1 = select i1 %cmp, i16 %min, i16 %x372 ret i16 %1373}374 375define arm_aapcs_vfpcc i32 @inverted_sminv4i32(<4 x i32> %vec, i32 %min) {376; CHECK-LABEL: inverted_sminv4i32:377; CHECK: @ %bb.0:378; CHECK-NEXT: vminv.s32 r0, q0379; CHECK-NEXT: bx lr380 %x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)381 %cmp = icmp sgt i32 %x, %min382 %1 = select i1 %cmp, i32 %min, i32 %x383 ret i32 %1384}385 386define arm_aapcs_vfpcc zeroext i8 @inverted_umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {387; CHECK-LABEL: inverted_umaxv16i8:388; CHECK: @ %bb.0:389; CHECK-NEXT: vmaxv.u8 r0, q0390; CHECK-NEXT: uxtb r0, r0391; CHECK-NEXT: bx lr392 %x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)393 %cmp = icmp ult i8 %x, %max394 %1 = select i1 %cmp, i8 %max, i8 %x395 ret i8 %1396}397 398define arm_aapcs_vfpcc zeroext i16 @inverted_umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {399; CHECK-LABEL: inverted_umaxv8i16:400; CHECK: @ %bb.0:401; CHECK-NEXT: vmaxv.u16 r0, q0402; CHECK-NEXT: uxth r0, r0403; CHECK-NEXT: bx lr404 %x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)405 %cmp = icmp ult i16 %x, %max406 %1 = select i1 %cmp, i16 %max, i16 %x407 ret i16 %1408}409 410define arm_aapcs_vfpcc i32 @inverted_umaxv4i32(<4 x i32> %vec, i32 %max) {411; CHECK-LABEL: inverted_umaxv4i32:412; CHECK: @ %bb.0:413; CHECK-NEXT: vmaxv.u32 r0, q0414; CHECK-NEXT: bx lr415 %x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)416 %cmp = icmp ult i32 %x, %max417 %1 = select i1 %cmp, i32 %max, i32 %x418 ret i32 %1419}420 421define arm_aapcs_vfpcc signext i8 @inverted_smaxv16i8(<16 x i8> %vec, i8 signext %max) {422; CHECK-LABEL: inverted_smaxv16i8:423; CHECK: @ %bb.0:424; CHECK-NEXT: vmaxv.s8 r0, q0425; CHECK-NEXT: sxtb r0, r0426; CHECK-NEXT: bx lr427 %x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)428 %cmp = icmp slt i8 %x, %max429 %1 = select i1 %cmp, i8 %max, i8 %x430 ret i8 %1431}432 433define arm_aapcs_vfpcc signext i16 @inverted_smaxv8i16(<8 x i16> %vec, i16 signext %max) {434; CHECK-LABEL: inverted_smaxv8i16:435; CHECK: @ %bb.0:436; CHECK-NEXT: vmaxv.s16 r0, q0437; CHECK-NEXT: sxth r0, r0438; CHECK-NEXT: bx lr439 %x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)440 %cmp = icmp slt i16 %x, %max441 %1 = select i1 %cmp, i16 %max, i16 %x442 ret i16 %1443}444 445define arm_aapcs_vfpcc i32 @inverted_smaxv4i32(<4 x i32> %vec, i32 %max) {446; CHECK-LABEL: inverted_smaxv4i32:447; CHECK: @ %bb.0:448; CHECK-NEXT: vmaxv.s32 r0, q0449; CHECK-NEXT: bx lr450 %x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)451 %cmp = icmp slt i32 %x, %max452 %1 = select i1 %cmp, i32 %max, i32 %x453 ret i32 %1454}455 456define arm_aapcs_vfpcc signext i16 @trunc_and_sext(<8 x i16> %vec, i32 %max) #1 {457; CHECK-LABEL: trunc_and_sext:458; CHECK: @ %bb.0:459; CHECK-NEXT: movw r1, #32768460; CHECK-NEXT: movt r1, #65535461; CHECK-NEXT: vmaxv.s16 r1, q0462; CHECK-NEXT: sxth r2, r1463; CHECK-NEXT: cmp r0, r2464; CHECK-NEXT: csel r0, r0, r1, gt465; CHECK-NEXT: sxth r0, r0466; CHECK-NEXT: bx lr467 %x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)468 %xs = sext i16 %x to i32469 %cmp = icmp sgt i32 %max, %xs470 %mt = trunc i32 %max to i16471 %1 = select i1 %cmp, i16 %mt, i16 %x472 ret i16 %1473}474 475define arm_aapcs_vfpcc signext i16 @trunc_and_zext(<8 x i16> %vec, i32 %max) #1 {476; CHECK-LABEL: trunc_and_zext:477; CHECK: @ %bb.0:478; CHECK-NEXT: movs r1, #0479; CHECK-NEXT: vmaxv.u16 r1, q0480; CHECK-NEXT: uxth r2, r1481; CHECK-NEXT: cmp r0, r2482; CHECK-NEXT: csel r0, r0, r1, gt483; CHECK-NEXT: sxth r0, r0484; CHECK-NEXT: bx lr485 %x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)486 %xs = zext i16 %x to i32487 %cmp = icmp sgt i32 %max, %xs488 %mt = trunc i32 %max to i16489 %1 = select i1 %cmp, i16 %mt, i16 %x490 ret i16 %1491}492 493define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) {494; CHECK-LABEL: uminv2i64:495; CHECK: @ %bb.0:496; CHECK-NEXT: .save {r4, lr}497; CHECK-NEXT: push {r4, lr}498; CHECK-NEXT: vmov r12, lr, d1499; CHECK-NEXT: vmov r2, r3, d0500; CHECK-NEXT: subs.w r4, r2, r12501; CHECK-NEXT: sbcs.w r4, r3, lr502; CHECK-NEXT: csel r2, r2, r12, lo503; CHECK-NEXT: csel r3, r3, lr, lo504; CHECK-NEXT: subs r4, r2, r0505; CHECK-NEXT: sbcs.w r4, r3, r1506; CHECK-NEXT: csel r0, r2, r0, lo507; CHECK-NEXT: csel r1, r3, r1, lo508; CHECK-NEXT: pop {r4, pc}509 %x = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)510 %cmp = icmp ult i64 %x, %min511 %1 = select i1 %cmp, i64 %x, i64 %min512 ret i64 %1513}514 515define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) {516; CHECK-LABEL: sminv2i64:517; CHECK: @ %bb.0:518; CHECK-NEXT: .save {r4, lr}519; CHECK-NEXT: push {r4, lr}520; CHECK-NEXT: vmov r12, lr, d1521; CHECK-NEXT: vmov r2, r3, d0522; CHECK-NEXT: subs.w r4, r2, r12523; CHECK-NEXT: sbcs.w r4, r3, lr524; CHECK-NEXT: csel r2, r2, r12, lt525; CHECK-NEXT: csel r3, r3, lr, lt526; CHECK-NEXT: subs r4, r2, r0527; CHECK-NEXT: sbcs.w r4, r3, r1528; CHECK-NEXT: csel r0, r2, r0, lt529; CHECK-NEXT: csel r1, r3, r1, lt530; CHECK-NEXT: pop {r4, pc}531 %x = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)532 %cmp = icmp slt i64 %x, %min533 %1 = select i1 %cmp, i64 %x, i64 %min534 ret i64 %1535}536 537define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) {538; CHECK-LABEL: umaxv2i64:539; CHECK: @ %bb.0:540; CHECK-NEXT: .save {r4, lr}541; CHECK-NEXT: push {r4, lr}542; CHECK-NEXT: vmov r12, lr, d0543; CHECK-NEXT: vmov r2, r3, d1544; CHECK-NEXT: subs.w r4, r2, r12545; CHECK-NEXT: sbcs.w r4, r3, lr546; CHECK-NEXT: csel r2, r12, r2, lo547; CHECK-NEXT: csel r3, lr, r3, lo548; CHECK-NEXT: subs r4, r0, r2549; CHECK-NEXT: sbcs.w r4, r1, r3550; CHECK-NEXT: csel r0, r2, r0, lo551; CHECK-NEXT: csel r1, r3, r1, lo552; CHECK-NEXT: pop {r4, pc}553 %x = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)554 %cmp = icmp ugt i64 %x, %max555 %1 = select i1 %cmp, i64 %x, i64 %max556 ret i64 %1557}558 559define arm_aapcs_vfpcc i64 @smaxv2i64(<2 x i64> %vec, i64 %max) {560; CHECK-LABEL: smaxv2i64:561; CHECK: @ %bb.0:562; CHECK-NEXT: .save {r4, lr}563; CHECK-NEXT: push {r4, lr}564; CHECK-NEXT: vmov r12, lr, d0565; CHECK-NEXT: vmov r2, r3, d1566; CHECK-NEXT: subs.w r4, r2, r12567; CHECK-NEXT: sbcs.w r4, r3, lr568; CHECK-NEXT: csel r2, r12, r2, lt569; CHECK-NEXT: csel r3, lr, r3, lt570; CHECK-NEXT: subs r4, r0, r2571; CHECK-NEXT: sbcs.w r4, r1, r3572; CHECK-NEXT: csel r0, r2, r0, lt573; CHECK-NEXT: csel r1, r3, r1, lt574; CHECK-NEXT: pop {r4, pc}575 %x = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)576 %cmp = icmp sgt i64 %x, %max577 %1 = select i1 %cmp, i64 %x, i64 %max578 ret i64 %1579}580 581declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)582 583declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)584 585declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)586 587declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)588 589declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)590 591declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)592 593declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)594 595declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)596 597declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)598 599declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)600 601declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)602 603declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)604 605declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)606 607declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)608 609declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)610 611declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)612