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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s3 4declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)5declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)6declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)7declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)8declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)9declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)10declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)11declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)12declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)13declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)14declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)15declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)16 17define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8(<16 x i8> %s1) {18; CHECK-LABEL: vmaxv_s_v16i8:19; CHECK: @ %bb.0:20; CHECK-NEXT: mvn r0, #12721; CHECK-NEXT: vmaxv.s8 r0, q022; CHECK-NEXT: bx lr23 %r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %s1)24 ret i8 %r25}26 27define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16(<8 x i16> %s1) {28; CHECK-LABEL: vmaxv_s_v8i16:29; CHECK: @ %bb.0:30; CHECK-NEXT: movw r0, #3276831; CHECK-NEXT: movt r0, #6553532; CHECK-NEXT: vmaxv.s16 r0, q033; CHECK-NEXT: bx lr34 %r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %s1)35 ret i16 %r36}37 38define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32(<4 x i32> %s1) {39; CHECK-LABEL: vmaxv_s_v4i32:40; CHECK: @ %bb.0:41; CHECK-NEXT: mov.w r0, #-214748364842; CHECK-NEXT: vmaxv.s32 r0, q043; CHECK-NEXT: bx lr44 %r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %s1)45 ret i32 %r46}47 48define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8(<16 x i8> %s1) {49; CHECK-LABEL: vmaxv_u_v16i8:50; CHECK: @ %bb.0:51; CHECK-NEXT: movs r0, #052; CHECK-NEXT: vmaxv.u8 r0, q053; CHECK-NEXT: bx lr54 %r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %s1)55 ret i8 %r56}57 58define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16(<8 x i16> %s1) {59; CHECK-LABEL: vmaxv_u_v8i16:60; CHECK: @ %bb.0:61; CHECK-NEXT: movs r0, #062; CHECK-NEXT: vmaxv.u16 r0, q063; CHECK-NEXT: bx lr64 %r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %s1)65 ret i16 %r66}67 68define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32(<4 x i32> %s1) {69; CHECK-LABEL: vmaxv_u_v4i32:70; CHECK: @ %bb.0:71; CHECK-NEXT: movs r0, #072; CHECK-NEXT: vmaxv.u32 r0, q073; CHECK-NEXT: bx lr74 %r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %s1)75 ret i32 %r76}77 78define arm_aapcs_vfpcc i8 @vminv_s_v16i8(<16 x i8> %s1) {79; CHECK-LABEL: vminv_s_v16i8:80; CHECK: @ %bb.0:81; CHECK-NEXT: movs r0, #12782; CHECK-NEXT: vminv.s8 r0, q083; CHECK-NEXT: bx lr84 %r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %s1)85 ret i8 %r86}87 88define arm_aapcs_vfpcc i16 @vminv_s_v8i16(<8 x i16> %s1) {89; CHECK-LABEL: vminv_s_v8i16:90; CHECK: @ %bb.0:91; CHECK-NEXT: movw r0, #3276792; CHECK-NEXT: vminv.s16 r0, q093; CHECK-NEXT: bx lr94 %r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %s1)95 ret i16 %r96}97 98define arm_aapcs_vfpcc i32 @vminv_s_v4i32(<4 x i32> %s1) {99; CHECK-LABEL: vminv_s_v4i32:100; CHECK: @ %bb.0:101; CHECK-NEXT: mvn r0, #-2147483648102; CHECK-NEXT: vminv.s32 r0, q0103; CHECK-NEXT: bx lr104 %r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %s1)105 ret i32 %r106}107 108define arm_aapcs_vfpcc i8 @vminv_u_v16i8(<16 x i8> %s1) {109; CHECK-LABEL: vminv_u_v16i8:110; CHECK: @ %bb.0:111; CHECK-NEXT: movs r0, #255112; CHECK-NEXT: vminv.u8 r0, q0113; CHECK-NEXT: bx lr114 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %s1)115 ret i8 %r116}117 118define arm_aapcs_vfpcc i16 @vminv_u_v8i16(<8 x i16> %s1) {119; CHECK-LABEL: vminv_u_v8i16:120; CHECK: @ %bb.0:121; CHECK-NEXT: movw r0, #65535122; CHECK-NEXT: vminv.u16 r0, q0123; CHECK-NEXT: bx lr124 %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %s1)125 ret i16 %r126}127 128define arm_aapcs_vfpcc i32 @vminv_u_v4i32(<4 x i32> %s1) {129; CHECK-LABEL: vminv_u_v4i32:130; CHECK: @ %bb.0:131; CHECK-NEXT: mov.w r0, #-1132; CHECK-NEXT: vminv.u32 r0, q0133; CHECK-NEXT: bx lr134 %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %s1)135 ret i32 %r136}137 138 139 140define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i8(<16 x i8> %s1, i8 %s2) {141; CHECK-LABEL: vmaxv_s_v16i8_i8:142; CHECK: @ %bb.0:143; CHECK-NEXT: vmaxv.s8 r0, q0144; CHECK-NEXT: bx lr145 %r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %s1)146 %c = icmp sgt i8 %r, %s2147 %s = select i1 %c, i8 %r, i8 %s2148 ret i8 %s149}150 151define arm_aapcs_vfpcc i32 @vmaxv_s_v16i8_i32(<16 x i8> %s1, i32 %s2) {152; CHECK-LABEL: vmaxv_s_v16i8_i32:153; CHECK: @ %bb.0:154; CHECK-NEXT: mvn r1, #127155; CHECK-NEXT: vmaxv.s8 r1, q0156; CHECK-NEXT: sxtb r1, r1157; CHECK-NEXT: cmp r1, r0158; CHECK-NEXT: csel r0, r1, r0, gt159; CHECK-NEXT: bx lr160 %r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %s1)161 %rs = sext i8 %r to i32162 %c = icmp sgt i32 %rs, %s2163 %s = select i1 %c, i32 %rs, i32 %s2164 ret i32 %s165}166 167define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i16(<8 x i16> %s1, i16 %s2) {168; CHECK-LABEL: vmaxv_s_v8i16_i16:169; CHECK: @ %bb.0:170; CHECK-NEXT: vmaxv.s16 r0, q0171; CHECK-NEXT: bx lr172 %r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %s1)173 %c = icmp sgt i16 %r, %s2174 %s = select i1 %c, i16 %r, i16 %s2175 ret i16 %s176}177 178define arm_aapcs_vfpcc i32 @vmaxv_s_v8i16_i32(<8 x i16> %s1, i32 %s2) {179; CHECK-LABEL: vmaxv_s_v8i16_i32:180; CHECK: @ %bb.0:181; CHECK-NEXT: movw r1, #32768182; CHECK-NEXT: movt r1, #65535183; CHECK-NEXT: vmaxv.s16 r1, q0184; CHECK-NEXT: sxth r1, r1185; CHECK-NEXT: cmp r1, r0186; CHECK-NEXT: csel r0, r1, r0, gt187; CHECK-NEXT: bx lr188 %r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %s1)189 %rs = sext i16 %r to i32190 %c = icmp sgt i32 %rs, %s2191 %s = select i1 %c, i32 %rs, i32 %s2192 ret i32 %s193}194 195define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {196; CHECK-LABEL: vmaxv_s_v4i32_i32:197; CHECK: @ %bb.0:198; CHECK-NEXT: vmaxv.s32 r0, q0199; CHECK-NEXT: bx lr200 %r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %s1)201 %c = icmp sgt i32 %r, %s2202 %s = select i1 %c, i32 %r, i32 %s2203 ret i32 %s204}205 206define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i8(<16 x i8> %s1, i8 %s2) {207; CHECK-LABEL: vmaxv_u_v16i8_i8:208; CHECK: @ %bb.0:209; CHECK-NEXT: vmaxv.u8 r0, q0210; CHECK-NEXT: bx lr211 %r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %s1)212 %c = icmp ugt i8 %r, %s2213 %s = select i1 %c, i8 %r, i8 %s2214 ret i8 %s215}216 217define arm_aapcs_vfpcc i32 @vmaxv_u_v16i8_i32(<16 x i8> %s1, i32 %s2) {218; CHECK-LABEL: vmaxv_u_v16i8_i32:219; CHECK: @ %bb.0:220; CHECK-NEXT: movs r1, #0221; CHECK-NEXT: vmaxv.u8 r1, q0222; CHECK-NEXT: uxtb r1, r1223; CHECK-NEXT: cmp r1, r0224; CHECK-NEXT: csel r0, r1, r0, hi225; CHECK-NEXT: bx lr226 %r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %s1)227 %rs = zext i8 %r to i32228 %c = icmp ugt i32 %rs, %s2229 %s = select i1 %c, i32 %rs, i32 %s2230 ret i32 %s231}232 233define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i16(<8 x i16> %s1, i16 %s2) {234; CHECK-LABEL: vmaxv_u_v8i16_i16:235; CHECK: @ %bb.0:236; CHECK-NEXT: vmaxv.u16 r0, q0237; CHECK-NEXT: bx lr238 %r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %s1)239 %c = icmp ugt i16 %r, %s2240 %s = select i1 %c, i16 %r, i16 %s2241 ret i16 %s242}243 244define arm_aapcs_vfpcc i32 @vmaxv_u_v8i16_i32(<8 x i16> %s1, i32 %s2) {245; CHECK-LABEL: vmaxv_u_v8i16_i32:246; CHECK: @ %bb.0:247; CHECK-NEXT: movs r1, #0248; CHECK-NEXT: vmaxv.u16 r1, q0249; CHECK-NEXT: uxth r1, r1250; CHECK-NEXT: cmp r1, r0251; CHECK-NEXT: csel r0, r1, r0, hi252; CHECK-NEXT: bx lr253 %r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %s1)254 %rs = zext i16 %r to i32255 %c = icmp ugt i32 %rs, %s2256 %s = select i1 %c, i32 %rs, i32 %s2257 ret i32 %s258}259 260define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1, i32 %s2) {261; CHECK-LABEL: vmaxv_u_v4i32_i32:262; CHECK: @ %bb.0:263; CHECK-NEXT: vmaxv.u32 r0, q0264; CHECK-NEXT: bx lr265 %r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %s1)266 %c = icmp ugt i32 %r, %s2267 %s = select i1 %c, i32 %r, i32 %s2268 ret i32 %s269}270 271define arm_aapcs_vfpcc i8 @vminv_s_v16i8_i8(<16 x i8> %s1, i8 %s2) {272; CHECK-LABEL: vminv_s_v16i8_i8:273; CHECK: @ %bb.0:274; CHECK-NEXT: vminv.s8 r0, q0275; CHECK-NEXT: bx lr276 %r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %s1)277 %c = icmp slt i8 %r, %s2278 %s = select i1 %c, i8 %r, i8 %s2279 ret i8 %s280}281 282define arm_aapcs_vfpcc i32 @vminv_s_v16i8_i32(<16 x i8> %s1, i32 %s2) {283; CHECK-LABEL: vminv_s_v16i8_i32:284; CHECK: @ %bb.0:285; CHECK-NEXT: movs r1, #127286; CHECK-NEXT: vminv.s8 r1, q0287; CHECK-NEXT: sxtb r1, r1288; CHECK-NEXT: cmp r1, r0289; CHECK-NEXT: csel r0, r1, r0, lt290; CHECK-NEXT: bx lr291 %r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %s1)292 %rs = sext i8 %r to i32293 %c = icmp slt i32 %rs, %s2294 %s = select i1 %c, i32 %rs, i32 %s2295 ret i32 %s296}297 298define arm_aapcs_vfpcc i16 @vminv_s_v8i16_i16(<8 x i16> %s1, i16 %s2) {299; CHECK-LABEL: vminv_s_v8i16_i16:300; CHECK: @ %bb.0:301; CHECK-NEXT: vminv.s16 r0, q0302; CHECK-NEXT: bx lr303 %r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %s1)304 %c = icmp slt i16 %r, %s2305 %s = select i1 %c, i16 %r, i16 %s2306 ret i16 %s307}308 309define arm_aapcs_vfpcc i32 @vminv_s_v8i16_i32(<8 x i16> %s1, i32 %s2) {310; CHECK-LABEL: vminv_s_v8i16_i32:311; CHECK: @ %bb.0:312; CHECK-NEXT: movw r1, #32767313; CHECK-NEXT: vminv.s16 r1, q0314; CHECK-NEXT: sxth r1, r1315; CHECK-NEXT: cmp r1, r0316; CHECK-NEXT: csel r0, r1, r0, lt317; CHECK-NEXT: bx lr318 %r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %s1)319 %rs = sext i16 %r to i32320 %c = icmp slt i32 %rs, %s2321 %s = select i1 %c, i32 %rs, i32 %s2322 ret i32 %s323}324 325define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {326; CHECK-LABEL: vminv_s_v4i32_i32:327; CHECK: @ %bb.0:328; CHECK-NEXT: vminv.s32 r0, q0329; CHECK-NEXT: bx lr330 %r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %s1)331 %c = icmp slt i32 %r, %s2332 %s = select i1 %c, i32 %r, i32 %s2333 ret i32 %s334}335 336define arm_aapcs_vfpcc i8 @vminv_u_v16i8_i8(<16 x i8> %s1, i8 %s2) {337; CHECK-LABEL: vminv_u_v16i8_i8:338; CHECK: @ %bb.0:339; CHECK-NEXT: vminv.u8 r0, q0340; CHECK-NEXT: bx lr341 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %s1)342 %c = icmp ult i8 %r, %s2343 %s = select i1 %c, i8 %r, i8 %s2344 ret i8 %s345}346 347define arm_aapcs_vfpcc i32 @vminv_u_v16i8_i32(<16 x i8> %s1, i32 %s2) {348; CHECK-LABEL: vminv_u_v16i8_i32:349; CHECK: @ %bb.0:350; CHECK-NEXT: movs r1, #255351; CHECK-NEXT: vminv.u8 r1, q0352; CHECK-NEXT: uxtb r1, r1353; CHECK-NEXT: cmp r1, r0354; CHECK-NEXT: csel r0, r1, r0, lo355; CHECK-NEXT: bx lr356 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %s1)357 %rs = zext i8 %r to i32358 %c = icmp ult i32 %rs, %s2359 %s = select i1 %c, i32 %rs, i32 %s2360 ret i32 %s361}362 363define arm_aapcs_vfpcc i16 @vminv_u_v8i16_i16(<8 x i16> %s1, i16 %s2) {364; CHECK-LABEL: vminv_u_v8i16_i16:365; CHECK: @ %bb.0:366; CHECK-NEXT: vminv.u16 r0, q0367; CHECK-NEXT: bx lr368 %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %s1)369 %c = icmp ult i16 %r, %s2370 %s = select i1 %c, i16 %r, i16 %s2371 ret i16 %s372}373 374define arm_aapcs_vfpcc i32 @vminv_u_v8i16_i32(<8 x i16> %s1, i32 %s2) {375; CHECK-LABEL: vminv_u_v8i16_i32:376; CHECK: @ %bb.0:377; CHECK-NEXT: movw r1, #65535378; CHECK-NEXT: vminv.u16 r1, q0379; CHECK-NEXT: uxth r1, r1380; CHECK-NEXT: cmp r1, r0381; CHECK-NEXT: csel r0, r1, r0, lo382; CHECK-NEXT: bx lr383 %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %s1)384 %rs = zext i16 %r to i32385 %c = icmp ult i32 %rs, %s2386 %s = select i1 %c, i32 %rs, i32 %s2387 ret i32 %s388}389 390define arm_aapcs_vfpcc i32 @vminv_u_v4i32_i32(<4 x i32> %s1, i32 %s2) {391; CHECK-LABEL: vminv_u_v4i32_i32:392; CHECK: @ %bb.0:393; CHECK-NEXT: vminv.u32 r0, q0394; CHECK-NEXT: bx lr395 %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %s1)396 %c = icmp ult i32 %r, %s2397 %s = select i1 %c, i32 %r, i32 %s2398 ret i32 %s399}400