1365 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE4; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE5 6define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() {7; CHECK-LABEL: mov_int8_1:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: vmov.i8 q0, #0x110; CHECK-NEXT: bx lr11entry:12 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>13}14 15define arm_aapcs_vfpcc <16 x i8> @xor_int8_1(<16 x i8> %a) {16; CHECKLE-LABEL: xor_int8_1:17; CHECKLE: @ %bb.0: @ %entry18; CHECKLE-NEXT: vmov.i8 q1, #0x119; CHECKLE-NEXT: veor q0, q0, q120; CHECKLE-NEXT: bx lr21;22; CHECKBE-LABEL: xor_int8_1:23; CHECKBE: @ %bb.0: @ %entry24; CHECKBE-NEXT: vmov.i8 q1, #0x125; CHECKBE-NEXT: vrev64.8 q2, q026; CHECKBE-NEXT: veor q1, q2, q127; CHECKBE-NEXT: vrev64.8 q0, q128; CHECKBE-NEXT: bx lr29entry:30 %b = xor <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>31 ret <16 x i8> %b32}33 34define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() {35; CHECK-LABEL: mov_int8_m1:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vmov.i8 q0, #0xff38; CHECK-NEXT: bx lr39entry:40 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>41}42 43define arm_aapcs_vfpcc <16 x i8> @xor_int8_m1(<16 x i8> %a) {44; CHECKLE-LABEL: xor_int8_m1:45; CHECKLE: @ %bb.0: @ %entry46; CHECKLE-NEXT: vmvn q0, q047; CHECKLE-NEXT: bx lr48;49; CHECKBE-LABEL: xor_int8_m1:50; CHECKBE: @ %bb.0: @ %entry51; CHECKBE-NEXT: vrev64.8 q1, q052; CHECKBE-NEXT: vmvn q1, q153; CHECKBE-NEXT: vrev64.8 q0, q154; CHECKBE-NEXT: bx lr55entry:56 %b = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>57 ret <16 x i8> %b58}59 60; This has 0x01020304 or 0x04030201 vdup.32'd to q reg depending on endianness.61; The big endian is different as there is an implicit vrev64.8 out of the62; function, which gets constant folded away.63define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() {64; CHECKLE-LABEL: mov_int8_1234:65; CHECKLE: @ %bb.0: @ %entry66; CHECKLE-NEXT: movw r0, #51367; CHECKLE-NEXT: movt r0, #102768; CHECKLE-NEXT: vdup.32 q0, r069; CHECKLE-NEXT: bx lr70;71; CHECKBE-LABEL: mov_int8_1234:72; CHECKBE: @ %bb.0: @ %entry73; CHECKBE-NEXT: movw r0, #77274; CHECKBE-NEXT: movt r0, #25875; CHECKBE-NEXT: vdup.32 q0, r076; CHECKBE-NEXT: bx lr77entry:78 ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>79}80 81define arm_aapcs_vfpcc <16 x i8> @xor_int8_1234(<16 x i8> %a) {82; CHECKLE-LABEL: xor_int8_1234:83; CHECKLE: @ %bb.0: @ %entry84; CHECKLE-NEXT: movw r0, #51385; CHECKLE-NEXT: movt r0, #102786; CHECKLE-NEXT: vdup.32 q1, r087; CHECKLE-NEXT: veor q0, q0, q188; CHECKLE-NEXT: bx lr89;90; CHECKBE-LABEL: xor_int8_1234:91; CHECKBE: @ %bb.0: @ %entry92; CHECKBE-NEXT: movw r0, #51393; CHECKBE-NEXT: vrev64.8 q1, q094; CHECKBE-NEXT: movt r0, #102795; CHECKBE-NEXT: vdup.32 q0, r096; CHECKBE-NEXT: veor q1, q1, q097; CHECKBE-NEXT: vrev64.8 q0, q198; CHECKBE-NEXT: bx lr99entry:100 %b = xor <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>101 ret <16 x i8> %b102}103 104define arm_aapcs_vfpcc <16 x i8> @mov_int8_32() {105; CHECKLE-LABEL: mov_int8_32:106; CHECKLE: @ %bb.0: @ %entry107; CHECKLE-NEXT: vmov.i32 q0, #0x1108; CHECKLE-NEXT: bx lr109;110; CHECKBE-LABEL: mov_int8_32:111; CHECKBE: @ %bb.0: @ %entry112; CHECKBE-NEXT: vmov.i32 q0, #0x1000000113; CHECKBE-NEXT: bx lr114entry:115 ret <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>116}117 118define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {119; CHECKLE-LABEL: xor_int8_32:120; CHECKLE: @ %bb.0: @ %entry121; CHECKLE-NEXT: vmov.i32 q1, #0x1122; CHECKLE-NEXT: veor q0, q0, q1123; CHECKLE-NEXT: bx lr124;125; CHECKBE-LABEL: xor_int8_32:126; CHECKBE: @ %bb.0: @ %entry127; CHECKBE-NEXT: vmov.i32 q1, #0x1128; CHECKBE-NEXT: vrev64.8 q2, q0129; CHECKBE-NEXT: veor q1, q2, q1130; CHECKBE-NEXT: vrev64.8 q0, q1131; CHECKBE-NEXT: bx lr132entry:133 %b = xor <16 x i8> %a, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>134 ret <16 x i8> %b135}136 137define arm_aapcs_vfpcc <16 x i8> @mov_int8_64() {138; CHECKLE-LABEL: mov_int8_64:139; CHECKLE: @ %bb.0: @ %entry140; CHECKLE-NEXT: vmov.i64 q0, #0xffff00ffff0000ff141; CHECKLE-NEXT: bx lr142;143; CHECKBE-LABEL: mov_int8_64:144; CHECKBE: @ %bb.0: @ %entry145; CHECKBE-NEXT: vmov.i64 q0, #0xff0000ffff00ffff146; CHECKBE-NEXT: bx lr147entry:148 ret <16 x i8> <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>149}150 151define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {152; CHECKLE-LABEL: xor_int8_64:153; CHECKLE: @ %bb.0: @ %entry154; CHECKLE-NEXT: vmov.i64 q1, #0xffff00ffff0000ff155; CHECKLE-NEXT: veor q0, q0, q1156; CHECKLE-NEXT: bx lr157;158; CHECKBE-LABEL: xor_int8_64:159; CHECKBE: @ %bb.0: @ %entry160; CHECKBE-NEXT: vmov.i64 q1, #0xffff00ffff0000ff161; CHECKBE-NEXT: vrev64.8 q2, q0162; CHECKBE-NEXT: veor q1, q2, q1163; CHECKBE-NEXT: vrev64.8 q0, q1164; CHECKBE-NEXT: bx lr165entry:166 %b = xor <16 x i8> %a, <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>167 ret <16 x i8> %b168}169 170define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {171; CHECK-LABEL: mov_int16_1:172; CHECK: @ %bb.0: @ %entry173; CHECK-NEXT: vmov.i16 q0, #0x1174; CHECK-NEXT: bx lr175entry:176 ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>177}178 179define arm_aapcs_vfpcc <8 x i16> @xor_int16_1(<8 x i16> %a) {180; CHECKLE-LABEL: xor_int16_1:181; CHECKLE: @ %bb.0: @ %entry182; CHECKLE-NEXT: vmov.i16 q1, #0x1183; CHECKLE-NEXT: veor q0, q0, q1184; CHECKLE-NEXT: bx lr185;186; CHECKBE-LABEL: xor_int16_1:187; CHECKBE: @ %bb.0: @ %entry188; CHECKBE-NEXT: vmov.i16 q1, #0x1189; CHECKBE-NEXT: vrev64.16 q2, q0190; CHECKBE-NEXT: veor q1, q2, q1191; CHECKBE-NEXT: vrev64.16 q0, q1192; CHECKBE-NEXT: bx lr193entry:194 %b = xor <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>195 ret <8 x i16> %b196}197 198define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() {199; CHECK-LABEL: mov_int16_m1:200; CHECK: @ %bb.0: @ %entry201; CHECK-NEXT: vmov.i8 q0, #0xff202; CHECK-NEXT: bx lr203entry:204 ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>205}206 207define arm_aapcs_vfpcc <8 x i16> @xor_int16_m1(<8 x i16> %a) {208; CHECKLE-LABEL: xor_int16_m1:209; CHECKLE: @ %bb.0: @ %entry210; CHECKLE-NEXT: vmvn q0, q0211; CHECKLE-NEXT: bx lr212;213; CHECKBE-LABEL: xor_int16_m1:214; CHECKBE: @ %bb.0: @ %entry215; CHECKBE-NEXT: vmov.i8 q1, #0xff216; CHECKBE-NEXT: vrev64.16 q2, q0217; CHECKBE-NEXT: veor q1, q2, q1218; CHECKBE-NEXT: vrev64.16 q0, q1219; CHECKBE-NEXT: bx lr220entry:221 %b = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>222 ret <8 x i16> %b223}224 225define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() {226; CHECK-LABEL: mov_int16_256:227; CHECK: @ %bb.0: @ %entry228; CHECK-NEXT: vmov.i16 q0, #0x100229; CHECK-NEXT: bx lr230entry:231 ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>232}233 234define arm_aapcs_vfpcc <8 x i16> @xor_int16_256(<8 x i16> %a) {235; CHECKLE-LABEL: xor_int16_256:236; CHECKLE: @ %bb.0: @ %entry237; CHECKLE-NEXT: vmov.i16 q1, #0x100238; CHECKLE-NEXT: veor q0, q0, q1239; CHECKLE-NEXT: bx lr240;241; CHECKBE-LABEL: xor_int16_256:242; CHECKBE: @ %bb.0: @ %entry243; CHECKBE-NEXT: vmov.i16 q1, #0x100244; CHECKBE-NEXT: vrev64.16 q2, q0245; CHECKBE-NEXT: veor q1, q2, q1246; CHECKBE-NEXT: vrev64.16 q0, q1247; CHECKBE-NEXT: bx lr248entry:249 %b = xor <8 x i16> %a, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>250 ret <8 x i16> %b251}252 253define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() {254; CHECK-LABEL: mov_int16_257:255; CHECK: @ %bb.0: @ %entry256; CHECK-NEXT: vmov.i8 q0, #0x1257; CHECK-NEXT: bx lr258entry:259 ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>260}261 262define arm_aapcs_vfpcc <8 x i16> @xor_int16_257(<8 x i16> %a) {263; CHECKLE-LABEL: xor_int16_257:264; CHECKLE: @ %bb.0: @ %entry265; CHECKLE-NEXT: vmov.i8 q1, #0x1266; CHECKLE-NEXT: veor q0, q0, q1267; CHECKLE-NEXT: bx lr268;269; CHECKBE-LABEL: xor_int16_257:270; CHECKBE: @ %bb.0: @ %entry271; CHECKBE-NEXT: vmov.i8 q1, #0x1272; CHECKBE-NEXT: vrev64.16 q2, q0273; CHECKBE-NEXT: veor q1, q2, q1274; CHECKBE-NEXT: vrev64.16 q0, q1275; CHECKBE-NEXT: bx lr276entry:277 %b = xor <8 x i16> %a, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>278 ret <8 x i16> %b279}280 281define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {282; CHECK-LABEL: mov_int16_258:283; CHECK: @ %bb.0: @ %entry284; CHECK-NEXT: mov.w r0, #258285; CHECK-NEXT: vdup.16 q0, r0286; CHECK-NEXT: bx lr287entry:288 ret <8 x i16> <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>289}290 291define arm_aapcs_vfpcc <8 x i16> @xor_int16_258(<8 x i16> %a) {292; CHECKLE-LABEL: xor_int16_258:293; CHECKLE: @ %bb.0: @ %entry294; CHECKLE-NEXT: mov.w r0, #258295; CHECKLE-NEXT: vdup.16 q1, r0296; CHECKLE-NEXT: veor q0, q0, q1297; CHECKLE-NEXT: bx lr298;299; CHECKBE-LABEL: xor_int16_258:300; CHECKBE: @ %bb.0: @ %entry301; CHECKBE-NEXT: mov.w r0, #258302; CHECKBE-NEXT: vrev64.16 q2, q0303; CHECKBE-NEXT: vdup.16 q1, r0304; CHECKBE-NEXT: veor q1, q2, q1305; CHECKBE-NEXT: vrev64.16 q0, q1306; CHECKBE-NEXT: bx lr307entry:308 %b = xor <8 x i16> %a, <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>309 ret <8 x i16> %b310}311 312define arm_aapcs_vfpcc <8 x i16> @mov_int16_32() {313; CHECKLE-LABEL: mov_int16_32:314; CHECKLE: @ %bb.0: @ %entry315; CHECKLE-NEXT: movw r0, #257316; CHECKLE-NEXT: movt r0, #256317; CHECKLE-NEXT: vdup.32 q0, r0318; CHECKLE-NEXT: bx lr319;320; CHECKBE-LABEL: mov_int16_32:321; CHECKBE: @ %bb.0: @ %entry322; CHECKBE-NEXT: movw r0, #256323; CHECKBE-NEXT: movt r0, #257324; CHECKBE-NEXT: vdup.32 q0, r0325; CHECKBE-NEXT: bx lr326entry:327 ret <8 x i16> <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>328}329 330define arm_aapcs_vfpcc <8 x i16> @xor_int16_32(<8 x i16> %a) {331; CHECKLE-LABEL: xor_int16_32:332; CHECKLE: @ %bb.0: @ %entry333; CHECKLE-NEXT: movw r0, #257334; CHECKLE-NEXT: movt r0, #256335; CHECKLE-NEXT: vdup.32 q1, r0336; CHECKLE-NEXT: veor q0, q0, q1337; CHECKLE-NEXT: bx lr338;339; CHECKBE-LABEL: xor_int16_32:340; CHECKBE: @ %bb.0: @ %entry341; CHECKBE-NEXT: movw r0, #257342; CHECKBE-NEXT: vrev64.16 q1, q0343; CHECKBE-NEXT: movt r0, #256344; CHECKBE-NEXT: vdup.32 q0, r0345; CHECKBE-NEXT: veor q1, q1, q0346; CHECKBE-NEXT: vrev64.16 q0, q1347; CHECKBE-NEXT: bx lr348entry:349 %b = xor <8 x i16> %a, <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>350 ret <8 x i16> %b351}352 353define arm_aapcs_vfpcc <8 x i16> @mov_int16_64() {354; CHECK-LABEL: mov_int16_64:355; CHECK: @ %bb.0: @ %entry356; CHECK-NEXT: vmov.i64 q0, #0xff0000000000ff357; CHECK-NEXT: bx lr358entry:359 ret <8 x i16> <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>360}361 362define arm_aapcs_vfpcc <8 x i16> @xor_int16_64(<8 x i16> %a) {363; CHECKLE-LABEL: xor_int16_64:364; CHECKLE: @ %bb.0: @ %entry365; CHECKLE-NEXT: vmov.i64 q1, #0xff0000000000ff366; CHECKLE-NEXT: veor q0, q0, q1367; CHECKLE-NEXT: bx lr368;369; CHECKBE-LABEL: xor_int16_64:370; CHECKBE: @ %bb.0: @ %entry371; CHECKBE-NEXT: vmov.i64 q1, #0xff0000000000ff372; CHECKBE-NEXT: vrev64.16 q2, q0373; CHECKBE-NEXT: veor q1, q2, q1374; CHECKBE-NEXT: vrev64.16 q0, q1375; CHECKBE-NEXT: bx lr376entry:377 %b = xor <8 x i16> %a, <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>378 ret <8 x i16> %b379}380 381define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() {382; CHECK-LABEL: mov_int32_1:383; CHECK: @ %bb.0: @ %entry384; CHECK-NEXT: vmov.i32 q0, #0x1385; CHECK-NEXT: bx lr386entry:387 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>388}389 390define arm_aapcs_vfpcc <4 x i32> @xor_int32_1(<4 x i32> %a) {391; CHECKLE-LABEL: xor_int32_1:392; CHECKLE: @ %bb.0: @ %entry393; CHECKLE-NEXT: vmov.i32 q1, #0x1394; CHECKLE-NEXT: veor q0, q0, q1395; CHECKLE-NEXT: bx lr396;397; CHECKBE-LABEL: xor_int32_1:398; CHECKBE: @ %bb.0: @ %entry399; CHECKBE-NEXT: vmov.i32 q1, #0x1400; CHECKBE-NEXT: vrev64.32 q2, q0401; CHECKBE-NEXT: veor q1, q2, q1402; CHECKBE-NEXT: vrev64.32 q0, q1403; CHECKBE-NEXT: bx lr404entry:405 %b = xor <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>406 ret <4 x i32> %b407}408 409define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() {410; CHECK-LABEL: mov_int32_256:411; CHECK: @ %bb.0: @ %entry412; CHECK-NEXT: vmov.i32 q0, #0x100413; CHECK-NEXT: bx lr414entry:415 ret <4 x i32> <i32 256, i32 256, i32 256, i32 256>416}417 418define arm_aapcs_vfpcc <4 x i32> @xor_int32_256(<4 x i32> %a) {419; CHECKLE-LABEL: xor_int32_256:420; CHECKLE: @ %bb.0: @ %entry421; CHECKLE-NEXT: vmov.i32 q1, #0x100422; CHECKLE-NEXT: veor q0, q0, q1423; CHECKLE-NEXT: bx lr424;425; CHECKBE-LABEL: xor_int32_256:426; CHECKBE: @ %bb.0: @ %entry427; CHECKBE-NEXT: vmov.i32 q1, #0x100428; CHECKBE-NEXT: vrev64.32 q2, q0429; CHECKBE-NEXT: veor q1, q2, q1430; CHECKBE-NEXT: vrev64.32 q0, q1431; CHECKBE-NEXT: bx lr432entry:433 %b = xor <4 x i32> %a, <i32 256, i32 256, i32 256, i32 256>434 ret <4 x i32> %b435}436 437define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() {438; CHECK-LABEL: mov_int32_65536:439; CHECK: @ %bb.0: @ %entry440; CHECK-NEXT: vmov.i32 q0, #0x10000441; CHECK-NEXT: bx lr442entry:443 ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>444}445 446define arm_aapcs_vfpcc <4 x i32> @xor_int32_65536(<4 x i32> %a) {447; CHECKLE-LABEL: xor_int32_65536:448; CHECKLE: @ %bb.0: @ %entry449; CHECKLE-NEXT: vmov.i32 q1, #0x10000450; CHECKLE-NEXT: veor q0, q0, q1451; CHECKLE-NEXT: bx lr452;453; CHECKBE-LABEL: xor_int32_65536:454; CHECKBE: @ %bb.0: @ %entry455; CHECKBE-NEXT: vmov.i32 q1, #0x10000456; CHECKBE-NEXT: vrev64.32 q2, q0457; CHECKBE-NEXT: veor q1, q2, q1458; CHECKBE-NEXT: vrev64.32 q0, q1459; CHECKBE-NEXT: bx lr460entry:461 %b = xor <4 x i32> %a, <i32 65536, i32 65536, i32 65536, i32 65536>462 ret <4 x i32> %b463}464 465define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() {466; CHECK-LABEL: mov_int32_16777216:467; CHECK: @ %bb.0: @ %entry468; CHECK-NEXT: vmov.i32 q0, #0x1000000469; CHECK-NEXT: bx lr470entry:471 ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>472}473 474define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777216(<4 x i32> %a) {475; CHECKLE-LABEL: xor_int32_16777216:476; CHECKLE: @ %bb.0: @ %entry477; CHECKLE-NEXT: vmov.i32 q1, #0x1000000478; CHECKLE-NEXT: veor q0, q0, q1479; CHECKLE-NEXT: bx lr480;481; CHECKBE-LABEL: xor_int32_16777216:482; CHECKBE: @ %bb.0: @ %entry483; CHECKBE-NEXT: vmov.i32 q1, #0x1000000484; CHECKBE-NEXT: vrev64.32 q2, q0485; CHECKBE-NEXT: veor q1, q2, q1486; CHECKBE-NEXT: vrev64.32 q0, q1487; CHECKBE-NEXT: bx lr488entry:489 %b = xor <4 x i32> %a, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>490 ret <4 x i32> %b491}492 493define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {494; CHECK-LABEL: mov_int32_16777217:495; CHECK: @ %bb.0: @ %entry496; CHECK-NEXT: movs r0, #1497; CHECK-NEXT: movt r0, #256498; CHECK-NEXT: vdup.32 q0, r0499; CHECK-NEXT: bx lr500entry:501 ret <4 x i32> <i32 16777217, i32 16777217, i32 16777217, i32 16777217>502}503 504define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777217(<4 x i32> %a) {505; CHECKLE-LABEL: xor_int32_16777217:506; CHECKLE: @ %bb.0: @ %entry507; CHECKLE-NEXT: movs r0, #1508; CHECKLE-NEXT: movt r0, #256509; CHECKLE-NEXT: vdup.32 q1, r0510; CHECKLE-NEXT: veor q0, q0, q1511; CHECKLE-NEXT: bx lr512;513; CHECKBE-LABEL: xor_int32_16777217:514; CHECKBE: @ %bb.0: @ %entry515; CHECKBE-NEXT: movs r0, #1516; CHECKBE-NEXT: vrev64.32 q1, q0517; CHECKBE-NEXT: movt r0, #256518; CHECKBE-NEXT: vdup.32 q0, r0519; CHECKBE-NEXT: veor q1, q1, q0520; CHECKBE-NEXT: vrev64.32 q0, q1521; CHECKBE-NEXT: bx lr522entry:523 %b = xor <4 x i32> %a, <i32 16777217, i32 16777217, i32 16777217, i32 16777217>524 ret <4 x i32> %b525}526 527define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() {528; CHECK-LABEL: mov_int32_17919:529; CHECK: @ %bb.0: @ %entry530; CHECK-NEXT: vmov.i32 q0, #0x45ff531; CHECK-NEXT: bx lr532entry:533 ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919>534}535 536define arm_aapcs_vfpcc <4 x i32> @xor_int32_17919(<4 x i32> %a) {537; CHECKLE-LABEL: xor_int32_17919:538; CHECKLE: @ %bb.0: @ %entry539; CHECKLE-NEXT: vmov.i32 q1, #0x45ff540; CHECKLE-NEXT: veor q0, q0, q1541; CHECKLE-NEXT: bx lr542;543; CHECKBE-LABEL: xor_int32_17919:544; CHECKBE: @ %bb.0: @ %entry545; CHECKBE-NEXT: vmov.i32 q1, #0x45ff546; CHECKBE-NEXT: vrev64.32 q2, q0547; CHECKBE-NEXT: veor q1, q2, q1548; CHECKBE-NEXT: vrev64.32 q0, q1549; CHECKBE-NEXT: bx lr550entry:551 %b = xor <4 x i32> %a, <i32 17919, i32 17919, i32 17919, i32 17919>552 ret <4 x i32> %b553}554 555define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() {556; CHECK-LABEL: mov_int32_4587519:557; CHECK: @ %bb.0: @ %entry558; CHECK-NEXT: vmov.i32 q0, #0x45ffff559; CHECK-NEXT: bx lr560entry:561 ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519>562}563 564define arm_aapcs_vfpcc <4 x i32> @xor_int32_4587519(<4 x i32> %a) {565; CHECKLE-LABEL: xor_int32_4587519:566; CHECKLE: @ %bb.0: @ %entry567; CHECKLE-NEXT: vmov.i32 q1, #0x45ffff568; CHECKLE-NEXT: veor q0, q0, q1569; CHECKLE-NEXT: bx lr570;571; CHECKBE-LABEL: xor_int32_4587519:572; CHECKBE: @ %bb.0: @ %entry573; CHECKBE-NEXT: vmov.i32 q1, #0x45ffff574; CHECKBE-NEXT: vrev64.32 q2, q0575; CHECKBE-NEXT: veor q1, q2, q1576; CHECKBE-NEXT: vrev64.32 q0, q1577; CHECKBE-NEXT: bx lr578entry:579 %b = xor <4 x i32> %a, <i32 4587519, i32 4587519, i32 4587519, i32 4587519>580 ret <4 x i32> %b581}582 583define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() {584; CHECK-LABEL: mov_int32_m1:585; CHECK: @ %bb.0: @ %entry586; CHECK-NEXT: vmov.i8 q0, #0xff587; CHECK-NEXT: bx lr588entry:589 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>590}591 592define arm_aapcs_vfpcc <4 x i32> @xor_int32_m1(<4 x i32> %a) {593; CHECKLE-LABEL: xor_int32_m1:594; CHECKLE: @ %bb.0: @ %entry595; CHECKLE-NEXT: vmvn q0, q0596; CHECKLE-NEXT: bx lr597;598; CHECKBE-LABEL: xor_int32_m1:599; CHECKBE: @ %bb.0: @ %entry600; CHECKBE-NEXT: vmov.i8 q1, #0xff601; CHECKBE-NEXT: vrev64.32 q2, q0602; CHECKBE-NEXT: veor q1, q2, q1603; CHECKBE-NEXT: vrev64.32 q0, q1604; CHECKBE-NEXT: bx lr605entry:606 %b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>607 ret <4 x i32> %b608}609 610define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() {611; CHECK-LABEL: mov_int32_4294901760:612; CHECK: @ %bb.0: @ %entry613; CHECK-NEXT: vmvn.i32 q0, #0xffff614; CHECK-NEXT: bx lr615entry:616 ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>617}618 619define arm_aapcs_vfpcc <4 x i32> @xor_int32_4294901760(<4 x i32> %a) {620; CHECKLE-LABEL: xor_int32_4294901760:621; CHECKLE: @ %bb.0: @ %entry622; CHECKLE-NEXT: vmvn.i32 q1, #0xffff623; CHECKLE-NEXT: veor q0, q0, q1624; CHECKLE-NEXT: bx lr625;626; CHECKBE-LABEL: xor_int32_4294901760:627; CHECKBE: @ %bb.0: @ %entry628; CHECKBE-NEXT: vmvn.i32 q1, #0xffff629; CHECKBE-NEXT: vrev64.32 q2, q0630; CHECKBE-NEXT: veor q1, q2, q1631; CHECKBE-NEXT: vrev64.32 q0, q1632; CHECKBE-NEXT: bx lr633entry:634 %b = xor <4 x i32> %a, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>635 ret <4 x i32> %b636}637 638define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {639; CHECK-LABEL: mov_int32_4278190335:640; CHECK: @ %bb.0: @ %entry641; CHECK-NEXT: movs r0, #255642; CHECK-NEXT: movt r0, #65280643; CHECK-NEXT: vdup.32 q0, r0644; CHECK-NEXT: bx lr645entry:646 ret <4 x i32> <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>647}648 649define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278190335(<4 x i32> %a) {650; CHECKLE-LABEL: xor_int32_4278190335:651; CHECKLE: @ %bb.0: @ %entry652; CHECKLE-NEXT: movs r0, #255653; CHECKLE-NEXT: movt r0, #65280654; CHECKLE-NEXT: vdup.32 q1, r0655; CHECKLE-NEXT: veor q0, q0, q1656; CHECKLE-NEXT: bx lr657;658; CHECKBE-LABEL: xor_int32_4278190335:659; CHECKBE: @ %bb.0: @ %entry660; CHECKBE-NEXT: movs r0, #255661; CHECKBE-NEXT: vrev64.32 q1, q0662; CHECKBE-NEXT: movt r0, #65280663; CHECKBE-NEXT: vdup.32 q0, r0664; CHECKBE-NEXT: veor q1, q1, q0665; CHECKBE-NEXT: vrev64.32 q0, q1666; CHECKBE-NEXT: bx lr667entry:668 %b = xor <4 x i32> %a, <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>669 ret <4 x i32> %b670}671 672define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() {673; CHECK-LABEL: mov_int32_4278255615:674; CHECK: @ %bb.0: @ %entry675; CHECK-NEXT: vmvn.i32 q0, #0xff0000676; CHECK-NEXT: bx lr677entry:678 ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>679}680 681define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278255615(<4 x i32> %a) {682; CHECKLE-LABEL: xor_int32_4278255615:683; CHECKLE: @ %bb.0: @ %entry684; CHECKLE-NEXT: vmvn.i32 q1, #0xff0000685; CHECKLE-NEXT: veor q0, q0, q1686; CHECKLE-NEXT: bx lr687;688; CHECKBE-LABEL: xor_int32_4278255615:689; CHECKBE: @ %bb.0: @ %entry690; CHECKBE-NEXT: vmvn.i32 q1, #0xff0000691; CHECKBE-NEXT: vrev64.32 q2, q0692; CHECKBE-NEXT: veor q1, q2, q1693; CHECKBE-NEXT: vrev64.32 q0, q1694; CHECKBE-NEXT: bx lr695entry:696 %b = xor <4 x i32> %a, <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>697 ret <4 x i32> %b698}699 700define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {701; CHECK-LABEL: mov_int32_16908546:702; CHECK: @ %bb.0: @ %entry703; CHECK-NEXT: mov.w r0, #258704; CHECK-NEXT: vdup.16 q0, r0705; CHECK-NEXT: bx lr706entry:707 ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>708}709 710define arm_aapcs_vfpcc <4 x i32> @xor_int32_16908546(<4 x i32> %a) {711; CHECKLE-LABEL: xor_int32_16908546:712; CHECKLE: @ %bb.0: @ %entry713; CHECKLE-NEXT: mov.w r0, #258714; CHECKLE-NEXT: vdup.16 q1, r0715; CHECKLE-NEXT: veor q0, q0, q1716; CHECKLE-NEXT: bx lr717;718; CHECKBE-LABEL: xor_int32_16908546:719; CHECKBE: @ %bb.0: @ %entry720; CHECKBE-NEXT: mov.w r0, #258721; CHECKBE-NEXT: vrev64.32 q2, q0722; CHECKBE-NEXT: vdup.16 q1, r0723; CHECKBE-NEXT: veor q1, q2, q1724; CHECKBE-NEXT: vrev64.32 q0, q1725; CHECKBE-NEXT: bx lr726entry:727 %b = xor <4 x i32> %a, <i32 16908546, i32 16908546, i32 16908546, i32 16908546>728 ret <4 x i32> %b729}730 731define arm_aapcs_vfpcc <4 x i32> @mov_int32_64() {732; CHECKLE-LABEL: mov_int32_64:733; CHECKLE: @ %bb.0: @ %entry734; CHECKLE-NEXT: vmov.i64 q0, #0xff00ffff00ff00735; CHECKLE-NEXT: bx lr736;737; CHECKBE-LABEL: mov_int32_64:738; CHECKBE: @ %bb.0: @ %entry739; CHECKBE-NEXT: vmov.i64 q0, #0xff00ff0000ff00ff740; CHECKBE-NEXT: bx lr741entry:742 ret <4 x i32> <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>743}744 745define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {746; CHECKLE-LABEL: xor_int32_64:747; CHECKLE: @ %bb.0: @ %entry748; CHECKLE-NEXT: vmov.i64 q1, #0xff00ffff00ff00749; CHECKLE-NEXT: veor q0, q0, q1750; CHECKLE-NEXT: bx lr751;752; CHECKBE-LABEL: xor_int32_64:753; CHECKBE: @ %bb.0: @ %entry754; CHECKBE-NEXT: vmov.i64 q1, #0xff00ffff00ff00755; CHECKBE-NEXT: vrev64.32 q2, q0756; CHECKBE-NEXT: veor q1, q2, q1757; CHECKBE-NEXT: vrev64.32 q0, q1758; CHECKBE-NEXT: bx lr759entry:760 %b = xor <4 x i32> %a, <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>761 ret <4 x i32> %b762}763 764define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {765; CHECKLE-LABEL: mov_int64_1:766; CHECKLE: @ %bb.0: @ %entry767; CHECKLE-NEXT: adr r0, .LCPI50_0768; CHECKLE-NEXT: vldrw.u32 q0, [r0]769; CHECKLE-NEXT: bx lr770; CHECKLE-NEXT: .p2align 4771; CHECKLE-NEXT: @ %bb.1:772; CHECKLE-NEXT: .LCPI50_0:773; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324774; CHECKLE-NEXT: .long 0775; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324776; CHECKLE-NEXT: .long 0777;778; CHECKBE-LABEL: mov_int64_1:779; CHECKBE: @ %bb.0: @ %entry780; CHECKBE-NEXT: adr r0, .LCPI50_0781; CHECKBE-NEXT: vldrb.u8 q1, [r0]782; CHECKBE-NEXT: vrev64.8 q0, q1783; CHECKBE-NEXT: bx lr784; CHECKBE-NEXT: .p2align 4785; CHECKBE-NEXT: @ %bb.1:786; CHECKBE-NEXT: .LCPI50_0:787; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324788; CHECKBE-NEXT: .long 1789; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324790; CHECKBE-NEXT: .long 1791entry:792 ret <2 x i64> <i64 1, i64 1>793}794 795define arm_aapcs_vfpcc <2 x i64> @xor_int64_1(<2 x i64> %a) {796; CHECKLE-LABEL: xor_int64_1:797; CHECKLE: @ %bb.0: @ %entry798; CHECKLE-NEXT: adr r0, .LCPI51_0799; CHECKLE-NEXT: vldrw.u32 q1, [r0]800; CHECKLE-NEXT: veor q0, q0, q1801; CHECKLE-NEXT: bx lr802; CHECKLE-NEXT: .p2align 4803; CHECKLE-NEXT: @ %bb.1:804; CHECKLE-NEXT: .LCPI51_0:805; CHECKLE-NEXT: .long 1 @ 0x1806; CHECKLE-NEXT: .long 0 @ 0x0807; CHECKLE-NEXT: .long 1 @ 0x1808; CHECKLE-NEXT: .long 0 @ 0x0809;810; CHECKBE-LABEL: xor_int64_1:811; CHECKBE: @ %bb.0: @ %entry812; CHECKBE-NEXT: adr r0, .LCPI51_0813; CHECKBE-NEXT: vldrb.u8 q1, [r0]814; CHECKBE-NEXT: vrev64.8 q2, q1815; CHECKBE-NEXT: veor q0, q0, q2816; CHECKBE-NEXT: bx lr817; CHECKBE-NEXT: .p2align 4818; CHECKBE-NEXT: @ %bb.1:819; CHECKBE-NEXT: .LCPI51_0:820; CHECKBE-NEXT: .long 0 @ 0x0821; CHECKBE-NEXT: .long 1 @ 0x1822; CHECKBE-NEXT: .long 0 @ 0x0823; CHECKBE-NEXT: .long 1 @ 0x1824entry:825 %b = xor <2 x i64> %a, <i64 1, i64 1>826 ret <2 x i64> %b827}828 829define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() {830; CHECK-LABEL: mov_int64_ff:831; CHECK: @ %bb.0: @ %entry832; CHECK-NEXT: vmov.i64 q0, #0xff833; CHECK-NEXT: bx lr834entry:835 ret <2 x i64> <i64 255, i64 255>836}837 838define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff(<2 x i64> %a) {839; CHECKLE-LABEL: xor_int64_ff:840; CHECKLE: @ %bb.0: @ %entry841; CHECKLE-NEXT: vmov.i64 q1, #0xff842; CHECKLE-NEXT: veor q0, q0, q1843; CHECKLE-NEXT: bx lr844;845; CHECKBE-LABEL: xor_int64_ff:846; CHECKBE: @ %bb.0: @ %entry847; CHECKBE-NEXT: vmov.i64 q1, #0xff00000000848; CHECKBE-NEXT: vrev64.32 q2, q1849; CHECKBE-NEXT: veor q0, q0, q2850; CHECKBE-NEXT: bx lr851entry:852 %b = xor <2 x i64> %a, <i64 255, i64 255>853 ret <2 x i64> %b854}855 856define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {857; CHECK-LABEL: mov_int64_m1:858; CHECK: @ %bb.0: @ %entry859; CHECK-NEXT: vmov.i8 q0, #0xff860; CHECK-NEXT: bx lr861entry:862 ret <2 x i64> <i64 -1, i64 -1>863}864 865define arm_aapcs_vfpcc <2 x i64> @xor_int64_m1(<2 x i64> %a) {866; CHECKLE-LABEL: xor_int64_m1:867; CHECKLE: @ %bb.0: @ %entry868; CHECKLE-NEXT: vmvn q0, q0869; CHECKLE-NEXT: bx lr870;871; CHECKBE-LABEL: xor_int64_m1:872; CHECKBE: @ %bb.0: @ %entry873; CHECKBE-NEXT: vmov.i8 q1, #0xff874; CHECKBE-NEXT: veor q0, q0, q1875; CHECKBE-NEXT: bx lr876entry:877 %b = xor <2 x i64> %a, <i64 -1, i64 -1>878 ret <2 x i64> %b879}880 881define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {882; CHECK-LABEL: mov_int64_ff0000ff0000ffff:883; CHECK: @ %bb.0: @ %entry884; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff885; CHECK-NEXT: bx lr886entry:887 ret <2 x i64> <i64 18374687574888349695, i64 18374687574888349695>888}889 890define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff0000ff0000ffff(<2 x i64> %a) {891; CHECKLE-LABEL: xor_int64_ff0000ff0000ffff:892; CHECKLE: @ %bb.0: @ %entry893; CHECKLE-NEXT: vmov.i64 q1, #0xff0000ff0000ffff894; CHECKLE-NEXT: veor q0, q0, q1895; CHECKLE-NEXT: bx lr896;897; CHECKBE-LABEL: xor_int64_ff0000ff0000ffff:898; CHECKBE: @ %bb.0: @ %entry899; CHECKBE-NEXT: vmov.i64 q1, #0xffffff0000ff900; CHECKBE-NEXT: vrev64.32 q2, q1901; CHECKBE-NEXT: veor q0, q0, q2902; CHECKBE-NEXT: bx lr903entry:904 %b = xor <2 x i64> %a, <i64 18374687574888349695, i64 18374687574888349695>905 ret <2 x i64> %b906}907 908define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {909; CHECKLE-LABEL: mov_int64_f_0:910; CHECKLE: @ %bb.0: @ %entry911; CHECKLE-NEXT: adr r0, .LCPI58_0912; CHECKLE-NEXT: vldrw.u32 q0, [r0]913; CHECKLE-NEXT: bx lr914; CHECKLE-NEXT: .p2align 4915; CHECKLE-NEXT: @ %bb.1:916; CHECKLE-NEXT: .LCPI58_0:917; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321918; CHECKLE-NEXT: .long 0919; CHECKLE-NEXT: .long 0 @ double 0920; CHECKLE-NEXT: .long 0921;922; CHECKBE-LABEL: mov_int64_f_0:923; CHECKBE: @ %bb.0: @ %entry924; CHECKBE-NEXT: adr r0, .LCPI58_0925; CHECKBE-NEXT: vldrb.u8 q1, [r0]926; CHECKBE-NEXT: vrev64.8 q0, q1927; CHECKBE-NEXT: bx lr928; CHECKBE-NEXT: .p2align 4929; CHECKBE-NEXT: @ %bb.1:930; CHECKBE-NEXT: .LCPI58_0:931; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321932; CHECKBE-NEXT: .long 255933; CHECKBE-NEXT: .long 0 @ double 0934; CHECKBE-NEXT: .long 0935entry:936 ret <2 x i64> <i64 255, i64 0>937}938 939define arm_aapcs_vfpcc <2 x i64> @xor_int64_f_0(<2 x i64> %a) {940; CHECKLE-LABEL: xor_int64_f_0:941; CHECKLE: @ %bb.0: @ %entry942; CHECKLE-NEXT: adr r0, .LCPI59_0943; CHECKLE-NEXT: vldrw.u32 q1, [r0]944; CHECKLE-NEXT: veor q0, q0, q1945; CHECKLE-NEXT: bx lr946; CHECKLE-NEXT: .p2align 4947; CHECKLE-NEXT: @ %bb.1:948; CHECKLE-NEXT: .LCPI59_0:949; CHECKLE-NEXT: .long 255 @ 0xff950; CHECKLE-NEXT: .long 0 @ 0x0951; CHECKLE-NEXT: .long 0 @ 0x0952; CHECKLE-NEXT: .long 0 @ 0x0953;954; CHECKBE-LABEL: xor_int64_f_0:955; CHECKBE: @ %bb.0: @ %entry956; CHECKBE-NEXT: adr r0, .LCPI59_0957; CHECKBE-NEXT: vldrb.u8 q1, [r0]958; CHECKBE-NEXT: vrev64.8 q2, q1959; CHECKBE-NEXT: veor q0, q0, q2960; CHECKBE-NEXT: bx lr961; CHECKBE-NEXT: .p2align 4962; CHECKBE-NEXT: @ %bb.1:963; CHECKBE-NEXT: .LCPI59_0:964; CHECKBE-NEXT: .long 0 @ 0x0965; CHECKBE-NEXT: .long 255 @ 0xff966; CHECKBE-NEXT: .long 0 @ 0x0967; CHECKBE-NEXT: .long 0 @ 0x0968entry:969 %b = xor <2 x i64> %a, <i64 255, i64 0>970 ret <2 x i64> %b971}972 973define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() {974; CHECKLE-LABEL: mov_int64_0f000f0f:975; CHECKLE: @ %bb.0: @ %entry976; CHECKLE-NEXT: vmov.i64 q0, #0xff000000ff00ff977; CHECKLE-NEXT: bx lr978;979; CHECKBE-LABEL: mov_int64_0f000f0f:980; CHECKBE: @ %bb.0: @ %entry981; CHECKBE-NEXT: vmov.i64 q0, #0xff00ff000000ff00982; CHECKBE-NEXT: bx lr983entry:984 ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>985}986 987define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {988; CHECKLE-LABEL: xor_int64_0f000f0f:989; CHECKLE: @ %bb.0: @ %entry990; CHECKLE-NEXT: vmov.i64 q1, #0xff000000ff00ff991; CHECKLE-NEXT: veor q0, q0, q1992; CHECKLE-NEXT: bx lr993;994; CHECKBE-LABEL: xor_int64_0f000f0f:995; CHECKBE: @ %bb.0: @ %entry996; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff997; CHECKBE-NEXT: vrev64.8 q2, q0998; CHECKBE-NEXT: veor q1, q2, q1999; CHECKBE-NEXT: vrev64.8 q0, q11000; CHECKBE-NEXT: bx lr1001entry:1002 %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>1003 ret <16 x i8> %b1004}1005 1006define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() {1007; CHECKLE-LABEL: mov_int64_ff00ffff:1008; CHECKLE: @ %bb.0: @ %entry1009; CHECKLE-NEXT: vmov.i64 q0, #0xffffffff0000ffff1010; CHECKLE-NEXT: bx lr1011;1012; CHECKBE-LABEL: mov_int64_ff00ffff:1013; CHECKBE: @ %bb.0: @ %entry1014; CHECKBE-NEXT: vmov.i64 q0, #0xffff0000ffffffff1015; CHECKBE-NEXT: bx lr1016entry:1017 ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>1018}1019 1020define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {1021; CHECKLE-LABEL: xor_int64_ff00ffff:1022; CHECKLE: @ %bb.0: @ %entry1023; CHECKLE-NEXT: vmov.i64 q1, #0xffffffff0000ffff1024; CHECKLE-NEXT: veor q0, q0, q11025; CHECKLE-NEXT: bx lr1026;1027; CHECKBE-LABEL: xor_int64_ff00ffff:1028; CHECKBE: @ %bb.0: @ %entry1029; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff1030; CHECKBE-NEXT: vrev64.16 q2, q01031; CHECKBE-NEXT: veor q1, q2, q11032; CHECKBE-NEXT: vrev64.16 q0, q11033; CHECKBE-NEXT: bx lr1034entry:1035 %b = xor <8 x i16> %a, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>1036 ret <8 x i16> %b1037}1038 1039define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {1040; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:1041; CHECKLE: @ %bb.0: @ %entry1042; CHECKLE-NEXT: vmov.i16 q0, #0xff1043; CHECKLE-NEXT: bx lr1044;1045; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:1046; CHECKBE: @ %bb.0: @ %entry1047; CHECKBE-NEXT: vmov.i16 q0, #0xff001048; CHECKBE-NEXT: bx lr1049entry:1050 ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>1051}1052 1053define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {1054; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:1055; CHECKLE: @ %bb.0: @ %entry1056; CHECKLE-NEXT: vmov.i16 q1, #0xff1057; CHECKLE-NEXT: veor q0, q0, q11058; CHECKLE-NEXT: bx lr1059;1060; CHECKBE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:1061; CHECKBE: @ %bb.0: @ %entry1062; CHECKBE-NEXT: vmov.i16 q1, #0xff1063; CHECKBE-NEXT: vrev64.8 q2, q01064; CHECKBE-NEXT: veor q1, q2, q11065; CHECKBE-NEXT: vrev64.8 q0, q11066; CHECKBE-NEXT: bx lr1067entry:1068 %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>1069 ret <16 x i8> %b1070}1071 1072define arm_aapcs_vfpcc <4 x float> @mov_float_1() {1073; CHECK-LABEL: mov_float_1:1074; CHECK: @ %bb.0: @ %entry1075; CHECK-NEXT: mov.w r0, #10653532161076; CHECK-NEXT: vdup.32 q0, r01077; CHECK-NEXT: bx lr1078entry:1079 ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>1080}1081 1082define arm_aapcs_vfpcc <4 x float> @fadd_float_1(<4 x float> %a) {1083; CHECKBE-LABEL: fadd_float_1:1084; CHECKBE: @ %bb.0: @ %entry1085; CHECKBE-NEXT: vmov.f32 q1, #1.000000e+001086; CHECKBE-NEXT: vrev64.32 q2, q01087; CHECKBE-NEXT: vadd.f32 q1, q2, q11088; CHECKBE-NEXT: vrev64.32 q0, q11089; CHECKBE-NEXT: bx lr1090entry:1091 %b = fadd <4 x float> %a, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>1092 ret <4 x float> %b1093}1094 1095define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {1096; CHECK-LABEL: mov_float_m3:1097; CHECK: @ %bb.0: @ %entry1098; CHECK-NEXT: movs r0, #01099; CHECK-NEXT: movt r0, #492161100; CHECK-NEXT: vdup.32 q0, r01101; CHECK-NEXT: bx lr1102entry:1103 ret <4 x float> <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>1104}1105 1106define arm_aapcs_vfpcc <4 x float> @fadd_float_m3(<4 x float> %a) {1107; CHECKBE-LABEL: fadd_float_m3:1108; CHECKBE: @ %bb.0: @ %entry1109; CHECKBE-NEXT: vmov.f32 q1, #-3.000000e+001110; CHECKBE-NEXT: vrev64.32 q2, q01111; CHECKBE-NEXT: vadd.f32 q1, q2, q11112; CHECKBE-NEXT: vrev64.32 q0, q11113; CHECKBE-NEXT: bx lr1114entry:1115 %b = fadd <4 x float> %a, <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>1116 ret <4 x float> %b1117}1118 1119define arm_aapcs_vfpcc <8 x half> @mov_float16_1() {1120; CHECK-LABEL: mov_float16_1:1121; CHECK: @ %bb.0: @ %entry1122; CHECK-NEXT: vmov.i16 q0, #0x3c001123; CHECK-NEXT: bx lr1124entry:1125 ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>1126}1127 1128define arm_aapcs_vfpcc <8 x half> @fadd_float16_1(<8 x half> %a) {1129; CHECKBE-LABEL: fadd_float16_1:1130; CHECKBE: @ %bb.0: @ %entry1131; CHECKBE-NEXT: vmov.i16 q1, #0x3c001132; CHECKBE-NEXT: vrev64.16 q2, q01133; CHECKBE-NEXT: vadd.f16 q1, q2, q11134; CHECKBE-NEXT: vrev64.16 q0, q11135; CHECKBE-NEXT: bx lr1136entry:1137 %b = fadd <8 x half> %a, <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>1138 ret <8 x half> %b1139}1140 1141define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() {1142; CHECK-LABEL: mov_float16_m3:1143; CHECK: @ %bb.0: @ %entry1144; CHECK-NEXT: vmov.i16 q0, #0xc2001145; CHECK-NEXT: bx lr1146entry:1147 ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>1148}1149 1150define arm_aapcs_vfpcc <8 x half> @fadd_float16_m3(<8 x half> %a) {1151; CHECKBE-LABEL: fadd_float16_m3:1152; CHECKBE: @ %bb.0: @ %entry1153; CHECKBE-NEXT: vmov.i16 q1, #0xc2001154; CHECKBE-NEXT: vrev64.16 q2, q01155; CHECKBE-NEXT: vadd.f16 q1, q2, q11156; CHECKBE-NEXT: vrev64.16 q0, q11157; CHECKBE-NEXT: bx lr1158entry:1159 %b = fadd <8 x half> %a, <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>1160 ret <8 x half> %b1161}1162 1163define arm_aapcs_vfpcc <2 x double> @mov_double_1() {1164; CHECKLE-LABEL: mov_double_1:1165; CHECKLE: @ %bb.0: @ %entry1166; CHECKLE-NEXT: adr r0, .LCPI74_01167; CHECKLE-NEXT: vldrw.u32 q0, [r0]1168; CHECKLE-NEXT: bx lr1169; CHECKLE-NEXT: .p2align 41170; CHECKLE-NEXT: @ %bb.1:1171; CHECKLE-NEXT: .LCPI74_0:1172; CHECKLE-NEXT: .long 0 @ double 11173; CHECKLE-NEXT: .long 10726932481174; CHECKLE-NEXT: .long 0 @ double 11175; CHECKLE-NEXT: .long 10726932481176;1177; CHECKBE-LABEL: mov_double_1:1178; CHECKBE: @ %bb.0: @ %entry1179; CHECKBE-NEXT: adr r0, .LCPI74_01180; CHECKBE-NEXT: vldrb.u8 q1, [r0]1181; CHECKBE-NEXT: vrev64.8 q0, q11182; CHECKBE-NEXT: bx lr1183; CHECKBE-NEXT: .p2align 41184; CHECKBE-NEXT: @ %bb.1:1185; CHECKBE-NEXT: .LCPI74_0:1186; CHECKBE-NEXT: .long 1072693248 @ double 11187; CHECKBE-NEXT: .long 01188; CHECKBE-NEXT: .long 1072693248 @ double 11189; CHECKBE-NEXT: .long 01190entry:1191 ret <2 x double> <double 1.000000e+00, double 1.000000e+00>1192}1193 1194define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) {1195; CHECKLE-LABEL: test:1196; CHECKLE: @ %bb.0: @ %entry1197; CHECKLE-NEXT: vmov.i64 q1, #0xff000000ff00ff1198; CHECKLE-NEXT: vorr q0, q0, q11199; CHECKLE-NEXT: bx lr1200;1201; CHECKBE-LABEL: test:1202; CHECKBE: @ %bb.0: @ %entry1203; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff1204; CHECKBE-NEXT: vrev64.8 q2, q01205; CHECKBE-NEXT: vorr q1, q2, q11206; CHECKBE-NEXT: vrev64.8 q0, q11207; CHECKBE-NEXT: bx lr1208entry:1209 %o = or <16 x i8> %i, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>1210 ret <16 x i8> %o1211}1212 1213define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {1214; CHECKLE-LABEL: test2:1215; CHECKLE: @ %bb.0: @ %entry1216; CHECKLE-NEXT: vmov.i64 q1, #0xffffffff0000ffff1217; CHECKLE-NEXT: vorr q0, q0, q11218; CHECKLE-NEXT: bx lr1219;1220; CHECKBE-LABEL: test2:1221; CHECKBE: @ %bb.0: @ %entry1222; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff1223; CHECKBE-NEXT: vrev64.16 q2, q01224; CHECKBE-NEXT: vorr q1, q2, q11225; CHECKBE-NEXT: vrev64.16 q0, q11226; CHECKBE-NEXT: bx lr1227entry:1228 %o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>1229 ret <8 x i16> %o1230}1231 1232define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {1233; CHECKLE-LABEL: i1and_vmov:1234; CHECKLE: @ %bb.0: @ %entry1235; CHECKLE-NEXT: cmp r0, #01236; CHECKLE-NEXT: mov.w r1, #151237; CHECKLE-NEXT: csetm r0, eq1238; CHECKLE-NEXT: ands r0, r11239; CHECKLE-NEXT: vmsr p0, r01240; CHECKLE-NEXT: vpsel q0, q0, q11241; CHECKLE-NEXT: bx lr1242;1243; CHECKBE-LABEL: i1and_vmov:1244; CHECKBE: @ %bb.0: @ %entry1245; CHECKBE-NEXT: cmp r0, #01246; CHECKBE-NEXT: mov.w r1, #151247; CHECKBE-NEXT: csetm r0, eq1248; CHECKBE-NEXT: vrev64.32 q2, q11249; CHECKBE-NEXT: ands r0, r11250; CHECKBE-NEXT: vrev64.32 q1, q01251; CHECKBE-NEXT: vmsr p0, r01252; CHECKBE-NEXT: vpsel q1, q1, q21253; CHECKBE-NEXT: vrev64.32 q0, q11254; CHECKBE-NEXT: bx lr1255entry:1256 %c1 = icmp eq i32 %c, zeroinitializer1257 %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 01258 %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer1259 %l699 = and <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>1260 %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b1261 ret <4 x i32> %s1262}1263 1264define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {1265; CHECKLE-LABEL: i1or_vmov:1266; CHECKLE: @ %bb.0: @ %entry1267; CHECKLE-NEXT: cmp r0, #01268; CHECKLE-NEXT: mov.w r1, #151269; CHECKLE-NEXT: csetm r0, eq1270; CHECKLE-NEXT: orrs r0, r11271; CHECKLE-NEXT: vmsr p0, r01272; CHECKLE-NEXT: vpsel q0, q0, q11273; CHECKLE-NEXT: bx lr1274;1275; CHECKBE-LABEL: i1or_vmov:1276; CHECKBE: @ %bb.0: @ %entry1277; CHECKBE-NEXT: cmp r0, #01278; CHECKBE-NEXT: mov.w r1, #151279; CHECKBE-NEXT: csetm r0, eq1280; CHECKBE-NEXT: vrev64.32 q2, q11281; CHECKBE-NEXT: orrs r0, r11282; CHECKBE-NEXT: vrev64.32 q1, q01283; CHECKBE-NEXT: vmsr p0, r01284; CHECKBE-NEXT: vpsel q1, q1, q21285; CHECKBE-NEXT: vrev64.32 q0, q11286; CHECKBE-NEXT: bx lr1287entry:1288 %c1 = icmp eq i32 %c, zeroinitializer1289 %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 01290 %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer1291 %l699 = or <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>1292 %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b1293 ret <4 x i32> %s1294}1295 1296define arm_aapcs_vfpcc <2 x i64> @v2i1and_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {1297; CHECK-LABEL: v2i1and_vmov:1298; CHECK: @ %bb.0: @ %entry1299; CHECK-NEXT: cmp r0, #01300; CHECK-NEXT: mov.w r1, #01301; CHECK-NEXT: csetm r0, eq1302; CHECK-NEXT: bfi r1, r0, #0, #81303; CHECK-NEXT: vmsr p0, r11304; CHECK-NEXT: vpsel q0, q0, q11305; CHECK-NEXT: bx lr1306entry:1307 %c1 = icmp eq i32 %c, zeroinitializer1308 %broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 01309 %broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer1310 %l699 = and <2 x i1> %broadcast.splat1968, <i1 true, i1 false>1311 %s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b1312 ret <2 x i64> %s1313}1314 1315define arm_aapcs_vfpcc <2 x i64> @v2i1or_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {1316; CHECK-LABEL: v2i1or_vmov:1317; CHECK: @ %bb.0: @ %entry1318; CHECK-NEXT: cmp r0, #01319; CHECK-NEXT: mov.w r1, #2551320; CHECK-NEXT: csetm r0, eq1321; CHECK-NEXT: bfi r1, r0, #8, #81322; CHECK-NEXT: vmsr p0, r11323; CHECK-NEXT: vpsel q0, q0, q11324; CHECK-NEXT: bx lr1325entry:1326 %c1 = icmp eq i32 %c, zeroinitializer1327 %broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 01328 %broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer1329 %l699 = or <2 x i1> %broadcast.splat1968, <i1 true, i1 false>1330 %s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b1331 ret <2 x i64> %s1332}1333 1334define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {1335; CHECKLE-LABEL: and_v8i16_m1:1336; CHECKLE: @ %bb.0:1337; CHECKLE-NEXT: vbic.i32 q0, #0x100001338; CHECKLE-NEXT: bx lr1339;1340; CHECKBE-LABEL: and_v8i16_m1:1341; CHECKBE: @ %bb.0:1342; CHECKBE-NEXT: vrev64.16 q1, q01343; CHECKBE-NEXT: vbic.i32 q1, #0x100001344; CHECKBE-NEXT: vrev64.16 q0, q11345; CHECKBE-NEXT: bx lr1346 %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>1347 ret <8 x i16> %b1348}1349 1350define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {1351; CHECKLE-LABEL: or_v8i16_1:1352; CHECKLE: @ %bb.0:1353; CHECKLE-NEXT: vorr.i32 q0, #0x100001354; CHECKLE-NEXT: bx lr1355;1356; CHECKBE-LABEL: or_v8i16_1:1357; CHECKBE: @ %bb.0:1358; CHECKBE-NEXT: vrev64.16 q1, q01359; CHECKBE-NEXT: vorr.i32 q1, #0x100001360; CHECKBE-NEXT: vrev64.16 q0, q11361; CHECKBE-NEXT: bx lr1362 %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>1363 ret <8 x i16> %b1364}1365